JP3479625B2 - Multi-stage low noise amplifier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multistage low noise amplifier, and more particularly to a multistage low noise amplifier on the receiving side in television broadcasting, mobile radio communication and the like.

[0002]

2. Description of the Related Art FIG. 20 is a block diagram showing a schematic configuration of an example of a receiving side of a base station for mobile communication or a relay broadcasting apparatus for TV broadcasting. In the figure, 101 is a receiving antenna, 102 is a wide band pass filter, 103 is a low noise amplifier, 104 _{1 to} 104 _n are narrow band pass filters, 1
05 ₁ to 105 _n are receiver. As shown in the figure,
A low noise amplifier (LNA) 103 for amplifying a minute high-frequency signal received by a receiving antenna 101 is provided on the receiving side of a base station for mobile communication or a relay broadcasting apparatus for TV broadcasting.
Is provided. FIG. 21 shows the low noise amplifier 1 shown in FIG.
10 is a block diagram showing an example of a conventional circuit configuration of 03.
In the figure, 111 is a circulator (isolator), 112 is a low-noise amplifier circuit in the first stage, 113 is a low-noise amplifier circuit in the next stage, and R is a non-reflection terminator. Here, the first-stage low noise amplifier circuit 112 and the next stage of the low noise amplifier circuit 113, as an amplifying element, HEMT (H igh E lectron
M obility T ransistor; high electron mobility transistor) devices, or, GaAsFET elements are used.

[0003]

[0007] Low noise amplifier circuit shown in FIG. 21 112, noise figure; but (NF N oise F igure) is designed to be best, therefore, that a large input voltage reflection coefficient There's a problem. In order to solve this problem, in the low noise amplifier 103 shown in FIG. 21, a circulator (isolator) is provided before the low noise amplifier circuit 112.
111 is inserted, the high-frequency signal reflected by the low-noise amplifier circuit 112 is absorbed by the non-reflective terminator R, and the low-noise amplifier circuit 1
The high frequency signal reflected by 12 is prevented from returning to the receiving antenna 101. However, the low noise amplifier 103 shown in FIG. 21 has a problem that the noise figure (NF) is deteriorated by the insertion loss of the circulator 111 inserted in the signal path.

FIG. 22 shows the low noise amplifier 10 shown in FIG.
3 is a block diagram showing a conventional circuit configuration of another example of FIG.
As shown in the figure, the low noise amplifier 103 shown in FIG.
Is that a hybrid circuit 10 for branching, a hybrid circuit 12 for combining, and first and second low noise amplifier circuits (11 ₁ , 11 ₂ ) are provided in the preceding stage of the low noise amplifier circuit 113. 21 is different from the conventional low noise amplifier 103 shown in FIG. Here, the first low noise amplifier circuit 11 ₁ is connected between the second terminal T ₁₂ of the branching hybrid circuit 10 and the first terminal T ₂₁ of the combining hybrid circuit 12, and The low-noise amplifier circuit 11 ₂ is connected between the third terminal T ₁₃ of the branching hybrid circuit 10 and the fourth terminal T ₂₄ of the combining hybrid circuit 12. Also,
A non-reflection terminator R is connected to the fourth terminal T ₁₄ of the branching hybrid circuit 10 and the second terminal T ₂₂ of the combining hybrid circuit 12. According to the low noise amplifier 103 shown in FIG. 22, the reflected power from the first and second low noise amplifier circuits (11 ₁ , 11 ₂ ) is output to the fourth terminal T ₁₄ of the hybrid circuit 10 for branching. As a result, the noise figure (NF) can be improved as compared with the low noise amplifier 103 shown in FIG.

However, in the low noise amplifier 103 shown in FIG. 22, the value of noise figure (NF) is 0.5 to 0.6 dB (NF = NF) when the frequency of the high frequency signal is 2 GHz.
There is a problem that the noise figure (NF) cannot be further improved because the limit is 0.5 to 0.6 dB; f = 2 GHz). Further, as shown in FIG. 21 and FIG. 22, the low-noise amplifier 103 having a two-stage configuration is illustrated. The conventional low-noise amplifier 103 is composed of a multi-stage amplifier in which low-noise amplifier circuits are cascade-connected. However, in such a multi-stage amplifier, unless the intersection point (IP) and the voltage amplification degree (G _V ) of each low noise amplifier circuit are optimized, the linearity or
There is a problem that the intermodulation wave (IM) characteristic is deteriorated. The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a multistage low noise amplifier capable of improving the noise figure (NF) as compared with the prior art. Especially. Another object of the present invention is to provide a multistage low noise amplifier capable of improving linearity or intermodulation wave (IM) characteristics. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0006]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows. That is, the present invention is a multi-stage low noise amplifier configured by cascade-connecting n low noise amplifiers, the intercept of the k (k = 1, 2, ..., N-1) th low noise amplifier. The point is IP _k , the intercept point of the (k + 1) th low noise amplifier is IP _{k + 1} ,
Further, when the voltage amplification degree of the (k + 1) th low noise amplifier is G _{V (k + 1)} , 6 dB ≦ IP _k −IP _{k + 1} + G
It is characterized by satisfying _{V (k + 1)} . According to the above-mentioned means, the intercept point IP _{k + 1} of the (k + 1) th low noise amplifier is obtained by the design requirement value obtained by the specification standard and the intercept of the _kth low noise amplifier is satisfied so as to satisfy the above expression. Since the point IP _K is set, a low noise amplifier with good linearity can be obtained.

Further, according to the present invention, the first low noise amplifier, the second low noise amplifier, and the isolator provided between the first low noise amplifier and the second low noise amplifier are cascaded. A multistage low noise amplifier configured by being connected, wherein the first low noise amplifier is a first hybrid circuit to which an input signal is applied to a first terminal,
A first low noise amplifier circuit having an input terminal connected to the second terminal of the first hybrid circuit; and a second low noise amplifier circuit having an input terminal connected to the third terminal of the first hybrid circuit. A low noise amplification circuit and a first terminal are connected to an output terminal of the first low noise amplification circuit, and a fourth terminal is connected to an output terminal of the second low noise amplification circuit, A third terminal is constituted by a second hybrid circuit connected to the first terminal of the isolator, and
When the intercept point of the _first low noise amplifier is IP ₁ , the intercept point of the second low noise amplifier is IP ₂ , and the voltage amplification degree of the second low noise amplifier is G _V2 , 6 dB ≦ IP ₁ -IP ₂ +
It is characterized by satisfying G _V2 .

The present invention is also a multi-stage low noise amplifier configured by cascading a first low noise amplifier and a second low noise amplifier, wherein the first low noise amplifier is A first hybrid circuit having an input signal applied to a first terminal, a first low noise amplifier circuit having an input terminal connected to a second terminal of the first hybrid circuit, and an input terminal A second low noise amplifying circuit connected to a third terminal of the first hybrid circuit; and a first terminal connected to an output terminal of the first low noise amplifying circuit,
The fourth terminal is configured with a second hybrid circuit connected to the output terminal of the second low noise amplification circuit, and the second low noise amplifier has a first terminal connected to the second hybrid circuit. A third hybrid circuit connected to the third terminal of the hybrid circuit; and a third low noise amplifier circuit having an input terminal connected to the second terminal of the third hybrid circuit,
A fourth low noise amplifier circuit having an input terminal connected to a third terminal of the third hybrid circuit; and a first terminal,
Connected to an output terminal of the third low noise amplifier circuit,
Is connected to the output terminal of the fourth low-noise amplifier circuit, and the intercept point of the first low-noise amplifier is I
When P ₁ , the intercept point of the second low noise amplifier is IP ₂ , and the voltage amplification degree of the second low noise amplifier is G _V2 , 6 dB ≦ IP ₁ −IP ₂ + G
It is characterized by satisfying _V2 .

Further, the present invention is a multi-stage low noise amplifier configured by cascading a first low noise amplifier and a second low noise amplifier, wherein the first low noise amplifier is A first hybrid circuit having an input signal applied to a first terminal, a first low noise amplifier circuit having an input terminal connected to a second terminal of the first hybrid circuit, and an input terminal A second low noise amplifying circuit connected to a third terminal of the first hybrid circuit; and a first terminal connected to an output terminal of the first low noise amplifying circuit,
The fourth terminal is composed of a second hybrid circuit connected to the output terminal of the second low noise amplifier circuit, and the second low noise amplifier is (2 ⁿ −1; n ≧ 2). Branching means for branching the amplified signal output from the third terminal of the second hybrid circuit into 2 ⁿ signals, and each of the branching means. It is composed of 2 ⁿ low-noise amplifier circuits for amplifying signals and (2 ⁿ -1) hybrid circuits, and combines the amplified signals output from the 2 ⁿ parallel low-noise amplifiers. And an intercept point of the _first low-noise amplifier is IP ₁ , an intercept point of the second low-noise amplifier is IP ₂ , and a voltage amplification of the second low-noise amplifier. and the degree G _V2 Rutoki, 6dB ≦ IP ₁ -I
It is characterized by satisfying P ₂ + G _V2 .

According to each of the above means, the reflected voltage at the second low noise amplifier is prevented from being reflected at the input end of the first low noise amplifier. In addition, the intercept point IP ₂ of the second low-noise amplifier can be obtained by a design requirement value obtained by a specification standard or the like, and the intercept point I of the first low-noise amplifier can be satisfied so as to satisfy the above expression.
Since P ₁ is set, a low noise amplifier with good linearity can be obtained.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are given to those having the same function, and the repeated description thereof will be omitted. [First Embodiment] FIG. 1 is a block diagram showing a schematic configuration of a low noise amplifier 103 according to a first embodiment of the present invention. As shown in the figure, the low noise amplifier 103 of the present embodiment
Is a circulator (isolator) between the hybrid circuit 12 for synthesis and the low-noise amplifier circuit 113 at the next stage.
22 is different from the conventional low noise amplifier 103 shown in FIG.

FIG. 2 is a diagram for explaining a hybrid circuit composed of a λ / 4/3 dB coupler. In the figure, assuming that each terminal other than the measurement terminal is terminated by a non-reflective terminator, the voltage reflection coefficient at each input terminal is zero,

[Number 1] becomes _{S 11 = S 22 = S 33} = S 44 = 0 ··············· (1). Terminate the terminals other than the measurement terminals with a non-reflective terminator,
Terminal _{(T 1 -T 2), (} T 2 -T 1), (T 3 -T 4), (T
₄ If -T ₃₎ for measuring the coupling coefficient between, it is possible to obtain the following formula (2).

[Number 2] _{S 12 = S 21 = S 34} = S 43 = jCsinθ / ((1-C 2) 1/2 · cosθ + jsinθ) = 1/2 1/2 = 0.707 ········ (2) However, C (coupling coefficient of hybrid circuit) = ^{1/2 1/2}
(= 0.707) and θ = 90 °.

In addition, the terminals other than the measurement terminals are non-reflective terminators.
End with a terminal (T₁-T₃), (T ₃-T₁), (T₂−
T_Four), (T_Four-T₂), The coupling coefficient between
Expression (3) can be obtained.

[Equation 3]   S₁₃= S₃₁= S_{twenty four}= S₄₂= (1-C²)^1/2/ ((1-C²)^1/2・ Cos θ + jsin θ)                         = -J / 2^1/2                           = -0.707 · j (3) However, C (coupling coefficient of hybrid circuit) = 1/2^1/2
(= 0.707) and θ = 90 °. Also, the measuring terminal
Terminals other than the₁−
T_Four), (T _Four-T₁), (T₂-T₃), (T₃-T₂)while
The following equation (4) can be obtained by measuring the coupling coefficient of
Wear.

Equation 4] _{S 14 = S 41 = S 23} = S 32 = 0 ··············· (4) using a relational expression of (1) to (4), When the [S] matrix of the hybrid circuit shown in FIG. 2 is obtained, it is expressed by the following equation (5).

[0014]

[Equation 5] The terminal T ₁ of the hybrid circuit shown in FIG. 2, upon application of an input voltage (Ein), the terminal T _2, T _3, the output voltage obtained from _{T 4 (E 11, E 12} , E 13, E 14) Is obtained by using the equation (5), the following equation (6) is obtained.

[0015]

[Equation 6]

As can be seen from the equation (6), the terminal T₂
Has Ein / 2^1/2(E₁₂= Ein / 2 ^1/2) Voltage is
Child T₃Includes -jEin / 2^1/2(E₁₃= -JEin /
Two^1/2) Voltage is obtained. FIG. 3 shows the present embodiment.
The first and second low noise amplifier circuits (11₁, 1
1₂) To explain the output destination of the high frequency signal reflected by
FIG. In FIG. 3, the first and second low noise increases
Width circuit (11₁, 11₂) Input voltage reflection coefficient
Γ₂, Γ₃Then, the terminal (T₁₂，
T₁₃) Reflected voltage (E_{Γ 2}, E_{Γ 3}) Is below
It is expressed by equation (7).

[0017]

[Equation 7]   E_{Γ 2}= Γ₂Ein / 2^1/2   E_{Γ 3}= -J Γ₃Ein / 2^1/2      (7) Using the equations (5) and (7), the hybrid circuit
Terminal (T₁₁, T₁₂, T ₁₃, T₁₄) Output voltage (E
₁, E₂, E₃, E_Four), The following equation (8) is obtained.
Become.

[0018]

[Equation 8]

As can be seen from the equation (8), the first and
And a second low noise amplifier circuit (11₁, 11₂) Input voltage reverse
Emissivity coefficient (Γ₂, Γ₃) Are equal to each other, and Γ (= Γ₂= Γ₃)
If so, the first terminal of the hybrid circuit 10 for branching
T₁₁Includes the first and second low noise amplifier circuits (11₁，
11₂), The reflected voltage reflected by
The fourth terminal T of the dead circuit 10.₁₄Only the first and second
Low noise amplifier circuit (11₁, 11₂) Reflected by
The combined voltage of pressure is output and absorbed by the non-reflective terminator R.
It In FIG. 3, the terminal (T₁₂, T₁₃) From each
Forced E₁₂(= Ein / 2 ^1/2), E₁₃(= -JEin /
Two^1/2) Voltage of the first and second low noise amplifier circuits
(11₁, 11₂), The first
And a second low noise amplifier circuit (11₁, 11₂) Is entered in
It Here, the first and second low noise amplifier circuits (1
1₁, 11₂The voltage input to) is expressed by the following equation (9).
Be done.

[0020]

E _12i = (1-Γ ² ) ^1/2 Ein / 2 ^1/2 E _13i = -j (1-Γ ² ) ^1/2 Ein / 2 ^1/2 ... (9) The voltage amplification degree (voltage gain) of the first and second low-noise amplification circuits (11 ₁ , 11 ₂ ) is G _v , and the noise output voltage is E _N1 , E _N2 , respectively. Then, the output voltage of the first and second low noise amplifier circuits (11 ₁ , 11 ₂ ) is expressed by the following equation (10).

[0021]

[Equation 10] E ₂₁₀ = G _v (1-Γ ² ) ^1/2 Ein / 2 ^1/2 + E _N1 E ₂₄₀ = −jG _v (1-Γ ² ) ^1/2 Ein / 2 ^1/2 + E _N2 · (10) FIG. 4 shows the output of the high-frequency signal input from the first and fourth terminals of the hybrid circuit 12 for synthesis in the present embodiment. It is a figure for explaining the destination. As shown in the figure, assuming that the voltage expressed by the equation (10) is applied to the first terminal T ₂₁ and the fourth terminal T ₂₄ of the hybrid circuit 12 for synthesis, the hybrid circuit 12 for synthesis is assumed.
The voltage output from the second terminal T ₂₂ and the third terminal T ₂₃ of the above is expressed by the following equation (11).

[0022]

[Equation 11] That is, in the constant impedance type low noise amplifier circuit shown in FIG.
Where the voltage reflection coefficient (Γ_in11, Γ_out23) Is that
0 (Γ_in11, Γ_out23= 0) and the terminal (T _{twenty two}, T
_{twenty three}) Output voltage is E_{twenty two}, E_{twenty three}Becomes here
Output voltage (E_{twenty two}, E_{twenty three}) Is expressed by the following equation (12).
Be done.

[0023]

[Equation 12]   E_{twenty two}= (E_N1-JE_N2) / 2^1/2    E_{twenty three}= -JG_v(1-Γ²)^1/2Ein + (E_N2-JE_N1) / 2^1/2                               (12) As can be seen from equation (12), the hybrid circuit for synthesis is
Second terminal T of path 12 _{twenty two}Is a composite high frequency signal output
However, the first and second low noise amplifier circuits (11₁，
11₂) Generated noise power (E_n1, E_N2)
Is output. In addition, the first hybrid circuit 12 for synthesis
3 terminals T_{twenty three}Are the combined wave of the signal voltage and the first and
2 low noise amplifier circuit (11₁, 11₂) Generated by noise
Power (E_n1, E_N2) Is output. Also, in FIG.
As shown, the noise amplification circuit 112 shown in FIG.
In the low noise amplifier to which the noise amplification circuit 113 is connected,
Output voltage E₃Is expressed by the following equation (13).

[0024]

[Equation 13] E ₃ = −jG _v1 G _V2 (1-Γ ₁ ² ) ^1/2 (1-Γ ₂ ² ) ^1/2 Ein + (E _N2 −jE _N1 ) (1-Γ ₂ ² ) ^{1 / 2/2 1/2} ............... (13) wherein, G _v1, the first and second low-noise amplifier circuit (1
1 ₁ , 11 ₂ ) voltage amplification factor, Γ ₁ is the voltage reflection coefficient of the first and second low noise amplifier circuits (11 ₁ , 11 ₂ ), G _v2
Is the voltage amplification factor of the low noise amplification circuit 113, and Γ ₂ is the voltage reflection coefficient of the low noise amplification circuit 113. Also, the third terminal T ₂₃ of the synthesis for hybrid circuit 12 shown in FIG. 6, the reflection of the low noise amplifier circuit 113, the following (14)
A reflected voltage E _P23 represented by the formula is generated.

[0025]

[Equation 14] E _P23 = (− jG _v1 (1-Γ ₁ ² ) ^1/2 Ein + (E _N2 −jE _N1 ) / 2 ^1/2 ) Γ ₂・ ・ ・ ・ ・ ・ ・ ・ ・ ・.. (14) When this reflected voltage E _P23 is applied to the third terminal T ₂₃ of the combining hybrid circuit 12, the first terminal T ₂₁ and the first terminal T _{24 of the} combining hybrid circuit 12 are applied. A reflected voltage (E _P21 , E _P24 ) represented by the following equation (15) is output to and.

[0026]

[Equation 15] E _P21 = Γ ₂ (−G _v1 (1−Γ ₁ ² ) ^1/2 Ein − (E _N1 −jE _N2 ) / 2 ^1/2 ) / 2 ^1/2 E _P24 = Γ ₂ (− ^{_{jG v1 (1-Γ 1 2}} ) 1/2 Ein + (E N2 -jE N1) 2 1/2) / 2 1/2 ··············· (15) the The reflected voltage (E _P21 , E _P24 ) is applied to the second branch of the branching hybrid circuit 10 by the coupling between the output terminal and the input terminal of the first and second low noise amplifier circuits (11 ₁ , 11 ₂ ). The voltage is applied to the terminal T ₁₂ and the third terminal T ₁₃ . Here, the reflected voltage (E _P12 , E _P13 ) applied to the second terminal T ₁₂ and the third terminal T ₁₃ of the branch hybrid circuit 10 is expressed by the following equation (16).

[0027]

[ _Equation 16] E _P12 = SSE _P21 E _P13 = SSE _P24 (16) where SS is the first and second low noise amplification circuits (1
It is a coupling coefficient between the output end and the input end of 1 ₁ , 11 ₂ ). When the reflected voltage output to each terminal of the hybrid circuit 11 for branching is obtained by using the equations (5) and (16), the following equation (17) is obtained.

[0028]

[Equation 17] Therefore, the first end of the hybrid circuit 11 for branching
Child T₁₁And the fourth terminal T ₁₄Reflected voltage (E_P11, E
_P14) Is expressed by the following equation (18).

[0029]

[Equation 18] E _P11 = SS (E _P21 −jE _P24 ) / 2 ^1/2 = Γ ₂ SS (−G _v1 (1−Γ ₁ ² ) ^1/2 Ein − (E _N1 + jE _N2 ) / 2 ^{1 / _{2) / 2 -jΓ 2 SS (}} -jG v1 (1-Γ 1 2) 1/2 Ein + (E N2 -jE N1) / 2 1/2) / 2 = Γ 2 SS (-G v1 (1- Γ ₁ ² ) ^1/2 Ein− (E _N1 + jE _N2 ) / 2 ^1/2 ) E _P14 = SS (E _P24 −jE _P21 ) = Γ ₂ SS (−G _v1 (1−Γ ₁ ² ) ^1/2 _{Ein + (E N2 -jE N1)} / 2 1/2) / 2 -jΓ 2 SS (-G v1 (1-Γ 1 2) 1/2 Ein - (E N1 + jE N2) / 2 1/2) / 2 = 0 (18)

As can be seen from the equation (18), the reflected voltage generated at the fourth terminal T ₁₄ of the branching hybrid circuit 11 is 0, but at the first terminal T ₁₁ , the equation (18) is used. The required reflected voltage is generated. The reflected voltage E _P11 deteriorates the input impedance of the first terminal T ₁₁ of the branching hybrid circuit 10, and the reflected voltage E _P11 further deteriorates.
_P11 is reflected again and is amplified by the first and second low noise amplifier circuits (11 ₁ , 11 ₂ ) and the low noise amplifier circuit 113. Therefore, in the low noise amplifier (that is, the low noise amplifier shown in FIG. 22) as shown in FIG. 6, the noise figure (NF) deteriorates more than the theoretical value. The input impedance characteristic of the low noise amplifier shown in FIG. 6 is shown in FIG.
FIG. 8 shows the noise figure (NF) of the low noise amplifier shown in FIG.
Shown in. As can be seen from FIG. 8, the low noise amplifier shown in FIG. 6 has a noise figure (NF) of approximately 0.6 dB.

As shown in FIG. 1, in the present embodiment, the isolator 15 is interposed between the branch hybrid circuit 10 and the low noise amplifier circuit 113. Therefore, in the present embodiment, the reflected voltage (E _P23 ) expressed by the equation (14) is output to the non-reflecting terminator of the isolator 15, so that the first terminal T ₁₁ of the branching hybrid circuit 10 is generated. The input impedance characteristic and the noise figure (NF) can be improved. FIG. 9 shows an input impedance characteristic of an example of the low noise amplifier of this embodiment.
In addition, the noise figure (N
F) is shown in FIG. As can be seen from FIG. 10, the low noise amplifier of the present embodiment has a noise figure (NF) of 0.3.
It can be dB.

Next, the intersect point (IP) of the first and second low noise amplifying circuits (11 ₁ , 11 ₂ ) of this embodiment will be described. The intersect point (IP) of the single low-noise amplifier circuit and the output level (P _1dB ) when the power is compressed by _{1 dB} have the relationship shown in the following equation (19).

IP = P _1dB + 10dB ·························································· (19) Point (I
P), or the output level (P _{1d B} ) when the power is compressed by 1 dB, the intersect point (IP) and the output level (P _{1d B} ) when the power is compressed by 1 dB are expressed by the equation (19).
_1dB ) can be obtained. In addition, like the first and second low noise amplifier circuits (11 ₁ , 11 ₂ ) shown in FIG.
When the n-type low-noise amplifier circuits are used to form a parallel circuit configuration, the intersect point (IP) becomes larger than when the low-noise amplifier circuits are used alone. The amount of increase (ΔIP) in that case can be expressed by the following equation (20).

[0033]

ΔIP = 10logn (n is the number of unit low noise amplifiers connected in parallel) (20) For example, as in this embodiment , If the number of unit low noise amplifiers connected in parallel is two, increase (ΔIP)
Can be expressed by the following equation (21).

ΔIP = 10log2 = 3dB (21) Therefore, (I) of the low noise amplifier circuit of the present embodiment is
P ₁ ) is given by the following equation (22).

[Equation 22] IP ₁ = IP _T1 + ΔIP = IP _T1 +3 dB (22) where IP _T1 is the first and second low noise amplification. This is an intersect point of the circuit (11 ₁ , 11 ₂ ) alone.

FIG. 11 is a graph showing the intersect point (IP) of the low noise amplifier circuit. In the figure,
The horizontal axis represents the input power (unit: dBm), the vertical axis represents the output power (unit: dBm), F is the input-output power characteristic of the fundamental wave, and T is the input-output power characteristic of the third-order IM wave by two waves. Indicates. In the figure, IP is an intersect point and G is a power gain. FIG. 12 is a simplified diagram showing the low noise amplifier according to the present embodiment. In FIG. 12, a low noise amplifier circuit A1 represents the first and second low noise amplifier circuits (11 ₁ , 11 ₂ ), and the low noise amplifier circuit A2
Represents a low noise amplifier circuit 311 in the next stage. Further, in the figure, G _V1 and IP _T1 +3 dB are the voltage amplification degree and the intersect point of the low noise amplification circuit A1, respectively,
G _V2 and IP ₂ are the voltage amplification degree and the intersect point of the low noise amplification circuit A2, respectively.

In the multistage low noise amplifier as in the present embodiment, unless the intersection point (IP) and the voltage amplification degree (G _V ) of the low noise amplifier circuit in each stage are optimized, the total characteristics will be improved. The third-order IM characteristic becomes less than the design value, or as shown in FIG. 11, the power is 1 dB.
The linearity near the output level (P _1dB ) during compression deteriorates.
Therefore, the margin M represented by the following equation (23) is defined,
Further, if IP ₂ is obtained by a design requirement value obtained by a specification standard or the like and IP ₁ is obtained so as to satisfy the following equation (23), a low noise amplifier with good linearity can be obtained.

(23) M = IP _T1 +3 dB-IP ₂ + G _V2 ≧ 6 dB IP _T1 +3 dB-IP ₂ + G _V2 ≧ 6 dB IP _T1 −IP ₂ + G _V2 ≧ 3 dB (23)

Generally, in a multi-stage type low noise amplifier in which n pieces of low noise amplifying circuits as shown in FIG. 13 are connected in cascade, by designing to satisfy the following equation (24), the linearity can be improved. A good low noise amplifier can be obtained.

[Equation 24] IP _k −IP _{k + 1} + G _{V (k + 1)} ≧ 6 dB (24) where IP _k is k (1 ≦ k ≦ n -1) Inter-sector point of the low noise amplifier circuit, IP _{k + 1} , G _{V (k + 1)}
Is the inter-sector point of the (k + 1) th low noise amplifier circuit and the voltage amplification degree. Next, how to find the total noise figure (NF) in the multistage noise amplifier shown in FIG. 13 will be described. In FIG. 13, F ₁ dB,
F ₂ dB to F _n dB, G _V1 dB, G _V2 dB to G _Vn dB are
The noise figure (NF) and the voltage amplification factor of the first, second, or nth low noise increase circuits displayed in dB value, respectively, and the total noise figure (NF) displayed in dB value.
Is F _t dB.

First, the noise figure (F
dB) is converted into a true noise figure (F) by the following equation (25).

(25) FdB = 10logF F = 10 ^{FdB /} 10 ^... (25) Further, the noise figure (FdB) displayed in dB value is calculated. To achieve this, the voltage amplification factor (G _V dB) is also required, but since the voltage amplification factor is displayed in dB, the following (26)
It is converted into the true voltage amplification degree (G _V ) by the formula.

G _V dB = 10 ^log G _V G _V = 10 ^GVdB (26) The total noise figure (F _t dB) is the following (27). ) Equation can be obtained.

[0038]

[Equation 27]   F_t= F₁+ (F₂-1) / G₁+ (F₃-1) / G₁G₂+           + (F_n-1) / G₁G₂・ ・ ・ G_n   F_tdB = 10 logF_t                   ・ ・ ・ ・ ・ ・ ・ ・ ・ (27) Next, as an example, the low noise amplifier 103 according to the present embodiment.
Total noise displayed in dB under the following conditions
Index (F_tCalculate dB). <conditions> Amplification frequency f = 2GHZ The first-stage low-noise amplifier circuit is composed of HEMT elements,
Low noise amplifier circuit (11 ₁, 11₂) Intersect point
To (IP_T1) = 24 dBm, noisy finger displayed in dB value
Number (F₁dB) = 0.3 dB, voltage displayed in dB value
Amplification degree (G_V1dB) = 18 dB. Next stage low noise
The path 113 is composed of a GaAs FET element, and a low noise amplification circuit
Intersect point of road 113 (IP₂) = 39.5
Noise figure displayed in dBm and dB values (F₂dB) =
Voltage amplification (G of 1.2 dB and dB)_V2d
B) = 18 dB. Also, insert the isolator 15
Loss (L₁) = 0.5 dB.

From the equations (25) and (26), the true noise figure (F ₁ , F ₂ ) and the true voltage amplification degree (G ₁ ,
G ₂ ) is given by the following equation (28).

[Formula 28] F ₁ = 10 ^{0.3 / 10} ≈1.072 F ₂ = 10 ^{2.5 /} 10 ^≈1.778 G _V1 = G _V2 = 10 ^{18/10 ≈63.1} (28) Further, the insertion loss of the isolator 15 and the low noise amplification circuit 1
The noise figure (F ₂ ') in which the noise figure of 13 is added is given by the following expression (29).

F ₂ 'dB = F ₂ dB + L ₁ = 2.5 + 0.5 = ^3.0 dB F ₂ ' = 10 ^{3.0 / 10} ≈ 2.0 (29) Therefore, the total noise figure (F _t , F _t db) is expressed by the following formula (30) using the formula (27).

[0040]

F _t = F ₁ + (F ₂ '−1) / G ₁ = 1.072 + (2.0-1) /63.1 ≈1.088 F _t dB = 10log 1.088 ≈0.37 dB (30) The resistance loss (L ₁ ) of the hybrid circuit 10 is 0.05 dB.
Then, the resistance figure (L ₁ ) of the hybrid circuit 10 and the noise figure (F ₁ ') in which the noise figure of the low noise amplifier circuit 112 is added are as shown in the following equation (31).

F ₁ 'dB = F ₁ dB + L ₁ = 0.3 + 0.05 = ^0.35 dB F ₁ ' = 10 ^{0.35 / 10} ≈1.084 (31) Therefore, the total noise figure (F _t , F _t db) in this case
Is expressed by the following expression (32) using the expression (27).

[0041]

F _t = F ₁ '+ (F ₂ ' -1) / G _V1 = 1.084 + (2.0-1) /63.1 ≈1.102 F _t dB = 10log 1.102 ≈0. 42dB ・ ・ ・ ・ ・ ・ ・ ・ ・ (32)

Further, the intersect point (IP ₁ ) of the low noise amplifying circuit 112 at the first stage is given by the following equation (33) in consideration of the increase amount (ΔIP).

[Equation 33] IP ₁ = IP _T1 + 10log2 = 24 dBm + 3 dB (33) Therefore, the margin M (= IP ₁ −IP ₂ + G _V2 ) is It becomes like a formula 34).

(34) M = IP ₁ −IP ₂ + G _V2 = 24 dBm + 3 dB−39.5 dBm + 18 dB + 0.5 dB = 6.0 (34) As described above, since the margin M is 6 or more, the above-described low noise amplifier has good linearity.

[Second Embodiment] FIG. 14 is a block diagram showing a schematic structure of a low noise amplifier 103 according to a second embodiment of the present invention. As shown in the figure, the low-noise amplifier 103 of the present embodiment includes a low-noise amplifier circuit 113 in the next stage, a hybrid circuit 20 for branching, a hybrid circuit 22 for combining, a third and a fourth hybrid circuit 22. Low noise amplifier circuit (21 ₁ ,
21 ₂ ) is the difference from the low noise amplifier 103 of the above-mentioned embodiment. Here, the third low-noise amplifier circuit 21 ₁ has a second terminal T ₃₂ of the branching hybrid circuit 20 and a first terminal T ₄₁ of the combining hybrid circuit 22.
And the fourth low noise amplifier circuit 21 ₂ is connected between the third terminal T ₃₃ of the branching hybrid circuit 20 and the fourth terminal T ₄₄ of the combining hybrid circuit 22. To be done. The first terminal T ₃₁ of the hybrid circuit 20 for branching and the third terminal T ₃₁ of the hybrid circuit 22 for combining.
A non-reflective terminator R is connected to the terminal T ₄₃ of. Further, the fourth terminal T of the hybrid circuit 20 for branching
₃₄ is the third terminal T ₂₃ of the hybrid circuit 12 for synthesis.
Connected to.

In this embodiment, the amplified signal is output from the second terminal T ₄₂ of the hybrid circuit 22 for combining, but the first terminal T of the branching hybrid circuit 10 is affected by the load. _When the input voltage reflection coefficient of ₁₁ changes, as shown in FIG. 15, the isolator 15 may be connected to the latter stage of the second terminal T ₄₂ of the hybrid circuit 22 for synthesis. FIG. 16 is a diagram schematically showing the low noise amplifier according to the present embodiment. In the figure, the low-noise amplifier circuit A1 is the first and second low-noise amplifier circuits (11
₁ , 11 ₂ ), and the low noise amplifier circuit A2 represents the third and fourth low noise amplifier circuits (21 ₁ , 21 ₂ ). Also,
In the figure, G _V1 and IP _T1 +3 dB are the voltage amplification degree and the intersect point of the low noise amplification circuit A1, respectively, and G _V2 and IP _T2 +3 dB are the voltage amplification degree and the intersection point of the low noise amplification circuit A2, respectively. It is a point.

Here, if (IP _T2 +3 dB) is obtained by the design requirement value and IP ₁ is obtained so as to satisfy the following equation (35), a low noise amplifier with good linearity can be obtained.

M = IP _T1 +3 dB-IP _T2 -3 dB + G _V2 ≧ 6 dB IP _T1 +3 dB-IP _T2 -3 dB + G _V2 ≧ 6 dB IP _T1- IP _T2 + G _V2 ≧ 6 dB (35) The present embodiment is a circuit suitable when the intersect point of the low noise amplifying circuit A2 is higher than the intersect point of the low noise amplifying circuit A1 by several ten dBm.

[Third Embodiment] FIG. 17 is a block diagram showing a schematic structure of a low noise amplifier 103 according to a third embodiment of the present invention. As shown in the figure, the low noise amplifier 103 according to the present embodiment includes a low noise amplifier circuit 113 at the next stage
(= 2 ^{(4-1) +1} -1 = 16-1) hybrid circuits (30 ₁ to 30 ₁₅ ), and 16 (=
2 ⁴ ) low-noise amplifier circuits (31 _{1 to} 31 ₁₆ ) and 16 hybrid circuits (32 _{1 to} 32 ₁₅ ) are used as synthesizing means.
Different from 03. In the present embodiment, the amplified signal is output from the third terminal of the hybrid circuit 32 ₁ of the combining means, but due to the influence of the load, the input voltage of the first terminal T ₁₁ of the branching hybrid circuit 10 is increased. When the reflection coefficient fluctuates, as shown in FIG. 18, the isolator 15 may be connected to the latter stage of the second terminal of the hybrid circuit 32 ₁₅ of the combining means. When the number of unit low-noise amplifiers connected in parallel is 16, like the low-noise amplifier circuit 113 of the present embodiment, the increase amount (ΔIP) is equal to (2)
It can be expressed by the following equation (36) from the equation (1).

[0047]

ΔIP = 10logn = 10log16 = 12dB (36) Therefore, (IP of the low noise amplification circuit 113 of the present embodiment is ) Is expressed by the following equation (37).

[Equation 37] IP = IP _T2 +12 dB (37)

FIG. 19 is a simplified diagram showing the low noise amplifier of the present embodiment. In the figure, the low-noise amplifier circuit A1 includes a first and a second low-noise amplifier circuits (11 ₁ ,
11 ₂ ), and the low noise amplifier circuit A2 has 16 (=
2 ⁴⁾ represents the number of low-noise amplifier (34 ₁ to 14 _16). Further, in the figure, G _V1 and IP _T1 +3 dB are the voltage amplification degree and the intersect point of the low noise amplification circuit A1, respectively, and G _V2 and IP _T2 +12 dB are the voltage amplification degree of the low noise amplification circuit A2, respectively. It is an intersect point.

Here, if (IP _T2 +12 dB) is obtained by the design requirement value and IP _T1 is obtained so as to satisfy the following equation (38), a low noise amplifier with good linearity can be obtained.

(38) M = IP _T1 +3 dB−IP _T2 −12 dB + G _V2 ≧ 6 dB IP _T1 −IP _T2 + G _V2 ≧ 15 dB ... (38) The GaAsFET element is an intersect point. (IP)
However, the noise figure (NF) is slightly deteriorated as compared with the HEMT device. For example, the noise figure (NF) is about 0.5 dB in a two-stage low noise amplifier composed of GaAs FET elements. Therefore, in the present embodiment, when the HEMT element is composed of the low noise amplifier, the intersect point can be increased.

Next, the low noise amplifier 103 of the present embodiment.
Compute the total noise figure (F _t dB) in dB, expressed in dB, under the following conditions. <Conditions> Amplification frequency f = 2GHZ The first stage low-noise amplifier circuit 112 is composed of HEMT elements,
Intersecting point (IP _T1 ) of a single low-noise amplifier circuit (11 ₁ , 11 ₂ ) = 24 dBm, noise figure displayed by dB value (F ₁ dB) = 0.3 dB, voltage amplification displayed by dB value Degree (G _V1 dB) = 18 dB. The low-noise circuit 113 in the next stage is composed of HEMT elements, and the intersection point (IP _T2 ) of the single low-noise amplifier circuit (13 _{1 to 3 16} ) is 26 dBm, and the noise figure (F ₂ dB) displayed in dB value ) = 0.35 dB, and the voltage amplification degree (G _V2 dB) displayed in dB value = 18 dB. The resistance loss of the hybrid circuit 10 (L ₁₎ = 0.05dB, resistance loss of the hybrid circuit _{(30 1 ~30 8) (L} 2) = 0.2
dB.

Resistance loss of hybrid circuit 10 (L ₁ )
, The noise figure (F ₁ ') in which the noise figure of the low-noise amplifier circuit 112 is added, the resistance loss (L ₂ ) of the hybrid circuit (30 ₁ to 30 ₈ ) and the noise figure of the low-noise amplifier circuit 113 are added. The noise figure (F ₂ ') is expressed by the following equation (39).

F ₁ 'dB = F ₁ dB + L ₁ = 0.3 + 0.05 = ^0.35 dB F ₁ ' = 10 ^{0.35 / 10} ≈ 1.084 F ₂ 'dB = F ₂ dB + L ₂ = 0.35 + 0.2 = 0.55dB F ₂ '= 10 ^{0.55 / 10} ≈1.135 ・ ・ ・ ・ ・ ・ ・ ・ ・ (39)

From the equations (25) and (26), the true voltage amplification degree (G _V1 , G _V2 ) is as shown in the following equation (40).

G _V1 = G _V2 = 10 ^{18/10 ≈63.1} (40) Therefore, the total noise figure (F _t , F _t db ) Is expressed by the following expression (41) using the expression (27).

[0053]

F _t = F ₁ '+ (F ₂ ' -1) / G _V1 = 1.084 + (1.135-1) /63.1 ≈1.086 F _t dB = 10log 1.086 ≈0. 36dB ・ ・ ・ ・ ・ ・ ・ ・ ・ (41)

Further, the margin M (= IP _T1 +3 dB-IP
_T2 -12 dB + G _V2) is as follows (42) below.

(42) M = IP _T1 +3 dB-IP _T2 -12 dB + G _V2 = 24 dBm + 3 dB-26 dBm-12 dB + 18 dB = 7.0 42) As described above, since the margin M is 6 or more, the above-described low noise amplifier has good linearity. Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course,

[0055]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the multistage low noise amplifier of the present invention, linearity,
Alternatively, it becomes possible to improve the intermodulation wave (IM) characteristics. (2) According to the multistage low noise amplifier of the present invention, it is possible to improve the noise figure (NF) more than before.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a low noise amplifier according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a hybrid circuit composed of a λ / 4/3 dB coupler.

FIG. 3 is a diagram for explaining an output destination of the high frequency signal reflected by the first and second low noise amplifier circuits in the first embodiment of the present invention.

FIG. 4 is a diagram for explaining an output destination of a high frequency signal input from the first and fourth terminals of the second hybrid circuit in the first embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional constant impedance type low noise amplifier circuit.

6 is a block diagram showing a low noise amplifier in which a low noise amplifier circuit is connected to a stage subsequent to the constant impedance type low noise amplifier circuit shown in FIG.

7 is a graph showing an input impedance characteristic of the low noise amplifier shown in FIG.

8 is a table showing a noise figure (NF) of the low noise amplifier shown in FIG.

FIG. 9 is a graph showing an input impedance characteristic of the low noise amplifier according to the first embodiment of the present invention.

FIG. 10 is a table showing the noise figure (NF) of the low noise amplifier according to the first embodiment of the present invention.

FIG. 11 is a graph showing intersect points (IP) of a single low-noise amplifier circuit.

FIG. 12 is a diagram schematically showing the low noise amplifier according to the first embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a general multistage low noise amplifier.

FIG. 14 is a block diagram showing a schematic configuration of a low noise amplifier according to a second embodiment of the present invention.

FIG. 15 is a block diagram showing a modification of the low noise amplifier according to the second embodiment of the present invention.

FIG. 16 is a diagram schematically showing a low noise amplifier according to a second embodiment of the present invention.

FIG. 17 is a block diagram showing a schematic configuration of a low noise amplifier according to a third embodiment of the present invention.

FIG. 18 is a block diagram showing a modification of the low noise amplifier according to the third embodiment of the present invention.

FIG. 19 is a diagram schematically showing a low noise amplifier according to a third embodiment of the present invention.

FIG. 20 is a block diagram showing a schematic configuration of an example of a receiving side of a mobile communication base station or a TV broadcast relay broadcast device.

21 is a block diagram showing a conventional circuit configuration of an example of the low noise amplifier shown in FIG.

22 is a block diagram showing a conventional circuit configuration of another example of the low noise amplifier shown in FIG.

[Explanation of symbols]

10, ₁₂ , 20, 22, 30 ₁ to 30 ₁₅ , 32 _{1 to} 3
2 ₁₅ ... Hybrid circuit, 11 ₁ , 11 ₂ , 21 ₁ , 2
1 ₂ , 31 _{1 to} 31 ₁₆ , 112, 113, A1, A2, A
n ... Low noise amplification circuit, 15, 111 ... Circulator (isolator), 101 ... Reception antenna, 102 ... Wideband bandpass filter, 103 ... Multistage low noise amplifier,
104 _{1 to} 104 _n ... Narrow band pass filter, 105 ₁ to 1
05 _n ... Receiving device, R ... Non-reflective terminator.

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-5-283953 (JP, A) JP-A-6-216671 (JP, A) JP-A-6-252670 (JP, A) JP-A-10- 224154 (JP, A) JP 63-80603 (JP, A) Actual development 63-136416 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03F 1/26 H03F 1 / 32 H03F 3/68

Claims (4)

(57) [Claims] 1. A multi-stage low noise amplifier configured by cascade-connecting n low noise amplifiers, wherein an intercept point of a k (k = 1, 2, ..., N-1) th low noise amplifier. IP _k , the intercept point of the (k + 1) th low noise amplifier is IP _{k + 1} , and the voltage amplification degree of the (k + 1) th low noise amplifier is G
_{When V (k + 1)} , 6 dB ≦ IP _k −IP _{k + 1} + G _{V (k + 1)}
A multi-stage low noise amplifier characterized by satisfying the following. 2. A first low noise amplifier, a second low noise amplifier, and an isolator provided between the first low noise amplifier and the second low noise amplifier are cascade-connected. And a first hybrid circuit in which an input signal is applied to a first terminal, and an input terminal is the first hybrid circuit of the first hybrid circuit. A first low noise amplifier circuit connected to the second terminal, a second low noise amplifier circuit having an input terminal connected to the third terminal of the first hybrid circuit, and a first terminal The fourth terminal is connected to the output terminal of the first low noise amplifier circuit, the fourth terminal is connected to the output terminal of the second low noise amplifier circuit, and the third terminal is connected to the first terminal of the isolator. A second hybrid circuit connected to the terminals Is configured, and the intercept point of the first low-noise amplifier IP _1, IP ₂ the intercept point of the second low-noise amplifier, and the voltage amplification degree of the second low-noise amplifier and G _V2 6 dB ≦ IP ₁ −
A multi-stage low noise amplifier characterized by satisfying IP ₂ + G _V2 . 3. A multi-stage type low noise amplifier configured by cascading a first low noise amplifier and a second low noise amplifier, wherein the first low noise amplifier has a first terminal. A first hybrid circuit to which an input signal is applied, a first low noise amplifier circuit having an input terminal connected to a second terminal of the first hybrid circuit, and an input terminal having the first hybrid circuit A second low noise amplifier circuit connected to the third terminal of the hybrid circuit, a first terminal connected to the output terminal of the first low noise amplifier circuit, and a fourth terminal connected to the second terminal. And a second hybrid circuit connected to the output terminal of the low noise amplifier circuit of the second low noise amplifier circuit, wherein the second low noise amplifier has a first terminal of the second hybrid circuit.
A third hybrid circuit connected to the third terminal of the hybrid circuit, and an input terminal connected to the second terminal of the third hybrid circuit, a third low noise amplifier circuit, and an input terminal A fourth low-noise amplifier circuit connected to the third terminal of the third hybrid circuit, and a first terminal connected to the output terminal of the third low-noise amplifier circuit, and a fourth terminal And a fourth hybrid circuit connected to the output terminal of the fourth low-noise amplifier circuit, and the intercept point of the _first low-noise amplifier is IP ₁ , and the second low-noise amplifier is the second low-noise amplifier. Where IP _{2 is} the intercept point of G 2 and the voltage amplification factor of the second low noise amplifier is G _V2 , 6 dB ≦ IP ₁ −
A multi-stage low noise amplifier characterized by satisfying IP ₂ + G _V2 . 4. A multi-stage low noise amplifier configured by cascading a first low noise amplifier and a second low noise amplifier, wherein the first low noise amplifier has a first terminal. A first hybrid circuit to which an input signal is applied, a first low noise amplifier circuit having an input terminal connected to a second terminal of the first hybrid circuit, and an input terminal having the first hybrid circuit A second low noise amplifier circuit connected to the third terminal of the hybrid circuit, a first terminal connected to the output terminal of the first low noise amplifier circuit, and a fourth terminal connected to the second terminal. And a second hybrid circuit connected to the output terminal of the low noise amplifier circuit, wherein the second low noise amplifier is composed of (2 ⁿ −1; n ≧ 2) hybrid circuits. , Output from the third terminal of the second hybrid circuit Is a branching means for branching the amplified signal to the 2 ⁿ number of signals, and the 2 ⁿ low noise amplifier circuit for amplifying the respective signals branched by said branching means, (2 ⁿ -1) number of hybrid circuit And combining means for combining the amplified signals output from the 2 ⁿ parallel low noise amplifiers, and the intercept point of the _first low noise amplifier is IP ₁ , When the intercept point of the second low noise amplifier is IP ₂ and the voltage amplification degree of the second low noise amplifier is G _V2 , 6 dB ≦ IP ₁ −
A multi-stage low noise amplifier characterized by satisfying IP ₂ + G _V2 .