CN109194347B - Intermediate frequency circuit for miniaturized ODU receiving channel - Google Patents
Intermediate frequency circuit for miniaturized ODU receiving channel Download PDFInfo
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- H—ELECTRICITY
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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Abstract
The invention discloses an intermediate frequency circuit for a miniaturized ODU receiving channel, which comprises an intermediate frequency signal input end, a first stage intermediate frequency filter electrically connected with the intermediate frequency signal input end, and a first stage intermediate frequency amplifier, a second stage intermediate frequency filter, a second stage intermediate frequency amplifier and a third stage intermediate frequency filter which are sequentially connected in series to form an intermediate frequency channel circuit with two stages of amplification and three stages of filtering. And a gain equalizer and a temperature compensation attenuator are further cascaded after the third stage intermediate frequency filter. The circuit can well filter clutter and harmonic components in the intermediate frequency signal, provides enough channel gain, ensures the flatness of the intermediate frequency signal in the whole frequency band and the characteristic that the gain is not influenced by high and low temperature, and has the advantages of reducing the volume, reducing the cost, keeping the signal stable and reliable and the like because the selected components are mainly integrated single components.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to an intermediate frequency circuit for a miniaturized ODU receiving channel.
Background
In satellite communication devices, ODU (Out-door Unit) refers to an outdoor Unit, mainly comprising frequency conversion and power amplification, and may be specifically divided into a transmitting channel and a receiving channel, where the transmitting channel is usually referred to as BUC (Block Up-Converter), i.e. an Up-conversion power amplifier, and the receiving channel is mainly referred to as LNB (Low Noise Block down-Converter), i.e. a low noise amplifying, frequency Converter.
In satellite communication equipment, an intermediate frequency circuit of a receiving channel refers to a channel circuit that processes an obtained intermediate frequency signal after a radio frequency signal is mixed with a local oscillation signal. The mixed intermediate frequency signal usually contains a large amount of harmonic wave and clutter components, so that filtering processing and signal amplification processing are required, and meanwhile, the mixed intermediate frequency signal has good signal-to-noise ratio characteristics and has good flatness in an operating bandwidth.
In the prior art, along with the miniaturization development trend of satellite communication equipment, the intermediate frequency circuit of a receiving channel hopefully adopts fewer components, and the component circuit has the advantages of small occupied space, low power consumption, high stability and the like.
Disclosure of Invention
The invention mainly solves the technical problems of insufficient clutter processing coverage, insufficient amplification processing gain and excessively complex circuit, large volume and high power consumption of an intermediate frequency signal in a limited space in the prior art.
In order to solve the technical problems, the technical scheme adopted by the invention is to provide an intermediate frequency circuit for a miniaturized ODU receiving channel, which comprises an intermediate frequency signal input end, wherein the intermediate frequency signal input end is firstly connected with an intermediate frequency filter for filtering clutter outside the intermediate frequency signal, then the output end of the intermediate frequency filter is electrically connected with an intermediate frequency amplifier, and the intermediate frequency amplifier performs power amplification on the intermediate frequency signal and then outputs the intermediate frequency signal.
In another embodiment of the intermediate frequency circuit for miniaturized ODU reception channels of the present invention, the intermediate frequency filter comprises a first stage intermediate frequency filter comprising a chip LFCN-6000, and a first matching attenuator is further connected in series between the chip LFCN-6000 and the intermediate frequency signal input.
In another embodiment of the intermediate frequency circuit for miniaturized ODU reception channels of the present invention, the intermediate frequency amplifier further comprises a first stage intermediate frequency amplifier, the first intermediate frequency amplifier comprising a chip UPC3226TB, an input of the chip UPC3226TB being electrically connected to an output of the chip LFCN-6000.
In another embodiment of the intermediate frequency circuit for miniaturized ODU reception channels of the present invention, the intermediate frequency filter comprises a second stage intermediate frequency filter comprising a chip LFCN-8400, and a second matched attenuator is further connected in series between the input of the chip LFCN-8400 and the output of the chip UPC3226 TB.
In another embodiment of the intermediate frequency circuit for miniaturizing ODU reception channels of the invention, the intermediate frequency filter comprises a second stage intermediate frequency amplifier comprising a chip ECG001F-G and electrically connected at an input of the chip ECG001F-G to an output of the chip LFCN-8400.
In another embodiment of the intermediate frequency circuit for miniaturizing an ODU reception channel of the invention, the intermediate frequency filter comprises a third stage intermediate frequency filter comprising a chip LFCN-2250, and an input of the chip LFCN-2250 is electrically connected to an output of the chip ECG 001F-G.
In another embodiment of the intermediate frequency circuit for miniaturized ODU reception channels of the present invention, a gain equalizer is further electrically connected to the output of the chip LFCN-2250.
In another embodiment of the intermediate frequency circuit for miniaturized ODU reception channels of the present invention, a third matching attenuator is further connected in series between the chip LFCN-2250 and the gain equalizer.
In another embodiment of the intermediate frequency circuit for miniaturized ODU reception channels of the present invention, a temperature compensation attenuator is further cascaded at the output of the gain equalizer.
In another embodiment of the intermediate frequency circuit for the miniaturized ODU reception channel of the present invention, the intermediate frequency circuit is disposed in a cavity, the cavity includes a power supply cavity, a first cavity, a second cavity, and a third cavity, the power supply cavity is communicated with the second cavity, and the first cavity, the second cavity, and the third cavity are combined into a whole in an S-type structure.
The beneficial effects of the invention are as follows: the invention discloses an intermediate frequency circuit for a miniaturized ODU receiving channel, which comprises an intermediate frequency signal input end, a first stage intermediate frequency filter electrically connected with a radio frequency signal input end, and a first stage intermediate frequency amplifier, a second stage intermediate frequency filter, a second stage intermediate frequency amplifier and a third stage intermediate frequency filter which are sequentially connected in series to form an intermediate frequency channel circuit with two stages of amplification and three stages of filtering. And a gain equalizer and a temperature compensation attenuator are further cascaded after the third stage intermediate frequency filter. The circuit can well filter clutter and harmonic components in the intermediate frequency signal, provides enough channel gain, ensures the flatness of the intermediate frequency signal in the whole frequency band and the characteristic that the gain is not influenced by high and low temperature, and has the advantages of reducing the volume, reducing the cost, keeping the signal stable and reliable and the like because the selected components are mainly integrated single components.
Drawings
FIG. 1 is a block diagram of an embodiment of an intermediate frequency circuit for a miniaturized ODU receive channel according to the present invention;
FIG. 2 is a circuit diagram of a first stage IF filter in another embodiment of an IF circuit for a miniaturized ODU receive channel of the present invention;
FIG. 3 is a circuit diagram of a first stage intermediate frequency amplifier in another embodiment of the intermediate frequency circuit for a miniaturized ODU receive channel of the invention;
FIG. 4 is a circuit diagram of a second stage IF filter in another embodiment of an IF circuit for a miniaturized ODU receive channel of the present invention;
FIG. 5 is a circuit diagram of a second stage intermediate frequency amplifier in another embodiment of the intermediate frequency circuit for a miniaturized ODU receive channel of the invention;
FIG. 6 is a circuit diagram of a third stage IF amplifier and gain equalizer, temperature compensated attenuator in another embodiment of an IF circuit for a miniaturized ODU receive channel according to the present invention;
FIG. 7 is a schematic diagram of an intermediate frequency circuit for miniaturized ODU receive channels according to another embodiment of the invention;
fig. 8 is a structural layout diagram of another embodiment of an intermediate frequency circuit for miniaturized ODU reception channels according to the present invention.
Detailed Description
In order that the invention may be readily understood, a more particular description thereof will be rendered by reference to specific embodiments that are illustrated in the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Fig. 1 is a schematic diagram showing the composition of an intermediate frequency circuit for miniaturized ODU reception channels according to an embodiment of the present invention. The circuit comprises an intermediate frequency signal input end 311, wherein the intermediate frequency signal input end 311 is firstly connected with an intermediate frequency filter for filtering clutter outside the intermediate frequency signal, then the output end of the intermediate frequency filter is electrically connected with an intermediate frequency amplifier, and the intermediate frequency amplifier performs power amplification on the intermediate frequency signal and then outputs the intermediate frequency signal.
Further, as shown in fig. 1, the intermediate frequency filter and the intermediate frequency amplifier have a multistage series structure. The intermediate frequency filter comprises a first stage intermediate frequency filter 31, wherein the first stage intermediate frequency filter 31 comprises a chip LFCN-6000, and a first matched attenuator is further connected in series between the chip LFCN-6000 and the intermediate frequency signal input end 311.
Further, the composition of the first matched attenuator and the first stage intermediate frequency filter 31 composed of the chip LFCN-6000 are shown in fig. 2. The intermediate frequency input terminal couples the intermediate frequency signal to a matching attenuator consisting of resistors R25, R28 and R29 through a capacitor C34 of 100pF, wherein the resistance value of R25 is 18Ω, the resistance values of R28 and R29 are both 300Ω, and R28 and R29 are respectively connected to both ends of the resistor R25 and then respectively grounded. The matcher can be used for matching the impedance of the front stage and the rear stage, and the intermediate frequency signal is kept to have good conductivity in the circuit. In FIG. 2, the connection ends of R25 and R29 are electrically connected with the No. 1 pin of the chip LFCN-6000, namely the signal input end, the No. 2 pin and the No. 4 pin of the chip LFCN-6000 are grounded, and the No. 3 pin is the signal output end. The filter has small volume, no need of interface circuit on the periphery, and is suitable for miniaturized intermediate frequency channel circuit. In addition, the frequency range of the incoming intermediate frequency signal is mainly concentrated in 950MHz-2150MHz, and the chip LFCN-6000 has good low-pass characteristics below 6000MHz, for example, at 5000MHz, the corresponding insertion loss is 0.57dB, the VSWR is 1.37:1, at 6000MHz, the corresponding insertion loss is 0.75dB, the VSWR is 1.24:1, and at 6800MHz, the corresponding insertion loss is 2.80dB, and the VSWR is 3.31:1. The first intermediate frequency filter is mainly formed by the chip and is used for filtering local oscillation signals in a mixer in the previous stage and filtering harmonic components in the intermediate frequency signals.
Further, in fig. 1, the intermediate frequency amplifier includes a first stage intermediate frequency amplifier 32, the first intermediate frequency amplifier 32 includes a chip UPC3226TB, and an input terminal of the chip UPC3226TB is electrically connected to an output terminal of the chip LFCN-6000.
As shown in fig. 3, the chip UPC3226TB and its peripheral circuit composition is shown, wherein it is electrically connected to the signal output (i.e., pin No. 3) of the previous stage chip LFCN-6000 through capacitor C36. The power end Vcc of the UPC3226TB of the chip is connected with direct current +5V through a power filter network, the power filter network is mainly an RC network, adverse effects on amplification of a medium-frequency signal caused by power fluctuation can be reduced through the network, the power is amplified through the chip and then output from a pin No. 4 of the power filter network, and the pin No. 4 is further connected to the power filter network through an inductor L8. It can be seen that the RC network comprises capacitors C46, C30 electrically connected to +5v, both of which are grounded at their other ends, and two parallel resistors R22, R23 electrically connected to +5v, the other ends of which are commonly electrically connected to the power supply terminal Vcc of the chip UPC3226 TB. The working frequency band of the UPC3226TB is 0-3GHz, the gain is 25dB@1GHz, the noise coefficient is 5.3dB, the output 1dB compression power is +7.5dBm, +5V power supply, and the working current is 15mA. The chip adopts 6-pin packaging, has small appearance and simple and easy-to-use circuit.
Further, in fig. 1, the intermediate frequency filter includes a second stage intermediate frequency filter 33, where the second stage intermediate frequency filter 33 includes a chip LFCN-8400, and a second matched attenuator is further connected in series between an input terminal of the chip LFCN-8400 and an output terminal of the chip UPC3226 TB.
The composition of the second matched attenuator and the second stage intermediate frequency filter 33 consisting of the chip LFCN-8400 is shown in fig. 4. The output terminal of the chip UPC3226TB further couples the intermediate frequency signal to a matching attenuator consisting of resistors R24, R26 and R27 through a capacitor C31 of 100pF, wherein the resistance value of R24 is 18Ω, the resistance values of R26 and R27 are both 300Ω, and R26 and R27 are respectively connected to both ends of the resistor R24, and then respectively grounded. The matcher can be used for matching the impedance of the front stage and the rear stage, and the intermediate frequency signal is kept to have good conductivity in the circuit. In FIG. 4, the connection ends of R24 and R27 are electrically connected with the No. 1 pin of the chip LFCN-8400, namely the signal input end, the No. 2 pin and the No. 4 pin of the chip LFCN-8400 are grounded, and the No. 3 pin is the signal output end. The filter has small volume, no need of interface circuit on the periphery, and is suitable for miniaturized intermediate frequency channel circuit. Therefore, the second-stage intermediate frequency filter and the second matched attenuator are similar to the first-stage intermediate frequency filter and the first matched attenuator in circuit structure, and the main difference is that the chip LFCN-8400 has good low-pass characteristics below 8000MHz, and high-frequency components in intermediate frequency signals are further filtered. For example, at 7000MHz, the corresponding insertion loss is 0.58dB, VSWR is 1.15:1, at 8000MHz, the corresponding insertion loss is 0.89dB, VSWR is 1.34:1, and at 9000MHz, the corresponding insertion loss is 1.89dB, VSWR is 2.08:1.
Further, in fig. 1, the intermediate frequency filter comprises a second stage intermediate frequency amplifier 34, the second stage intermediate frequency amplifier 34 comprising a chip ECG001F-G and being electrically connected at an input of the chip ECG001F-G to an output of the chip LFCN-8400.
As shown in FIG. 5, the chip ECG001F-G and its peripheral circuit components are shown, wherein the signal output (i.e., pin 3) of the previous stage chip LFCN-8400 is electrically connected to pin 3 (i.e., signal input) of the chip ECG001F-G via capacitor C33. The pins 1, 2, 4 and 5 of the chip ECG001F-G are all grounded, and the pin 6 is an amplified signal output end. In addition, it can be seen that the pin 6 is also connected with a power supply filter network through an inductor L9 to be connected with direct current +5V, the power supply filter network is mainly an RC network, and adverse effects of power supply fluctuation on amplification of the intermediate frequency signal can be reduced through the network. The output is then conducted to the subsequent stage through capacitor C43. The RC network comprises capacitors C37 and C38 electrically connected with +5V, the other ends of the capacitors are grounded, two resistors R30 and R31 connected in parallel are electrically connected with +5V, the other ends of the two resistors are electrically connected to an inductor L9 together, the other end of the inductor is electrically connected with a No. 6 pin of a chip ECG001F-G, and the pin is also used as a power supply pin.
The working frequency band of the chip ECG001F-G is 0-6GHz, the gain is 20dB@1GHz, the noise coefficient is 3.4dB, the output 1dB compressed power is 12.5dBm, +5V power supply, and the working current is 30mA. The chip adopts 6-pin packaging, has small appearance and simple and easy-to-use circuit.
Further, in fig. 1, the intermediate frequency filter comprises a third stage intermediate frequency filter 35 comprising a chip LFCN-2250, and the input of the chip LFCN-2250 is electrically connected to the output of the chip ECG 001F-G.
As shown in FIG. 6, pin 6 of chip ECG001F-G is connected with pin 1 of LFCN-2250 through capacitor C43, pins 2 and 4 of chip LFCN-2250 are grounded, and pin 3 is a signal output terminal. The near-end harmonic signals can be filtered by selecting a chip LFCN-2250, so that out-of-band spurious emissions meet the index requirement of-50 dBc. The chip has a corresponding insertion loss of 0.51dB, a VSWR of 1.06:1 at 2000MHz, a corresponding insertion loss of 0.82dB, a VSWR of 1.20:1 at 2250MHz, a corresponding insertion loss of 2.84dB, and a VSWR of 2.10:1 at 2575 MHz. Higher insertion loss results if the frequency is increased again. And the chip has a volume of only 3.20mm multiplied by 1.60mm multiplied by 0.94mm, and occupies small space.
It can be seen that the intermediate frequency channel circuit is subjected to three-stage filtering and two-stage amplification. In the three-stage filtering, firstly, the intermediate frequency signal is subjected to low-pass filtering in a frequency range of 950MHz-2150MHz by taking 6000MHz as a cutoff frequency, then the intermediate frequency signal is subjected to low-pass filtering by taking 8000MHz as a cutoff frequency, and the intermediate frequency signal is subjected to low-pass filtering by taking 2250MHz as a cutoff frequency, and the near-end harmonic component is mainly filtered.
In fig. 1, a gain equalizer 36 is also electrically connected to the output of the third stage intermediate frequency filter 35 (i.e., chip LFCN-2250). And in connection with fig. 6, a third matched attenuator is also connected in series between the chip LFCN-2250 and the gain equalizer.
In fig. 6, pin 3 of the chip LFCN-2250 is output to the subsequent stage through a capacitor C42, where the third matching attenuator includes a resistor matching attenuation network formed by resistors R33, R36 and R37, and the network has the same circuit composition as the first matching attenuator and the second matching attenuator, which are not described herein again. The gain equalizer is mainly composed of C39, R34, R38, L10 and R41. It can be seen that this is an RLC passive network, where resistors R34 and R38 connected in series are connected in parallel to both ends of a capacitor C39, an inductor L10 is connected between the two resistors, and the other end of the inductor L10 is electrically connected to a resistor R41, and the other end of the resistor R41 is grounded.
Such a gain equalizer is added to the intermediate frequency circuit, mainly because the frequency range of the intermediate frequency signal is 950MHz-2150MHz, the bandwidth is 1.2GHz, and the gain flatness of the amplifier of the entire intermediate frequency circuit exhibits the characteristics of high low frequency gain and low high frequency gain in the entire frequency band, so that the passive RLC gain equalizer of which one stage is added to the final output is required to improve the unevenness of the amplifier in the entire frequency band.
Preferably, in fig. 1, a temperature compensation attenuator 37 is further cascaded at the output of the gain equalizer 36. In fig. 6, the temperature compensation attenuator mainly includes a chip PXV S, the ground of the chip is grounded, the input end of the chip is connected with a capacitor C39 so as to be cascaded with a gain equalizer, and the output end of the chip can be connected with a matcher, and the matcher is composed of resistors R32, R39 and R40. Because the temperature range of the working environment of the whole machine is very wide, the output gain of the whole intermediate frequency amplifier is different in the high and low temperature environment, and therefore the gain change of the intermediate frequency amplification gain at the high and low temperature is compensated by arranging a temperature compensation attenuator.
In addition, the circuit also fully considers the power change of the intermediate frequency signal, can ensure that the power of the intermediate frequency signal in the whole intermediate frequency channel always works in a reasonable interval, and can also ensure that the transmission characteristic and the noise characteristic of the intermediate frequency signal are kept good. Therefore, when the intermediate frequency signal entering from the intermediate frequency signal input end passes through the circuit, the attenuation change of the signal power must be considered, so that after the intermediate frequency signal passes through the circuit, the intermediate frequency signal can have enough power to enter the next stage circuit.
As shown in fig. 7, when the power of the radio frequency signal entering the first matching attenuator 301 from the intermediate frequency signal input terminal is-36.6 dBm, there is a loss of 3dB after passing through the first matching attenuator 301, i.e., the power of the intermediate frequency signal after being output from the first matching attenuator 301 is-39.6 dBm. Then, there is a 2dB attenuation through the first stage intermediate frequency filter 302, i.e., LFCN-6000, with an intermediate frequency signal power of-41.6 dBm. Through the first stage intermediate frequency amplifier 303, the chip UPC3226TB performs gain amplification of 25dB, so that the intermediate frequency signal power is increased to-16.6 dBm, and higher gain amplification is obtained. However, this amplification also causes amplification of the spurious component and is mixed into the intermediate frequency signal, and for this purpose, the second filtering is performed by the second intermediate frequency filter 305, that is, LFCN-8400, and the second matching attenuator 304 (3 dB attenuation) is provided between the second intermediate frequency filter 305 (2 dB attenuation) and the first intermediate frequency amplifier 303, so that the power of the intermediate frequency signal output through the second intermediate frequency filter 305 is-21.6 dBm. Next, the intermediate frequency signal is power amplified by the second stage intermediate frequency amplifier 306 with an amplification gain of 20dB, whereby the power of the intermediate frequency signal is-1.6 dBm. Then sequentially passes through a second stage intermediate frequency filter 307 (3 dB attenuation), a third matched attenuator 308 (3 dB attenuation), a gain equalizer 309 (4 dB attenuation) and a temperature compensation attenuator 310 (5 dB attenuation), and finally outputs an intermediate frequency signal with power of-16.6 dBm. It can be seen that the gain value of each amplifier is reasonably set, the intermediate frequency filter and the matching attenuator are reasonably selected, the power change condition of the intermediate frequency signal can be precisely controlled, and under the condition that the gain and the flatness of the whole intermediate frequency channel are ensured to meet the requirements, the volume of the intermediate frequency channel circuit is optimized by adopting the modes of integrating microwave devices, reducing separation elements, using a single power supply (direct current 5V) and the like, so that the requirement of equipment miniaturization is met.
NF in fig. 7 represents a noise figure, gain represents a Gain value, OP1dB represents a power amplifier input compression point, OIP3 represents an output third-order intermodulation point of the power amplifier, and Po represents an intermediate frequency signal output power value of each component.
The power variation of the intermediate frequency signal in the circuit is shown in fig. 7, and it can be seen that a plurality of matched attenuators, such as a first matched attenuator 301, a second matched attenuator 304, and a third matched attenuator 308, are arranged therein. By arranging the attenuators, good impedance matching can be realized between components between the front stage and the rear stage, the problems of distortion and reverse power in the transmission process of the intermediate frequency signal are avoided, and the intermediate frequency signal can be ensured to have enough power through multistage amplification although certain attenuation is generated.
In order to achieve the miniaturization structural design of the intermediate frequency circuit, as shown in fig. 8, the layout of the intermediate frequency circuit includes a power cavity Q0, a first cavity Q1, a second cavity Q2 and a third cavity Q3, which is called as a cavity herein, and means that the periphery of the intermediate frequency circuit is provided with a metal wall, the height of the metal wall is higher than that of each component in the intermediate frequency circuit, and a metal cover is further added on the upper part of the metal wall, so that the whole intermediate frequency circuit is isolated in one cavity, thereby avoiding electromagnetic interference possibly generated by other external circuits on the intermediate frequency circuit. The power supply cavity Q0 is mainly internally provided with a power supply filter capacitor for stabilizing and filtering the externally input direct current 5V voltage. The first cavity Q1 mainly comprises a first stage intermediate frequency filter chip LFCN-6000 and a first matching attenuator connected in series before the chip LFCN-6000; a chip first intermediate frequency amplifier chip UPC3226TB is arranged at a connecting part Q12 of the first cavity Q1 and the second cavity Q2, and a second matching attenuator and a second stage intermediate frequency filter chip LFCN-8400 are mainly arranged in the second cavity Q2; a second stage intermediate frequency amplifier chip ECG001F-G is provided in the connection Q23 of the second and third cavities Q2 and Q3, and a third stage intermediate frequency filter chip LFCN-2250 is provided in the third cavity Q3, together with a corresponding third matched attenuator, gain equalizer circuit and temperature compensated attenuator chip PXV S. Therefore, the first-stage intermediate frequency filtering is mainly performed in the first cavity, the first filtering is mainly performed on the input intermediate frequency signal, the second-stage intermediate frequency filtering is mainly performed in the second cavity, and the first-stage intermediate frequency power amplification is performed at the joint of the first cavity and the second cavity, so that the intermediate frequency signal after the first intermediate frequency amplification is mainly filtered in the second cavity; the third cavity is mainly used for performing third-stage intermediate frequency filtering, and a second intermediate frequency power amplification is arranged between the second cavity and the third cavity, so that intermediate frequency signals after the second intermediate frequency amplification are mainly used for performing filtering in the third cavity, and finishing the processing of gain equalization and temperature compensation. This arrangement minimizes the nonlinear effects caused by power amplification, and the effects on the rf characteristics of the rf signal, which are mainly filtered in the cavities, and the power amplification is arranged at the junction of the cavities, which is also related to the fact that the power amplification is mainly performed by a single chip, and the power supply of the power amplification chip is also highly required, and the two power amplifiers are mainly arranged at the upper and lower parts of the second cavity, so that the +5v voltage output by the power supply cavity Q0 passes through the second cavity from top to bottom along a substantially straight line to supply power to the chip UPC3226TB and the chip ECG 001F-G. Moreover, it can be seen that the first cavity Q1, the second cavity Q2 and the third cavity Q3 are in a continuous S-shaped structural design, and the structural design has the effect of extending the circuit length in a limited space, and is suitable for the miniaturized application requirement.
Based on the above embodiments, the invention discloses an intermediate frequency circuit for a miniaturized ODU receiving channel, an intermediate frequency signal input end, a first stage intermediate frequency filter electrically connected with the radio frequency signal input end, and a first stage intermediate frequency amplifier, a second stage intermediate frequency filter, a second stage intermediate frequency amplifier, and a third stage intermediate frequency filter sequentially connected in series, which form an intermediate frequency channel circuit of two-stage amplification and three-stage filtering. And a gain equalizer and a temperature compensation attenuator are further cascaded after the third stage intermediate frequency filter. The circuit can well filter clutter and harmonic components in the intermediate frequency signal, provides enough channel gain, ensures the flatness of the intermediate frequency signal in the whole frequency band and the characteristic that the gain is not influenced by high and low temperature, and has the advantages of reducing the volume, reducing the cost, keeping the signal stable and reliable and the like because the selected components are mainly integrated single components.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structural changes made by the present invention and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the present invention.
Claims (9)
1. An intermediate frequency circuit for a miniaturized ODU receiving channel comprises an intermediate frequency signal input end, and is characterized in that the frequency range of an incoming intermediate frequency signal is 950MHz-2150MHz, the intermediate frequency signal input end is firstly connected with an intermediate frequency filter for filtering clutter outside the intermediate frequency signal, then the output end of the intermediate frequency filter is electrically connected with an intermediate frequency amplifier, and the intermediate frequency amplifier outputs the intermediate frequency signal after power amplification;
the intermediate frequency filter and the intermediate frequency amplifier include: the first-stage intermediate frequency filter is electrically connected with the intermediate frequency signal input end, and the first-stage intermediate frequency amplifier, the second-stage intermediate frequency filter, the second-stage intermediate frequency amplifier and the third-stage intermediate frequency filter are sequentially connected in series, and a gain equalizer and a temperature compensation attenuator are further connected behind the third-stage intermediate frequency filter in cascade;
the intermediate frequency circuit is arranged in the cavity, the cavity comprises a power cavity, a first cavity, a second cavity and a third cavity, the power cavity is communicated with the second cavity, and the first cavity, the second cavity and the third cavity are combined into a whole in an S-shaped structure;
the first cavity is internally provided with a first-stage intermediate frequency filter for carrying out first filtering on an input intermediate frequency signal, the second cavity is internally provided with a second-stage intermediate frequency filter for carrying out first-stage intermediate frequency power amplification at the joint of the first cavity and the second cavity, and the intermediate frequency signal after the first-stage intermediate frequency amplification is filtered in the second cavity; and the third cavity performs third-stage intermediate frequency filtering, performs second-stage intermediate frequency power amplification between the second cavity and the third cavity, performs filtering on intermediate frequency signals after the second-stage intermediate frequency amplification in the third cavity, and completes the processing of gain equalization and temperature compensation.
2. The intermediate frequency circuit for a miniaturized ODU reception channel of claim 1 wherein the first stage intermediate frequency filter comprises a chip LFCN-6000 and a first matched attenuator is further connected in series between the chip LFCN-6000 and the intermediate frequency signal input.
3. The intermediate frequency circuit for miniaturized ODU reception channels of claim 2 wherein the first stage intermediate frequency amplifier comprises a chip UPC3226TB, the input of the chip UPC3226TB being electrically connected to the output of the chip LFCN-6000.
4. An intermediate frequency circuit for a miniaturized ODU reception channel according to claim 3, characterized in that the second stage intermediate frequency filter comprises a chip LFCN-8400 and a second matched attenuator is also connected in series between the input of the chip LFCN-8400 and the output of the chip UPC3226 TB.
5. The intermediate frequency circuit for a miniaturized ODU receive channel of claim 4 wherein the second stage intermediate frequency amplifier comprises a chip ECG001F-G and is electrically connected at an input of the chip ECG001F-G to an output of the chip LFCN-8400.
6. The intermediate frequency circuit for a miniaturized ODU reception channel of claim 5 wherein the third stage intermediate frequency filter comprises a chip LFCN-2250 and an input of the chip LFCN-2250 is electrically connected to an output of the chip ECG 001F-G.
7. The intermediate frequency circuit for a miniaturized ODU reception channel of claim 6 further characterized by a gain equalizer connected electrically to the output of the chip LFCN-2250.
8. The intermediate frequency circuit for a miniaturized ODU reception channel of claim 7 further comprising a third matched attenuator in series between the chip LFCN-2250 and the gain equalizer.
9. The intermediate frequency circuit for a miniaturized ODU reception channel of claim 8 further comprising a temperature compensation attenuator in cascade at the output of the gain equalizer.
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| CN201811190610.7A CN109194347B (en) | 2018-10-12 | 2018-10-12 | Intermediate frequency circuit for miniaturized ODU receiving channel |
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| CN201811190610.7A CN109194347B (en) | 2018-10-12 | 2018-10-12 | Intermediate frequency circuit for miniaturized ODU receiving channel |
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| CN109194347A (en) | 2019-01-11 |
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