JP2769563B2 - Logarithmic amplifier - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logarithm of a true logarithmic system which outputs a logarithmic value of an input and is used in a spectrum analyzer, a radar, or the like, and has cascade-connected double gain characteristic amplifiers in multiple stages. Related to amplifiers.

FIG. 3 shows a conventional logarithmic amplifier of this kind. This example is 10 is cascaded double gain characteristic amplifier 11 ₁ to 11 ₁₀ of the same characteristics, the band-pass wave 12 is inserted into the middle. Double gain characteristic amplifier 11 ₁ to 11 respectively _10, for example the gain as shown in Figure 4 is the amplification unit 13 and the gain of 10 dB 0 dB
Consists of the parallel connection of an amplifier 14, a 5 V _i1 following sub input characteristics 15 inputs as shown in FIG. Is the gain 10 dB, the large input characteristics 16 input is above V _i1 is the gain 0 dB.

[Problems to be Solved by the Invention] Since the dual gain characteristic amplifier is composed of two amplifiers 13 and 14, the noise figure (NF) is bad, and even if a transistor having a good noise figure is used, the noise figure is 10dB. You cannot: Therefore, in the conventional logarithmic amplifier shown in FIG.
When used in a wide band without using 12, the maximum input dynamic range was only about 80dB. The input dynamic range by using a band pass duplexer 12 to widen the 100db of 0dB _m ~-100dB _m, 2.5M its passband
It must be limited to Hz or less, and cannot be used where wideband is required. Incidentally, the input dynamic range of 100 dB, and in order to be used in a 10MHz broadband, ideal noise (can not be smaller than this in noise by a semiconductor) is the noise figure of the logarithmic amplifier from a -104 dB _m -
100 dB _m (minimum _{input) - (- 104dB m) =} 4dB next, although the double gain characteristic amplifier 11 ₁ of the noise figure of the first stage is required to be 4dB less, double gain characteristic amplifier as described above is now However, the noise figure is limited to 10 dB, and 4 dB cannot be realized.

An object of the present invention is to increase the input dynamic range,
For example, it can be set to 100 dB, and wide band, for example, 1
An object of the present invention is to provide a logarithmic amplifier that can easily be set to 0 MHz.

[Means for Solving the Problems] According to the present invention, in a logarithmic amplifier in which double gain characteristic amplifiers are cascaded in multiple stages, the first stage double gain characteristic amplifier has a lower noise figure than the latter stage double gain characteristic amplifier. , And an attenuator connected to the output side of the preamplifier circuit. The double gain characteristic amplifier circuit has the same double gain characteristic as that of the subsequent double gain characteristic amplifier, and The saturation voltage of the amplifying section for obtaining the input characteristic is set to be approximately the same as that of the double gain characteristic amplifier at the subsequent stage, that is, the small input characteristic gain times.
The attenuation circuit has the same attenuation ratio as the gain of the preamplifier circuit.

"Embodiment" FIG. 1 shows an embodiment of the present invention, and portions corresponding to those in FIG. 3 are denoted by the same reference numerals. In other words, this example is obtained by cascaded ten double gain characteristic amplifier 11 ₁ to 11 _10, each double gain characteristic amplifier 11 ₁ to 11 ₁₀ indicates the characteristic shown in FIG. 5 for example the same characteristics . Double gain characteristic amplifier 11 _first-stage of the present invention, subsequent double gain characteristic amplifier 1
1 and the preamplifier circuit 21 noise figure is less than _{2-11 10,} a double gain characteristic amplifier circuit 22 connected to the output side, and a connection attenuation circuit 23 on its output side. The preamplifier circuit 21 is, for example, of a parallel injection voltage feedback system, and the gain of the preamplifier circuit 21 is, for example, 10 dB.

The double gain characteristic amplifier circuit 22 is a double gain characteristic amplifier in the subsequent stage.
11 is a _{2-11 10} double gain characteristics and the same characteristics of, in this example is the characteristics shown in FIG. 5, therefore the same configuration. Further, the saturation voltage V _s1 of the amplifying section for obtaining the small input characteristic of the double gain characteristic amplifying circuit 22 is changed to the double gain characteristic amplifier 11 _{2 in the subsequent} stage.
The saturation voltage V _s2 of the amplifying unit 13 (FIG. 4) that obtains a small input characteristic of 1111 ₁₀ is represented by the small input characteristic gain, 10 dB (= 3.1) in this example.
The value is assumed to be doubled. For example the collector current of the amplifying section to obtain a small input characteristics of the double gain characteristic amplifier circuit 22, 3.1 times the collector current of the amplification portion 13 of the small input characteristics of the subsequent double gain characteristic amplifier 11 ₂ to 11 ₁₀ (10 dB times ), The bias of the transistor is increased. The attenuation ratio of the attenuation circuit 23 is equal to the gain of the preamplifier circuit 21, and is 10 dB in this example.

Thus, preamplifier 21 and double gain characteristic comprehensive characteristics of the amplifier circuit 22 is input V _i1 following sub input characteristics 24 as shown in FIG. 2 gain 20dB, and the input V _i or more large input characteristics 25 Results in a gain of 10 dB. Since these characteristics 24 and 25 are attenuated by 10 dB in the attenuator 23, the input Vi ₁ or less is a small input characteristic 15 with a gain of 10 dB.
Next, the input V _i1 or become large input characteristic of the gain 0 dB, the same double gain characteristic and a double gain characteristics amplifier 11 _{2-11 10} in the subsequent stage. Note that the saturation voltage of the amplifier having the small input characteristic of the double gain characteristic amplifier circuit 22 is changed to the double gain characteristic amplifier 11 _{2 in the} subsequent stage.
To 11 if ₁₀ is equal to that V _s2 of the previous synthesis characteristic of amplifier circuit 21 and the dual gain characteristic amplifier circuit 22 is as shown in dotted line in FIG. 2, which is also characteristic is attenuated by the attenuating circuit 23 1
It will not be 5,16.

Previous NF ₁ the noise figure of the amplifier circuit 21, when the gain to the noise figure of G _a, double gain characteristic amplifier circuit 22 and NF _2, the noise figure NF _T double gain characteristic amplifier 11 ₁ of this first stage Becomes Therefore the noise figure NF _T is determined Isuzu noise figure NF ₁ Deho preamplifier circuit 21, becomes small.

The number of cascaded stages of the double gain characteristic amplifier is not limited to 10 stages, and each double gain characteristic is not limited to the 10 dB and 0 dB characteristics. The attenuation circuit 23 is constituted by, for example, a resistance voltage dividing circuit.

[Effects of the Invention] As described above, according to the present invention, the noise figure is conventionally reduced by configuring the first-stage double gain characteristic amplifier with the preamplifier circuit, the double gain characteristic amplifier circuit, and the attenuation circuit. Can be smaller than, for example, 4 dB or less, and the input dynamic range is 0 dB _m
The bandwidth can be widened to 10 MHz even if it is as large as 100 dB (~ -100 dBm ₎ , and the input dynamic range is 80 MHz.
If it is on the order of dB, the band can be remarkably widened without the need for the band pass wave device 12.

[Brief description of the drawings]

Figure 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the gain characteristics of the first-stage dual gain characteristic amplifier 11 ₁ of each section, Figure 3 is a block diagram showing a conventional logarithmic amplifier, the FIG. 4 is a block diagram showing a double gain characteristic amplifier, and FIG. 5 is an output characteristic diagram thereof.

Claims (1)

(57) [Claims] 1. A logarithmic amplifier of a true logarithmic system in which double gain characteristic amplifiers are cascaded in multiple stages, wherein a first stage double gain characteristic amplifier has a smaller noise figure than a latter stage double gain characteristic amplifier. The saturation voltage of the amplifying section connected to the output side of the preamplifier circuit and having the same characteristics as the double gain characteristics of the latter double gain characteristics amplifier and obtaining the small input characteristics thereof, A double gain characteristic amplifier circuit which is approximately double that of the double gain characteristic amplifier, and which is connected to an output side of the double gain characteristic amplifier circuit and has the same gain as that of the preamplifier circuit. A logarithmic amplifier comprising an attenuation circuit having an attenuation ratio.