JP3470432B2 - Signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] The present invention relates to an electronic musical instrument.
For signal processing devices such as DSPs,
The present invention relates to a signal processing device that facilitates a clearing operation of a signal. [0002] 2. Description of the Related Art In an electronic musical instrument, the synthesis and effect
DSPs used to provide fruits, etc.
Meaningless signals are output during
Signal processing so that incorrect signal processing is not
Clear internal registers before starting operation
There is. However, DSP requires high-speed response.
Therefore, it is necessary to clear this internal register at high speed.
You. [0003] SUMMARY OF THE INVENTION Conventional variable length instruction tie
In a general purpose DSP, a simple initialization program
Do not memorize them and execute them in response to external instructions.
Which method was taken, but specialized for music signal processing
DSPs generally have a limited number of program steps
Steps to such an initialization program
Occupied enough steps for the actual signal processing
There is a problem that can not be taken. Further, the register can be reset by hardware.
It is conceivable to configure the DSP element so that
When the SP has such a structure, the chip area becomes large.
And increase the cost and cost.
Was. According to the present invention, a register required by a simple configuration is provided.
Signal processing device that can initialize (data storage unit)
The purpose is to provide a device. [0006] [0007] [Means for Solving the Problems]The inventionIs entered from outside
Data that stores input signal data and operation result data
Executes a predetermined operation on the storage unit and given data
And a processing program to be repeatedly executed
An arithmetic processing program storage unit for storing
Based on the arithmetic processing program to be executed, the data
When the data stored in the storage unit is given to the arithmetic unit,
In addition, the calculation result data obtained by performing the calculation by the calculation unit is described above.
Data transfer means for writing to the data storage unit.
A predetermined initial value for the data storage unit.
Multiple initialization programs to execute value writing
An initialization program storage unit that stores types, and an arithmetic processing
When initialization is instructed during program execution,
Of the currently executed arithmetic processing program
During the interval between the two
Execute any one of them and then execute the arithmetic processing program.
Operation switching means for returning to the program cycle of the system.
It is characterized by having been provided. [0008] [0009] [0010] [0011] [Action]The inventionThe signal processing device ofFaithNo. processing
The signal processing program stored in the program storage means
It operates based on the system.That is, the data transfer means
The data stored in the data storage is given to the
The arithmetic unit performs a predetermined operation on the data. Data transfer
The transmitter writes the data of the operation result in the data storage unit.
Put in. By repeating this operation, the music signal
Configuration, filter processing, and the like.On the other hand, the initialization program
The program is initialized separately from the signal processing program storage unit.
It is stored in the RAM storage unit. When initialization is instructed
Operating the data transfer means with the initialization program
At the same time, data is read from the data storage
Spilled outDeData to the calculation unit instead of
Indicates the initial value in place of the data output by the arithmetic unit.
Write in the storage unit. This allows a simple initialization program
To quickly initialize the required data storage
You. [0012] [0013] [0014] FIG. 1 shows a digital system according to an embodiment of the present invention.
FIG. 2 is a block diagram of a signal processor (DSP). this
The DSP is stored in the microprogram register 11
Read the signal processing program
U. The signal processing program has a 256-step horizontal command.
And the micro program register 11
Also have this storage capacity. Micro program cash register
The writing of the signal processing program to the
The host CPU operates via the CPU interface 10.
U. The horizontal instruction consists of an instruction code (op code) and coefficient data.
Data, memory address and initialization field
This is a fixed-length instruction and is read at the same time. Read out
The instruction code is input to the decoder 14. decoder
14 decodes the instruction code into a decode signal
Transmit to each operation unit. Operation that received this decode signal
The unit performs a corresponding operation. During this operation,
And coefficients are used. Also, the initial value selection field
Registers such as IRAM21 and TRAM22, which will be described later,
Initial value selection command to select the initial value when initializing the
The code is written. The temporary RAM (TRAM) 22 is simply
Delay (Z^-1) And a register that stores values during the calculation
Group. Also, an input RAM (IRAM) 21
Is input from external input signal data or external memory.
Register group that stores the loaded data.
A register group that is also used as a temporary register.
You. The data in IRAM 21 is output to IBUS 23
You. The data of TRAM22 is output to TBUS24
Is done. IBUS23 and TBUS24 each have
Multiplexers 25 and 27 are connected. Multiple
The internal data BUS 18, which will be described later, is
Connected, and “1” as constant value data
Has been entered. The multiplexer 27 is connected to these three buses.
And one of the “1” data
To the ALU 20. To other input terminal of ALU20
Is connected to a multiplexer 28. This multi
The multiplexer 28 outputs the output value of the multiplexer 25,
Output value of chipplier 26, micro program register
11 as a coefficient value or a constant value
One of "1" is selected and input to the ALU 20. Previous
The multiplier 26 is connected to the multiplexer 25.
Data or TBUS selected on IBUS23
From the microprogram register 11 to the data on 24
Multiply the coefficient value to be read. In ALU20,
Data selectively input by the multiplexers 27 and 28
Is calculated and output. During normal operation,
The output of ALU 20 is output through multiplexer 16
Input to the accumulator 17. The accumulator 17
Accumulates the input value to the value stored at that time and internally
Output on the data bus 18. Output on internal data bus
The stored data is stored in the memory address register and data register.
When read by a predetermined circuit such as a star or an output port
First, IRAM21, TRAM22 and multiplexer 2
7 is input. In the above configuration in the DSP, usually the
Multiplication by Luchi pliers 26, addition by ALU 20
And accumulation by the accumulator 17 includes the TRAM 22
Repetition through the circulation path
A filter circuit or the like is realized by the calculation. Here, the multiplexer 16 is connected to the ALU2
Select one of the eight inputs, including the output of
This is a circuit to be input to the mullator 17. Of eight input terminals
The output of the ALU20 is supplied to the 0th input terminal.
The input terminals 1 to 7 have different 7
An initial value for the type is supplied. This initial value is IRAM2
1, the value to be written when initializing the TRAM 22
is there. The first, second, and third input terminals have constant values
"0", "1", and "-1" are supplied, respectively.
You. The four input terminals No. 4 to No. 7 have initial value levels.
An initial value stored in the register 12 is supplied. initial
Writing of the initial value to the value register 12 is performed by the host CPU.
This is performed by the host CPU via the interface 10. The multiplexer 16 has a select terminal
A port circuit (AND circuit group) 15 is connected. this
The gate circuit includes the microprogram register 11
Initial value selection code stored in the initial value selection field
Is entered for each program step. This gate
The fi terminal of the flag control circuit 13 is connected to the control terminal of the circuit 15.
Is entered. fi signal allows register initialization
/ Prohibit signal, when this signal is “1 (H)”
The gate circuit 15 is opened and the initial value selection code is
Input to the multiplexer 16 and output from the ALU 20
In place of the data (No. 0)
Input to the accumulator 17. The flag control circuit 13 has a host CPU interface.
Fi set signal, fi reset via interface 10
A signal is input. Also, the micro program register
11 in the signal processing program written in
And outputting a fi reset signal.
If there is, the fi set signal, fi
A reset signal is input. The flag control circuit 13
The fi signal is set (“1”) / reset based on these signals.
("0"). As described above, the fi signal is set.
Gate circuit 15 is opened when
Stored in the initialization field of the RAM register 11
The initial value selection code is input to the multiplexer 16, and 1
Of the seven types of initial values input to the input terminals
One of them is input to the accumulator 17. FIG. 2 is a detailed diagram of the flag control circuit 13.
is there. The flag control circuit 13 sends the fi from the host CPU.
When the set signal is input, the current execution cycle
To make the next execution cycle the initialization cycle,
Fi is set to "1" from the beginning of the row cycle. Ma
In addition, a fi reset signal is input from the host CPU.
Returns from the next execution cycle to the signal processing cycle.
Reset fi from the beginning of the next execution cycle
I do. Hereinafter, the operation of each unit will be described in detail. A fi set signal or f
When the i reset signal is input, the flip-flop 30
Is set by this signal input. Also flip flip
Rop 31 is set when the fi set signal is input.
Reset when a fi reset signal is input.
You. When the flip-flop 30 is set, the Q signal is
Since it becomes “1”, the flag is busy through the OR circuit 33.
A signal is output. This flag busy signal is
It is input to the U interface 10. This flag busy
While the signal is on, the host CPU interface 1
0 indicates the input of a new fi set signal or fi reset signal.
Do not accept power. The Q signal of the flip-flop 30 is A
The signal is input to the ND circuit 34. Other input of AND circuit 34
LASTST from the clock counter (not shown)
An EP signal is input. The LAST STEP signal is 2
Of the 56-step microprogram, the final step
This is a signal indicating that it is a loop (255 steps). My
Clock program (signal processing program) is executed repeatedly
Therefore, the LAST STEP signal is output from the next step.
This indicates that a new run cycle is starting, so
Set fi in accordance with the instruction of the host CPU.
Reset / reset. LAST STEP signal (“1” signal
Signal from the flip-flop 30 (“1” signal).
Signal passes through the AND circuit 34, the Q signal becomes
The signals are input to the ND circuits 37 and 38. AND circuit 37, 3
8 have input terminals of flip-flop 3
Q signal and / Q signal (/ indicates negative logic) from 1
It is empowered. Therefore, the signal input from the CPU
Is a fi set signal, the AND circuit 37
The output becomes “1” and the signal input from the CPU
If it is a reset signal, the output of the AND circuit 38
Becomes “1”. The output signal of the AND circuit 37 becomes "1".
In this case, the AND circuit 40, the OR circuit 44, and the OR circuit
This "1" signal is transmitted through fi
Output as a signal. The AND circuit 40 has an AN
A LASTSTEP signal similar to that of the D circuit 34 is input.
Therefore, it opens in synchronization with the AND circuit 34, and this “1”
The signal can pass. Also, the delay 48
AND circuit 3 formed by LASTSTEP signal
7 signal from the beginning of the next execution cycle
This is a delay for outputting as Delay 48?
When the fi signal (“1” signal) is output from the
The signal is input to the gate circuit 15 of FIG.
The signal is returned to the AND circuit 46 in the control circuit. This AND times
Normally, a "1" signal is input to the other input terminal of the path 46.
The AND circuit 46 returns from the delay 48
"1" is output in response to the "1" signal. this
The “1” signal is input to the delay 48 via the OR circuit 47
Therefore, after that, the other input of the AND circuit 46 is performed.
Until the output terminal (output of NOR circuit 45) falls to "0"
The fi signal will continue to be "1". On the other hand, a fi reset signal is input from the CPU.
After that, the LAST STEP signal is input and AND
When the output signal of the circuit 38 becomes “1”, AND
This signal is input to the NOR circuit 44 via the circuit 42.
You. The LAST STEP signal is input to the AND circuit 42.
Therefore, this "1" signal passes. NOR circuit 45
Outputs “0” by this “1” input, and
The circuit 46 receives the “1” input from the delay 48.
Is forced to "0", and this "0" signal is OR
The signal is input to the delay 48 via the circuit 47. In addition, this
In this case, the OR circuit 44 does not output "1". I
Therefore, after the fi reset signal is input, LAST
When the STEP signal is input, the fi signal drops to "0".
Will be done. Note that the delay 48 is
Delay to set the fi signal to "0" from the beginning of the cycle
I. Also, a fi set signal and a fi reset
If the signal is written during the microprogram
Are input from the decoder 14. Decoder 14
When the fi set signal is input from the AND circuit 42,
Via OR circuit 44, OR circuit 47 and delay 48
The lever set signal is output as the fi signal. What
The inverted LAS is connected to the other terminal of the AND circuit 42.
Since the TSTEP signal has been input, the
Except for the last step, fi input from the decoder 14
The set signal is transmitted to the delay 48 as it is. De
When the fi signal is output from the
1 gate circuit 15 and the flag system
The signal is returned to the AND circuit 46 in the control circuit. This AND circuit
Normally, a "1" signal is input to the other input terminal of 46.
Therefore, the AND circuit 46 returns from the delay 48
"1" is output by the obtained "1" signal. This "1"
The signal is input to the delay 48 via the OR circuit 47
Therefore, after this, the other input terminal of the AND circuit 46
(The output of the NOR circuit 45)
The number will continue to be "1". On the other hand, the fi reset signal from the decoder 14
Is input through the AND circuit 43 to N
The signal is input to the OR circuit 45. Note that other than the AND circuit 43
LAST STEP signal is input to the other terminal.
Except for the last step of the execution cycle.
The fi reset signal input from the coder 14 remains unchanged
The signal is input to the NOR circuit 45. The NOR circuit 45
Since “0” is output by “1” input, the AND circuit 4
6 is strong even if "1" input is input from delay 48
The signal is dropped to "0", and this "0" signal is
7 to the delay 48. In the description of FIG. 2, the host CPU
Fi set signal input from the host CPU
Reset by the reset signal
The fi set signal input from the decoder 14 is
Reset by the fi reset signal input from
Although described, the fi-set input from the host CPU is used.
Reset signal input from the decoder 14
Can be reset by the
The fi set signal input from the host CPU
It can be reset by a set signal. FIG. 3 shows a host in the flag control circuit having the above configuration.
Fi set signal or fi reset signal from CPU
FIG. 6 is a timing chart of signals of respective parts when input is performed.
You. When the fi set signal is input from the host CPU,
Thereafter, during this execution cycle, the flag busy signal
It becomes “1”. Closing the last step of this run cycle
LASTSTEP signal is input from the clock counter
The flag busy signal at the rise of the next step
At the same time as falling to "0", the fi signal rises. Hos
When the fi reset signal is input from the CPU,
During the row cycle, the flag busy signal is "1". This
From the clock counter to the last step of the execution cycle
When the LASTSTEP signal is input, the next step
When the flag busy signal falls to “0” at the rising edge
In contrast, the fi signal drops to "0", contrary to the fi set signal.
Chiru. FIG. 4 is a diagram showing an example of a simple filter.
You. FIG. 5A shows the filter of FIG.
Shows a microprogram to be realized by arithmetic
You. Further, FIG. 5B shows the actual program of FIG.
The initialization operation when fi is set in a row will be described.
FIG. The operation of FIG. 5A will be described. Where i
nit = 1 means the initial value stored in the initialization field.
The period value selection code is 1, that is, the value of the first input terminal is
Is selected as an initial value, and the fi
When the value becomes “1”, this value is input to the selector 16.
The constant value “0” input to the first input terminal
This indicates that the input is input to the mullator 17. INPUT data to accumulator
To load. INPUT is stored in IRAM21, for example.
It is a provided register. The value in the area T1 in the TRAM 22 is
Input to the multiplier 26 and multiply this value by the coefficient a1.
The multiplication result of the lever is accumulated in the accumulator 17. did
Therefore, the content of the accumulator is INPUT + T1 ×
a1. In addition, as shown in FIG.
This is the contents of the delay stored in the operation of the cycle. The contents of the accumulator 17 are stored in TRAM2
2 to the register T2. But Accumley
The above values still remain in the data 17. The value in area T1 is assigned to multiplier 2
6 and multiply this value by a coefficient a2.
It is accumulated in the accumulator 17. Therefore, accumulate
The content of the lator is INPUT + T1 × a1 + T1 × a2
Becomes Currently stored in the accumulator 17
Transfer the contents to OUT. OUT is, for example, an output buffer
It is. The contents stored in the output buffer are stored in an external circuit (eg,
For example, D / A converter)
You. Write the contents stored in T2 to T1
Put in. As a result, the delay value of the current cycle is
The data is written to the star T1. By repeating the above operation, FIG.
The operation of the indicated filter is performed. By the way, this behavior
Start, the value stored in T1 is indeterminate
Therefore, if it is not cleared, subsequent operations will be affected.
You. Therefore, prior to the start of such a filter operation,
Thus, an initialization cycle is executed. The initialization cycle is
As described above, fi is set to “1” to execute one cycle.
It is realized by performing the cycle. FIG.
0 is written to each area by the clear cycle.
The procedure is shown. If fi = 1, what instruction is
However, the accumulator 17 is selected with init = 1.
Is input. Usually the processed signal is
Transferred through the ALU 20 and the accumulator 17
Therefore, select between ALU 20 and accumulator 17
Data from the ALU 20 to the accumulator 17
Signal to be replaced with another signal (initial value: for example 0)
As a result, all data transferred within this DSP
Can be cleared with the initial value of. In this example, a simple filter circuit is described.
As described above, even when performing more complicated signal processing,
Because it is a combination of arithmetic, addition, and accumulation,
There is no fundamental difference from the data processing. Therefore,
Even complex signal processing like
One execution cycle of the signal processing program with fi = 1
The initialization cycle is executed by executing
Clear all registers required for processing to predetermined initial values
be able to. FIG. 6 shows a DS according to a second embodiment of the present invention.
FIG. 3 shows a block diagram of P. In this embodiment, as shown in FIG.
The same parts in the configuration as those of the first embodiment have the same numbers.
And the description is omitted. In this embodiment, the normal operation
For register initialization separately from the signal processing program for
Built-in initialization program.
Quickly initialize a given register by activating it
The first embodiment differs from the first embodiment in that
You. This DSP is a program dedicated to initialization.
Initialization program register that stores a certain initialization program
A star 50 is provided. Initialization program register 50
The initialization program stored in the
Instead of the parallel instruction format stored in the register 11,
Code indicating the address of the internal register to be initialized.
Register code) and the initial value selection code only.
It is a short form. That is, in the clear cycle
Therefore, it is not possible to execute arithmetic operations such as addition and multiplication.
Since only the initial value is transferred to each register,
Internal register code to be initialized as the initialization program
And the initial value selection code only, and the DSP actually operates.
The instruction for generating the instruction is automatically generated by the instruction generator 53.
In this embodiment, the instruction generator 53 issues an operation code.
This is input to the decoder 14 and converted into a decoded signal.
The instruction generator 53 decodes the decoded signal.
Signal generator directly, this instruction generator 53 and
By switching with the decoder 14, the signal processing cycle and
The initialization cycle can be switched. The host CPU initializes the initialization program
When writing to the program register 50,
The initstep data is input to the data 51. i
nitstep data is the step of the initialization program
This is data indicating a number. The counter 51 is an initialization program.
Address synchronized with the operation clock to the RAM register 50
Enter the address value and enter the
Release the mask flag MASK only during
The initialization program read from the
Command generator 53 and multiplexer 16
I do. The counting operation of the counter 51 is performed at the initialization size.
This is always performed not only during the signal cycle but also during the signal processing cycle.
Of the initialization program during the signal processing cycle.
The output is made by the fi “0” signal in the gate circuit 52.
Has been blocked. The host CPU executes the initialization program,
After initializing the initstep, initialize the DSP
In this case, the fi set signal is sent to the DSP as in the first embodiment.
And output. In a DSP, this fiset signal is
Flag control circuit via host CPU interface 10
Input to the road 13. The flag control circuit 13 is the same as in FIG.
Execution cycle in which the fi set signal is input.
"1" signal of fi is output from the beginning of the next cycle of
You. This signal is supplied to the AND circuit 55 and the multiplexer 5
6 is input to the select terminal. Another of the AND circuit 55
The / MASK signal is input to the input terminal. Ma
The output signal of the AND circuit 55 is input to the gate circuit 52.
Have been. The gate circuit 52 is an initialization program register.
Internal register code read from the
The value selection code is stored in the instruction generator 53 and the
Output to the lexer 16. The multiplexer 56 is f
The input is microprogrammed according to the "1" signal input of i.
Switching from the register 11 side to the instruction generator 53 side (this
At this time, MASK is “0”. ). Note that this
MASK is also input to the multiplexer 56, and fi
= 1 and MASK = 1, the multiplexer 56
Inputs NOP (Not Operation) to the decoder 14.
Power. That is, during the initialization cycle,
The decoder 14 is instructed only during the section where the
Command generator 53 is connected. Note that the instruction generator 53 and the
Delay 54 inserted between the multiplexor 56
Is for adjusting the input timing of the instruction code.
is there. The operation of the DSP having the above configuration will be described. Ma
Host CPU as a setting operation at startup
Write a signal processing program to the black program register 11.
Writes four types of initial values to the initial value register 12
In addition, the initialization program register 50
Program, and initializes the counter 51
Is written as step number data initstep. this
This makes this DSP operable. DSP is micro
Read the signal processing program from the program register 11
And repeat the execution cycle. At this time
The counter 51 responds to the initialization program register 50.
Address, and the initialization program runs in parallel.
Has been read. However, this initialization program
The signal is blocked by the gate circuit 52 and is not output inside the DSP.
No. When the host CPU initializes the registers,
When the fi set signal is input, at the beginning of the next cycle
fi becomes “1” and the AND circuit 55
Circuit 52 is opened and the multiplexer 56 is initialized.
To the generalized program register 50 (instruction generator 53) side
Take the place. As a result, the initialization program register 50
Instruction (internal register code) read from instruction is generated
Command code which is input to the
Is input to the decoder 14 via the multiplexer 56.
It is. Thereby, an initialization operation is performed. Predetermined step
When the execution of the initialization program for the number of
51 is a gate circuit 52 for setting the MASK signal to "1".
Closes, preventing further reading of the initialization program
And the multiplexer has fi = 1 AND
Outputs NOP code to decoder 14 when MASK = 1
I do. This completes the clear operation of the predetermined step.
After that, do not perform any other unnecessary operations in the cycle.
I'm trying. By doing so, the execution program
Program that is simpler than clearing using a program
Thus, the clear operation can be completed in a short time. Also,
The initialization program needs only a short number of steps,
Since the initialization program register can be short,
Micro program register that stores the signal processing program
It may be smaller than the data. Also, the initialization program
Registers are as large as microprogram registers.
If it is configured with the
Several types are stored, and the count
By specifying the start address and the number of steps
Of the initialization programs
It becomes possible to select and read / execute an object. In the above embodiment, the signal transmission path is
The multiplexer 16 for sending the period value is connected to the ALU 20
Inserted between the accumulator 17 and other places,
For example, IBUS23, TBUS24 and ALU20
Between the accumulator 17 and the internal data bus 18
It may be inserted. In the above embodiment, the initial value register 12
Can be set to four types of initial values, but more initial values
Values may be set, and conversely,
Initial values that can be selected by the lexer 16 are commonly used
(For example, “0”). Also, the microphone
In the program, the initial value selection code is set in the initial value field.
But should be set in this initial value field
The initial value may be directly written. The flag control circuit 13 is provided in the above-described embodiment.
It is not limited to one. In particular, in the above embodiment, the fi set
When fi = 1 by the signal, the fi reset signal
Is kept until fi is input.
After executing one processing cycle, fi =
It may be set to 0. Further, the configuration of the first embodiment (claim 1)
Is similarly applicable to DSPs of variable program length.
In this case, the simple initialization process requires many programs.
There is no need to split the ram size. The above embodiment is described in the claims.
The present invention has the following features in addition to the invention described above. "
The operation processing programs of the first and second terms are repeatedly executed.
Microprogram. "," Calculated data
Is circulated between the data storage unit and the arithmetic unit to perform arithmetic processing.
Execute. ", The signal processing device according to claims 1 and 2
According to the processing program, the data is stored in the memory and
The calculation process is performed by circulating between. , "
The logical program is a horizontal instruction program. " [0051] [0052] 【The invention's effect】thisAccording to the invention, a signal processing program
By providing an initialization program memory separate from the storage unit
The data in the device can be quickly saved with a simple initialization program.
The storage unit can be cleared. [0053]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a DSP according to an embodiment of the present invention. FIG. 2 is a block diagram of a flag control circuit of the DSP. FIG. 3 is a timing chart of signals of the flag control circuit. 4 is a diagram showing an example of a filter realized by the DSP. FIG. 5 is a diagram showing a microprogram for realizing the filter by the DSP. FIG. 6 is a block diagram of a DSP according to a second embodiment of the present invention. [Description of Signs] 12-initial value register, 13-flag control circuit, 16-
Multiplexer

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 1/24

Claims (1)

(57) [Claim 1] A data storage unit for storing signal data and operation result data inputted from outside, an operation unit for executing a predetermined operation on given data, An arithmetic processing program storage unit that stores an arithmetic processing program that is repeatedly executed, based on the arithmetic processing program that is repeatedly executed,
A data transfer unit that supplies data stored in the data storage unit to the operation unit and writes operation result data calculated by the operation unit to the data storage unit. An initialization program storage unit for storing a plurality of types of initialization programs for executing the writing of a predetermined initial value to the unit; and the operation processing being repeatedly executed when initialization is instructed during execution of the operation processing program. Operation switching means for executing any one of the plurality of types of initialization programs during a program cycle of the program, and thereafter returning to a program cycle of the arithmetic processing program. Signal processing device.