JPH08190445A - Signal processor - Google Patents

Abstract

PURPOSE: To provide a digital signal processor capable of initializing necessary registers. CONSTITUTION: A signal processing program is stored in a microprogram register 11. The DSP repeats the signal processing program to perform processing of musical sound synthesis, etc. The signal processing program reads data out of an IRAM 21, a TRAM 22, etc., to a multiplier 26, an ALU 20, an accumulator 17, etc., to perform arithmetic processing, writes out data on the arithmetic result to an output port, and also writes the data back to the TRAM 21 and TRAM 22 to use them as delay data. Therefore, input data and the arithmetic result data are circulated between the IRAM 21 and TRAM 22 of a register group, and accumulator 17. Values inputted to the accumulator 17 and the register group are initial values selected by the multiplexer 16 and the signal processing program is utilized to initialize the necessary registers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device such as a DSP used in an electronic musical instrument, and more particularly to a signal processing device which facilitates a clear operation of an internal register.

[0002]

2. Description of the Related Art In an electronic musical instrument, a DSP used for synthesizing a musical tone signal or adding an effect causes a meaningless signal to be output at the start of signal processing or erroneous signal processing due to remaining data. In order to prevent this, it is necessary to clear the internal register before starting the signal processing. However, since the DSP is required to have high-speed response, it is necessary to clear this internal register at high speed.

[0003]

In the conventional variable-length instruction type general-purpose DSP, a simple initialization program is stored and executed according to an external instruction or the like. However, DSPs specialized for musical tone signal processing generally have a limited number of program steps, so if the steps are occupied by such an initialization program, the steps for actual signal processing will be sufficient. There is a problem that it cannot be taken.

It is also possible to configure the DSP element so that the register can be reset by hardware.
When the SP has such a structure, there is a problem that a chip area becomes large, resulting in an increase in size and an increase in cost.

An object of the present invention is to provide a signal processing device capable of initializing a necessary register (data storage unit) with a simple structure.

[0006]

According to the invention of claim 1 of this application, a data storage section for storing signal data and operation result data inputted from the outside, and a predetermined operation for given data are executed. And an arithmetic processing program storage section for storing an arithmetic processing program, and based on the arithmetic processing program, the data stored in the data storage section is given to the arithmetic section, and the arithmetic section performs the arithmetic operation. In a signal processing device having a data transfer unit for writing operation result data to the data storage unit, the data transfer unit is responsive to an initialization instruction to replace the data read from the data storage unit with an initial value. Data switching means for writing an initial value into the data storage unit in place of the data input to the calculation unit or output from the calculation unit is provided. To.

According to a second aspect of the present invention, a data storage section for storing signal data and operation result data input from the outside, an operation section for executing a predetermined operation on given data, and an operation An arithmetic processing program storage unit for storing the processing program, and based on the arithmetic processing program,
In the signal processing device, the data stored in the data storage unit is given to the calculation unit, and the calculation result data obtained by the calculation unit is written into the data storage unit. An initialization program storage unit for storing the data is provided, and when the initialization is instructed, an operation switching unit that operates the data transfer unit by the initialization program, and read from the data storage unit according to the initialization instruction Data switching means for inputting an initial value to the arithmetic unit instead of the stored data, or for writing an initial value to the data storage unit in place of the data output by the arithmetic unit is provided.

The invention of claim 3 of this application is characterized in that the data switching means includes means for selecting one from a plurality of types of candidate values as an initial value.

The invention of claim 4 of this application is characterized in that it is carried out based on specified data described in the arithmetic processing program or the initialization program.

[0010]

The signal processing apparatus according to the first aspect operates based on the signal processing program stored in the signal processing program storage means. The data transfer means gives the data stored in the data storage unit to the arithmetic unit, and the arithmetic unit performs a predetermined arithmetic operation on this data. The data transfer device writes the data of the calculation result in the data storage unit. By repeating this operation, the synthesis of the musical tone signal, the filtering process and the like are executed. When the initialization is instructed, the operation based on the signal processing program is continued, but the data switching means gives the arithmetic unit an initial value instead of the data read from the data storage unit, or the arithmetic unit. The initial value is written in the data storage section in place of the data output by.
As a result, the data storage unit used by this signal processing program can be initialized only by switching the data switching means and executing the normal signal processing program, and there is no need to have a special initialization program.

The signal processing device according to claim 2 normally operates based on the signal processing program stored in the signal processing program storage means, similarly to the signal processing device according to claim 1. On the other hand, the initialization program is stored in an initialization program storage unit different from the signal processing program storage unit. When initialization is instructed, the data transfer means is operated by the initialization program, and the data switching means gives an initial value to the arithmetic section instead of the data data read from the data storage section, or An initial value is written in the data storage unit instead of the data output by the unit. As a result, the necessary data storage unit can be quickly initialized with a simple initialization program.

In the signal processing device according to the third aspect, one initial value written by the data switching means can be selected from a plurality of types of candidate values. As a result, the data storage section can be initialized with the optimum value for the next operation to be started.

Further, according to the invention of claim 4, the selection is performed based on designation data described in the arithmetic processing program or the initialization program. As a result, the initial value can be designated on the program, and initialization can be performed with a plurality of types of initial values for each step.

[0014]

1 is a block diagram of a digital signal processor (DSP) according to an embodiment of the present invention. The DSP sequentially reads out the signal processing program stored in the micro program register 11 and performs its processing. The signal processing program is composed of horizontal instructions of 256 steps, and the micro program register 11
Also has this storage capacity. The host CPU writes the signal processing program to the micro program register 11 via the host CPU interface 10. The horizontal instruction is a fixed-length instruction consisting of an instruction code (opcode), coefficient data, a memory address, and an initialization field, and is read simultaneously. The read instruction code is input to the decoder 14. The decoder 14 decodes this instruction code into a decode signal and sends it to each operation unit. The operation unit that receives this decode signal executes the corresponding operation. Memory addresses and coefficients are used during this operation. Further, in the initial value selection field, an initial value selection code for selecting an initial value when initializing registers such as IRAM 21 and TRAM 22 described later is written.

The temporary RAM (TRAM) 22 is a group of registers for storing a unit delay (Z ^-1 ) and a value in the middle of calculation. In addition, the input RAM (IRAM) 21
Is a register group for storing signal data input from the outside or data taken in from an external memory, and is a register group that is also sometimes used as a temporary register. The data in the IRAM 21 is output to the IBUS 23. The data in the TRAM 22 is output to the TBUS 24. Multiplexers 25 and 27 are connected to the IBUS 23 and TBUS 24, respectively. The multiplexer 27 is also connected to an internal data BUS18 described later, and also receives "1" as constant value data. The multiplexer 27 selects one of the data of the three buses and the data of “1” and inputs it to the ALU 20. The multiplexer 28 is connected to the other input terminal of the ALU 20. The multiplexer 28 selects one of the output value of the multiplexer 25, the output value of the multiplier 26, "1" as a coefficient value or a constant value read from the microprogram register 11, and inputs it to the ALU 20. The multiplier 26 selects the data on the IBUS 23 or the TBUS selected by the multiplexer 25.
The data on 24 is multiplied by the coefficient value read from the micro program register 11. In the ALU 20, the data selected and input by the multiplexers 27 and 28 are calculated and output. During normal operation, the output of this ALU 20 is input to the accumulator 17 via the multiplexer 16. Accumulator 17
The input value is accumulated in the value stored at that time and output on the internal data bus 18. The data output on the internal data bus is read by a predetermined circuit such as a memory address register, a data register, an output port, and the IRAM 21, TRAM 22, and multiplexer 2
7 is input.

In the above structure in the DSP, the multiplication by the multiplier 26, the addition by the ALU 20 and the accumulation by the accumulator 17 are normally repeated through the circulation path including the TRAM 22, and the convolution operation by this results in a filter circuit or the like. Will be realized.

Here, the multiplexer 16 is the ALU 2
It is a circuit that selects one of eight inputs including the output of 0 and inputs the selected one to the accumulator 17. The output of the ALU 20 is supplied to the 0th input terminal out of the 8 input terminals, and the 7th to 7th input terminals are different from each other.
An initial value for the type is supplied. This initial value is IRAM2
1, a value written when the TRAM 22 and the like are initialized. "0", "1", and "-1" are supplied as constant values to the first, second, and third input terminals, respectively. Further, the initial values stored in the initial value register 12 are supplied to the four input terminals Nos. 4 to 7. The initial value is written to the initial value register 12 by the host CPU.
It is performed by the host CPU via the interface 10.

A gate circuit (AND circuit group) 15 is connected to the select terminal of the multiplexer 16. The initial value selection code stored in the initial value selection field of the micro program register 11 is input to this gate circuit for each program step. The fi signal of the flag control circuit 13 is input to the control terminal of the gate circuit 15. The fi signal is a signal for permitting / prohibiting the initialization of the register. When this signal is "1 (H)", the gate circuit 15 is opened and the initial value selection code is input to the multiplexer 16 and output from the ALU 20. Instead of the data (0), the initial values of 1 to 7 are input to the accumulator 17.

A fi set signal and a fi reset signal are input to the flag control circuit 13 via the host CPU interface 10. When the signal processing program written in the micro program register 11 includes a step of outputting the fi set signal and the fi reset signal, the decoder 14 outputs the fi set signal and the fi reset signal.
A reset signal is input. The flag control circuit 13 sets (“1”) / reset (“0”) the fi signal based on these signals. As described above, when the fi signal is set, the gate circuit 15 is opened, the initial value selection code stored in the initialization field of the microprogram register 11 is input to the multiplexer 16, and 1
Any one of the seven types of initial values input to the No. 7 to No. 7 input terminals is input to the accumulator 17.

FIG. 2 is a detailed diagram of the flag control circuit 13. The flag control circuit 13 sends the fi
When the set signal is input, fi is set to "1" from the beginning of the next execution cycle so that the next execution cycle of the current execution cycle is the initialization cycle. When the fi reset signal is input from the host CPU, fi is reset from the beginning of the next execution cycle so as to return to the signal processing cycle from the next execution cycle. The operation of each unit will be described in detail below.

A fi set signal or f from the host CPU
When the i reset signal is input, the flip-flop 30
Is set by this signal input. The flip-flop 31 is set when the fi set signal is input and reset when the fi reset signal is input. When the flip-flop 30 is set, the Q signal becomes "1", so that the flag busy signal is output via the OR circuit 33. This flag busy signal is the host CP
It is input to the U interface 10. While this flag busy signal is on, the host CPU interface 1
0 does not accept input of a new fi set signal or fi reset signal. The Q signal of the flip-flop 30 is A
It is input to the ND circuit 34. The other input terminal of the AND circuit 34 is connected to a LASTST from a clock counter (not shown).
The EP signal is input. The LASTSTEP signal is 2
It is a signal indicating that it is the final step (255 steps) of the 56-step microprogram. Since the micro program (signal processing program) is repeatedly executed, the LASTSTEP signal indicates that a new execution cycle starts from the next step. Therefore, at this timing, fi is set / reset according to the instruction from the host CPU. . When the Q signal (“1” signal) of the flip-flop 30 passes through the AND circuit 34 by the LASTSTEP signal (“1” signal), this Q signal becomes
It is input to the ND circuits 37 and 38. AND circuits 37, 3
To the other input terminals of the flip-flop 3
Q signals and / Q signals (/ indicates negative logic) are input from 1. Therefore, when the signal input from the CPU is the fi set signal, the output of the AND circuit 37 becomes "1" and the signal input from the CPU is fi.
If it is a reset signal, the output of the AND circuit 38 becomes "1".

When the output signal of the AND circuit 37 becomes "1", this "1" signal is fi through the AND circuit 40, the OR circuit 44, the OR circuit 47 and the delay 48.
It is output as a signal. The AND circuit 40 has an AN
Since the LASTSTEP signal similar to that of the D circuit 34 is input, it opens in synchronization with the AND circuit 34, and this "1"
Signals can pass through. Also, the delay 48 is
AND circuit 3 formed by the LASTSTEP signal
This is a delay for outputting the "1" signal of No. 7 as the fi signal from the beginning of the next execution cycle. When the fi signal (“1” signal) is output from the delay 48, this signal is input to the gate circuit 15 of FIG. 1 and returned to the AND circuit 46 in the flag control circuit. Since the "1" signal is normally input to the other input terminal of the AND circuit 46, the AND circuit 46 outputs "1" by the "1" signal returned from the delay 48. Since this "1" signal is input to the delay 48 via the OR circuit 47, the fi signal is "" until the other input terminal of the AND circuit 46 (the output of the NOR circuit 45) falls to "0". 1 ”will be continued.

On the other hand, after the fi reset signal is input from the CPU, the LASTSTEP signal is input and the AND signal is input.
When the output signal of the circuit 38 becomes "1", AND
This signal is input to the NOR circuit 44 via the circuit 42. Since the LASTSTEP signal is input to the AND circuit 42, this "1" signal passes. NOR circuit 45
Outputs "0" by this "1" input, so AND
The circuit 46 is forcibly dropped to "0" even if the "1" input is input from the delay 48, and this "0" signal is ORed.
It is input to the delay 48 via the circuit 47. At this time, the OR circuit 44 does not output "1". Therefore, after the fi reset signal is input, LAST
When the STEP signal is input, the fi signal is dropped to "0". The delay 48 is a delay for setting the fi signal to "0" from the beginning of the next execution cycle.

When the fi set signal and the fi reset signal are written in the microprogram, they are input from the decoder 14. Decoder 14
When the fi set signal is input from the AND circuit 42,
This fi set signal is output as a fi signal via the OR circuit 44, the OR circuit 47, and the delay 48. Note that the other terminal of the AND circuit 42 has an inverted LAS
Since the TSTEP signal is input, the fi input from the decoder 14 is input except for the final step of the execution cycle.
The set signal is transmitted to the delay 48 as it is. When the fi signal is output from the delay 48, this signal is input to the gate circuit 15 of FIG. 1 and returned to the AND circuit 46 in the flag control circuit. Since the "1" signal is normally input to the other input terminal of the AND circuit 46, the AND circuit 46 outputs "1" by the "1" signal returned from the delay 48. This "1"
Since the signal is input to the delay 48 via the OR circuit 47, the fi signal continues to be "1" until the other input terminal of the AND circuit 46 (the output of the NOR circuit 45) drops to "0". Will be done.

On the other hand, when the fi reset signal is input from the decoder 14, this signal is set to N via the AND circuit 43.
It is input to the OR circuit 45. Since the inverted LASTSTEP signal is input to the other terminal of the AND circuit 43, the fi reset signal input from the decoder 14 is input to the NOR circuit 45 as it is, except for the final step of the execution cycle. Since the NOR circuit 45 outputs "0" by this "1" input, the AND circuit 4
6 is forcibly dropped to “0” even if the “1” input is input from the delay 48, and this “0” signal is applied to the OR circuit 4
It is input to the delay 48 via 7.

In the description of FIG. 2, the host CPU
The fi set signal input from the host CPU is reset by the fi reset signal input from the host CPU, and the fi set signal input from the decoder 14 is reset by the decoder 14.
The fi reset signal input from the host CPU is used for resetting, but the fi set signal input from the host CPU can also be reset by the fi reset signal input from the decoder 14, and the fi reset signal input from the decoder 14 is input. The fi set signal can be reset by a fi reset signal input from the host CPU.

FIG. 3 is a timing chart of signals of respective parts when a fi set signal or a fi reset signal is input from the host CPU to the flag control circuit having the above configuration. When the fi set signal is input from the host CPU,
After this, the flag busy signal becomes "1" during this execution cycle. When the LASTSTEP signal is input from the clock counter in the final step of this execution cycle, the flag busy signal drops to "0" and the fi signal rises at the rising edge of the next step. Even when the fi reset signal is input from the host CPU, the flag busy signal becomes "1" during the execution cycle. When the LASTSTEP signal is input from the clock counter in the final step of this execution cycle, the flag busy signal drops to "0" at the rising edge of the next step, and the fi signal drops to "0" in contrast to the above fi set signal. .

FIG. 4 is a diagram showing an example of a simple filter. Further, FIG. 5A shows a microprogram for realizing the filter of FIG. 4 by the calculation of the DSP. Further, FIG. 5B is a diagram for explaining the initialization operation when fi is set during execution of the program of FIG.

The operation of FIG. 5A will be described. Where i
nit = 1 means that the initial value selection code stored in the initialization field is 1, that is, the value of the first input terminal is selected as the initial value, and the fi is “1”. At this time, this value is input to the selector 16 and the constant value “0” input to the first input terminal is input to the accumulator 17.

The INPUT data is loaded into the accumulator. The INPUT is a register provided in the IRAM 21, for example.

The value in the area T1 in the TRAM 22 is input to the multiplier 26, this value is multiplied by the coefficient a1, and the multiplication result is accumulated in the accumulator 17. Therefore, the contents of the accumulator are INPUT + T1 ×
It becomes a1. As shown in FIG. 4, the area T1 is the content of the delay stored in the operation of the previous cycle.

The contents of the accumulator 17 are stored in the TRAM 2
2 to the register T2. However, the above value still remains in the accumulator 17.

The value in the area T1 is assigned to the multiplier 2
6 is input, this value is multiplied by a coefficient a2, and the multiplication result is accumulated in the accumulator 17. Therefore, the contents of the accumulator are INPUT + T1 × a1 + T1 × a2
Becomes

The contents currently stored in the accumulator 17 are transferred to OUT. OUT is, for example, an output buffer. The contents stored in the output buffer are read at appropriate times by an external circuit (for example, D / A converter) or the like.

The contents stored in T2 are written in T1. As a result, the delay value of this cycle is written in the delay register T1.

By repeating the above operation, the operation of the filter shown in FIG. 4 is executed. By the way, when this operation is started, the value stored in T1 is indefinite, so that if it is not cleared, it affects the subsequent calculation. Therefore, an initialization cycle is executed prior to the start of such filter operation. The initialization cycle is
As described above, it is realized by setting fi to "1" and performing one execution cycle. FIG. 6B shows a procedure in which 0 is written in each area by this clear cycle.

When fi = 1, the value "0" selected at init = 1 is input to the accumulator 17 for any instruction. Normally, the signal to be processed is transferred via the ALU 20 and the accumulator 17, so a selector is inserted between the ALU 20 and the accumulator 17 so that the signal sent from the ALU 20 to the accumulator 17 is another signal (initial value: 0, for example). By replacing with, it is possible to clear all the data transferred in this DSP with this initial value.

In this example, a simple filter circuit is explained, but even in the case of performing more complicated signal processing, since it is a combination of multiplication, addition and accumulation, there is basically no difference from the above filter processing. . Therefore, in any complicated signal processing, the initialization cycle is executed by setting fi = 1 before the start and executing the signal processing program for one execution cycle, and registers necessary for signal processing are set. All can be cleared to predetermined initial values.

FIG. 6 shows a DS according to the second embodiment of the present invention.
A block diagram of P is shown. In this embodiment, the same parts as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, in addition to the signal processing program for normal operation, an initialization program for register initialization is built in, and this is activated during the initialization cycle so that a predetermined register is quickly initialized. This is different from the first embodiment in that.

This DSP has an initialization program register 50 for storing an initialization program which is a program dedicated to initialization. Initialization program register 50
The initialization program stored in is not the parallel instruction format stored in the microprogram register 11,
This is a simple format consisting only of a code indicating the address of the internal register to be initialized (internal register code) and an initial value selection code. In other words, in the clear cycle, arithmetic operations such as addition and multiplication are not executed and the initial value is only transferred to each register. Therefore, the initialization program uses the internal register code and the initial value selection code to be initialized. The instruction generator 53 automatically generates an instruction for actually operating the DSP.
In this embodiment, the instruction generator 53 generates an opcode and inputs it to the decoder 14 to convert it into a decode signal. However, if the instruction generator 53 is configured to directly generate a decode signal, By switching between the instruction generator 53 and the decoder 14, the signal processing cycle and the initialization cycle can be switched.

When the host CPU writes the initialization program in the initialization program register 50, it simultaneously inputs the initstep data to the counter 51. i
The nitstep data is data indicating the number of steps of the initialization program. The counter 51 inputs an address value synchronized with the operation clock to the initialization program register 50, releases the mask flag MASK only in the section of initstep, and generates an instruction for the initialization program read from the initialization program register 50. The device 53 and the multiplexer 16 can be reached. The counting operation of the counter 51 is always performed not only during the initialization cycle but also during the signal processing cycle, and the output of the initialization program during the signal processing cycle is generated by the gate circuit 52 by the "0" signal of fi. It has been blocked.

The host CPU uses the initialization program,
When the DSP is initialized after the setting of initstep, the fi set signal is output to the DSP as in the first embodiment. In the DSP, this fi set signal is input to the flag control circuit 13 via the host CPU interface 10. The flag control circuit 13 has the same configuration as that of FIG. 2, and outputs the fi "1" signal from the beginning of the cycle next to the execution cycle to which the fi set signal is input. This signal is the AND circuit 55 and the multiplexer 5
6 is input to the select terminal. The / MASK signal is input to the other input terminal of the AND circuit 55. The output signal of the AND circuit 55 is input to the gate circuit 52. The gate circuit 52 outputs the internal register code and the initial value selection code read from the initialization program register 50 to the instruction generator 53 and the multiplexer 16, respectively. In addition, the multiplexer 56 is f
The input is switched from the side of the micro program register 11 to the side of the instruction generator 53 in response to the input of the signal "1" of i (MASK is "0" at this time). MASK is also input to the multiplexer 56, and fi
= 1 and MASK = 1, the multiplexer 56
Inputs NOP (Not Operation) to the decoder 14. That is, in the initialization cycle, the decoder 14 and the instruction generator 53 are connected only in the section in which the initialization program is actually read. In addition, the delay 54 inserted between the instruction generator 53 and the multiplexer 56.
Is for adjusting the input timing of the instruction code.

The operation of the DSP having the above configuration will be described. First, as a setting operation at startup, the host CPU writes a signal processing program in the micro program register 11, four types of initial values in the initial value register 12, and an initialization program in the initialization program register 50. The step count data initstep of the initialization program is written in the counter 51. This enables the DSP. The DSP reads the signal processing program from the micro program register 11 and repeatedly executes the execution cycle. At this time, the counter 51 simultaneously outputs the address to the initialization program register 50, and the initialization program is also read in parallel. However, this initialization program is blocked by the gate circuit 52 and is not output inside the DSP.

When the host CPU inputs the fi set signal to initialize the register, fi becomes "1" at the beginning of the next cycle, the AND circuit 55 opens the gate circuit 52, and the multiplexer 56 initializes. It is switched to the computerized program register 50 (instruction generator 53) side. As a result, the instruction (internal register code) read from the initialization program register 50 is input to the instruction generator 53, and the instruction code created based on this is input to the decoder 14 via the multiplexer 56. As a result, the initialization operation is executed. When the initialization program of a predetermined number of steps is completed, the counter 51 sets the MASK signal to "1" so that the gate circuit 52
Is closed to prevent the reading of the initialization program after that, and the multiplexer is fi = 1 AND
When MASK = 1, the NOP code is output to the decoder 14. As a result, after the clear operation of the predetermined step is completed, other unnecessary operations are not executed in the cycle.

By doing so, the clearing operation can be completed in a short time with a simple program as compared with the case where the execution program is used for clearing. Also,
Since the initialization program requires only a short number of steps and the instructions may be short, the initialization program register may be smaller than the micro program register storing the signal processing program. Further, when the initialization program register is formed to have the same size as the micro program register, a plurality of types of initialization programs are stored and the counter 51 is instructed of the count start address and the number of steps. As a result, it is possible to select and read out and execute an appropriate one from the plurality of types of initialization programs.

Although the multiplexer 16 for sending the initial value to the signal transmission path is inserted between the ALU 20 and the accumulator 17 in the above-mentioned embodiment, at a place other than this,
For example, it may be inserted between the IBUS 23, TBUS 24 and the ALU 20 or between the accumulator 17 and the internal data bus 18.

Further, in the above embodiment, the initial value register 12
Although it is possible to set four kinds of initial values, it is possible to set more initial values, and conversely, an initial value that can be selected by the multiplexer 16 is a commonly used value (for example, “0”). "). Further, in the above micro program, the initial value selection code is stored in the initial value field, but the initial value to be set in this initial value field may be directly written.

The flag control circuit 13 is not limited to that of the above embodiment. In particular, in the above embodiment, when fi = 1 is set by the fi set signal, it remains fi = 1 until the next fi reset signal is input. However, after fi = 1, the processing cycle is automatically executed after one cycle is executed. fi =
It may be set to 0.

The configuration of the first embodiment (claim 1) is also applicable to a DSP having a variable program length, and in this case, a large program size is required for simple initialization processing. No need to spend.

The above embodiment has the following features in addition to the invention described in the claims. "The arithmetic processing program according to claims 1 and 2 is a microprogram that is repeatedly executed.", "The arithmetic processing is executed by circulating the data to be arithmetically operated between the data storage unit and the arithmetic unit.", "The signal processing device according to claims 1 and 2 performs arithmetic processing by circulating data between a memory and an arithmetic unit according to an arithmetic processing program.", "The arithmetic processing program is a horizontal instruction program. . "

[0051]

As described above, according to the present invention, since the data storage unit used by the signal processing program can be initialized while the signal processing program is being executed, the initialization program is not particularly required and necessary. Only the data storage unit can be initialized.

According to the second aspect of the present invention, since the initialization program memory different from the signal processing program storage section is provided, the data storage section in the apparatus can be cleared quickly with a simple initialization program. be able to.

According to the third aspect of the invention, the data storage section is initialized with one initial value selected by the signal processing program or the initialization program from a plurality of types of initial values during the initialization operation. As a result, the data storage section can be initialized with the optimum value for the next operation to be started. Moreover, since the selection is performed based on the selection data written in the signal processing program or the initialization program, the program can select an arbitrary initial value.

[Brief description of drawings]

FIG. 1 is a block diagram of a DSP which is an embodiment of the present invention.

FIG. 2 is a block diagram of a flag control circuit of the DSP.

FIG. 3 is a timing chart of signals of the flag control circuit.

FIG. 4 is a diagram showing an example of a filter realized by the DSP.

FIG. 5 is a diagram showing a microprogram for realizing the filter with a DSP.

FIG. 6 is a block diagram of a DSP which is a second embodiment of the present invention.

[Explanation of symbols]

12-initial value register, 13-flag control circuit, 16-
Multiplexer

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Claims (4)

[Claims] 1. A data storage unit for storing signal data and calculation result data input from the outside, a calculation unit for executing a predetermined calculation on given data, and a calculation processing program for storing a calculation processing program. A storage unit, and data transfer means for supplying the data stored in the data storage unit to the calculation unit based on the calculation processing program and writing the calculation result data calculated by the calculation unit to the data storage unit. In the signal processing device having, the data transfer means inputs an initial value to the arithmetic unit instead of the data read from the data storage unit in response to an initialization instruction, or outputs the arithmetic unit. The signal processing device is provided with data switching means for writing an initial value to the data storage section instead of the data. 2. A data storage unit that stores signal data and calculation result data input from the outside, a calculation unit that executes a predetermined calculation on given data, and a calculation processing program that stores a calculation processing program. A storage unit, and data transfer means for supplying the data stored in the data storage unit to the calculation unit based on the calculation processing program and writing the calculation result data calculated by the calculation unit to the data storage unit. In the signal processing device having the above, an initialization program storage section for storing the initialization program is provided, and when the initialization is instructed, the operation switching means for operating the data transfer means by the initialization program, and the initialization instruction. In response to this, an initial value is input to the arithmetic unit instead of the data read from the data storage unit, or the arithmetic unit outputs the initial value. Signal processing device an initial value instead of the data, characterized in that a data switching means for writing in the data storage unit. 3. The data switching means includes means for selecting one of a plurality of types of candidate values as an initial value.
Alternatively, the signal processing device according to claim 2. 4. The signal processing apparatus according to claim 3, wherein the selection is performed based on designated data described in the arithmetic processing program or the initialization program.