JP2000322256A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an information processor which reduces the processing time of an entire program by realizing the branch decision processing, which is performed by plural operation instructions, with one conditional branch instruction. SOLUTION: In a PSW group 5, each PSW propagates contents of an operation state flag held in itself to another PSW of the next stage at each time of operation execution in an operation circuit 3, and the latest operation state flag inputted from the operation circuit 3 thereafter is held in a PSW 0. An operation state flag logical operation circuit 8 performs logical operation indicated by an operation state flag control instruction execution circuit 9. In the case of a conditional branch instruction, an instruction fetch circuit 10 refers to the output of the operation state flag logical operation circuit 8. Since the output of the operation state flag logical operation circuit 8 is the result of several past logical operations of operation state flags in the operation circuit 3, the condition decision processing which is performed by plural operation instructions is executed by one conditional branch instruction in this information processor by this operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to an information processing apparatus for determining a conditional branch instruction based on the operation results of a plurality of operation state flags.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing an example of a conventional information processing apparatus. In this information processing apparatus, an arithmetic circuit (AL
U) 3, when the instruction acquired by the instruction register 11 is an arithmetic instruction, executes the arithmetic indicated by the instruction register 11 on the contents of the general-purpose registers 1 and 2, and outputs the arithmetic result. While being stored in the general-purpose register 4, only the operation state flag is stored in a register (hereinafter, PSW) 5 'for storing the operation state. Instruction fetch circuit 1
If the instruction stored in the instruction register 11 is a conditional branch instruction, 0 refers to only the operation state flag of the immediately preceding operation instruction stored in the PSW 5 ′ and determines whether to change the instruction acquisition address. (Ie, whether or not to execute a branch).

As described above, in an information processing apparatus which can refer only to the operation state flag of the immediately preceding operation instruction in determining the condition of the conditional branch instruction, the branch / non-branch is determined based on the values of the operation state flags in a plurality of operation instructions. When executing the condition determination process, it is necessary to temporarily perform a branch process by a conditional branch instruction for each operation instruction.

In other words, as the number of operations required for the condition determination increases, the number of redundant conditional branch instructions increases in the information processing apparatus of FIG. 6, and as a result, the number of instructions in the entire program increases. It will put pressure on the available storage device area. Also, the time required to acquire such a large program by the instruction fetch circuit 10 increases,
This may cause a reduction in the processing capability of the entire information processing apparatus.

Further, in the condition judgment processing program constituted by a plurality of conditional branch instructions as described above, the execution path of the program changes depending on whether or not each conditional branch instruction branches. As a result, the execution time of the condition determination processing program varies depending on the determination result. This becomes a problem when the information processing apparatus of FIG. 6 is applied to real-time control of equipment as one example.

In order to always realize a process with a uniform control time, a waiting instruction is added to a program so that the same instruction execution time is obtained regardless of whether the result of branch determination processing branches or does not branch. It is necessary for the program creator to devise this. As a specific example, in the general information processing apparatus shown in FIG. 6, there is a program that realizes a process of branching to the branch destination address label1 only when all of the expressions 1 to 3 shown in Table 1 are satisfied. .

[0007]

[Table 1] Here, FIG. 7 is a diagram showing a program for realizing processing for branching to the branch destination address label1 only when all of the expressions 1 to 3 shown in Table 1 are satisfied, and FIG. 8 is used in the program of FIG. FIG. 4 is a diagram illustrating the meaning of each machine language instruction.

In the program shown in FIG. 7, a temporary conditional branch instruction is prepared for each comparison operation in order to make the determination of Expressions 1 to 3 (lines 2, 4, 6, 8, 10, and 12). After that, a branch instruction for realizing the condition for the address (label1) where the processing is to be actually branched is executed (line 13). In the example of FIG. 7, the temporary conditional branch instructions described in the second, fourth, sixth, eighth, tenth, and twelfth lines are redundant.

In order to solve the above-mentioned problem, there has been conventionally provided a mechanism having a plurality of operation state flags, and selecting and operating the operation state flags to determine the condition branch instruction. A processing apparatus is known (JP-A-60-258647). FIG. 9 shows a block diagram of an example of this conventional information processing apparatus. In the figure, when a conditional branch instruction is executed, an operation state flag selection pattern read from the memory 14 is sent to the multiplexer 15 in accordance with the address set in the address register 13 and a plurality of operation states are selected. The flag is sent to the logic operation circuits 16-18. Logical operation circuit 16-1
Reference numeral 8 executes a logical operation between a plurality of input operation state flags, and sends each operation result to the multiplexer 19. The conditional branch circuit 20 executes a conditional branch based on a logical operation result (a logical operation signal between a plurality of operation state flags) selected by the multiplexer 19 based on the logical operation selection signal.

[0010]

The above-described conventional information processing apparatus shown in FIG. 9 can perform branching, but has the following problems. The first problem is that in the conventional device shown in FIG. 9, since it is necessary to specify which of the operation state flag storage registers in which a plurality of operation results exist in an instruction, the instruction is stored in one instruction. The instruction bit length is increased, resulting in a larger total program size.

The second problem is that the program creator needs to separately create an operation state flag selection pattern in the area of the memory 14, so that the overall size of the program is further increased, and the maintenance and management of the program is also performed. Is complicated.

The present invention has been made in view of the above points,
It is an object of the present invention to provide an information processing apparatus capable of implementing a branch determination process determined by a plurality of operation instructions with a single conditional branch instruction and reducing the processing time of the entire program.

[0013]

According to the present invention, there is provided an instruction register for storing an instruction to be executed;
An operation means for executing an operation based on the operation instruction from the instruction register and outputting an operation state flag together with the operation result;
A plurality of serially connected registers for storing the operation state flags, and a plurality of operation state flags sequentially stored in the order of operation of the operation means in each of the plurality of registers. A logic operation means for performing a logic operation by executing a calculation state flag control instruction for decoding the contents of the instruction register and outputting a control signal to the logic operation means when the instruction fetched into the instruction register is an operation flag control instruction A circuit and an address to acquire an instruction are held, an instruction corresponding to the address is acquired from an instruction bus and output to an instruction register, and a logical operation is performed when the instruction acquired in the instruction register is a conditional branch instruction. An instruction fetch circuit for referring to the output result of the means and determining the address of the next instruction to be obtained based on the truth or falseness thereof. That.

Each of the plurality of registers transfers the storage operation state flag of each of the plurality of registers to the next-stage register each time the operation is performed by the arithmetic means. Discard the storage operation state flag,
The latest operation state flag is held in the first stage register.

According to the present invention, a plurality of registers connected in series store the latest operation state flag to the operation state flag at the time of a plurality of previous operations equal to the number of registers, respectively. The specified logical operation is simultaneously performed by the logical operation means on several operation state flags from the latest one specified by the instruction execution circuit, and the output result of the logical operation means is branched / non-branched by a conditional branch instruction. Since it is used for the determination, the branch determination processing (condition determination determined by a plurality of conditions) determined by a plurality of operation instructions can be realized by one (one-step) conditional branch instruction.

Here, the logical operation means is one of a plurality of operation state flags respectively output from the plurality of registers.
A mask circuit for invalidating an operation state flag older than that specified by the operation state flag control instruction execution circuit;
Of the valid operation state flags output from the mask circuit, a part is inverted according to the specification of the operation state flag control instruction execution circuit, and the rest is output to the inversion circuit for normal rotation and the output operation state flag of the inversion circuit. On the other hand, it can be constituted by an operation state flag logic operation circuit which executes the operation specified by the operation state flag control instruction execution circuit and outputs the operation result via the instruction fetch circuit.

[0017]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of an information processing apparatus according to the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals. In FIG. 1, an instruction register 11 stores an instruction to be executed, and outputs its contents to an operation circuit (ALU) 3, an operation state flag control instruction execution circuit 9, and an instruction fetch circuit 10. If the instruction acquired by the instruction register 11 is an arithmetic instruction, the arithmetic circuit 3 executes the arithmetic indicated by the instruction register 11 on the contents of the general-purpose register 1 and the general-purpose register 2 and outputs the result to the general-purpose register. While being stored in the register 4, an operation state flag (information such as occurrence of borrowing, the operation result becomes 0, etc.) is output to the PSW group (register group for storing the operation state) 5.

The PSW group 5 has a structure in which n pieces of PSWs from PSW0 to PSWn are connected in series. When the operation is performed by the operation circuit 3, the contents of the operation state flags stored in the PSW0 are stored. Shifts the contents of the operation state flags stored in PSWi (i = 0 to n-1) to PSWi + 1, for example, so that the contents of the operation state flags stored in PSW1 are in PSW2. Stores the operation state flag of the operation performed by the operation circuit 3.

The instruction fetch circuit 10 holds an address for acquiring an instruction, acquires an instruction corresponding to the address from the instruction bus 12, and outputs the acquired instruction to the instruction register 11. Thereafter, the instruction fetch circuit 10 updates the address for acquiring the instruction to the address of the instruction to be executed next. The operation state flag mask circuit 6 receives the operation state flags stored in the PSW group 5 as an input, and validates the number of operation state flags specified by the operation state flag control instruction execution circuit 9 to make the operation state flag inverting circuit 7 Output to

The operation state flag inverting circuit 7 receives the operation state flags output from the operation state flag mask circuit 6 as inputs and inverts the number of operation state flags specified by the operation state flag control instruction execution circuit 9. , And outputs the operation state flag, which is not instructed, to the operation state flag logic operation circuit 8 while keeping the normal rotation. Operation state flag logic operation circuit 8
Receives, as input, all operation state flags output from the operation state flag inversion circuit 7, performs the logical operation indicated by the operation state flag control instruction execution circuit 9, and outputs the logical operation result to the instruction fetch circuit 10. I do.

If the instruction fetched into the instruction register 11 is an operation flag control instruction, the operation state flag control instruction execution circuit 9 decodes the contents of the instruction register 11 and stores the operation state flag in the operation state flag mask circuit 6. The number of flags to be validated, the number of inversion of the operation state flag in the operation state flag inversion circuit 7 and the type of logical operation (logical product or logical sum) to be applied to the operation state flag in the operation state flag logical operation circuit 8 Are output.

The instruction fetch circuit 10 includes an instruction register 1
If the instruction acquired in step 1 is a conditional branch instruction, the output result of the operation state flag logical operation circuit 8 is referred to, and based on the truth or false, the address of the next instruction to be acquired is determined.

Next, the operation of this embodiment will be described. In the present information processing apparatus, if the instruction acquired from the instruction fetch circuit 10 and stored in the instruction register 11 is an arithmetic instruction, the arithmetic circuit 3 applies the instruction register 11 to the contents of the general-purpose registers 1 and 2. Is performed, and the result is stored in the general-purpose register 4, and a calculation state flag including information such as whether a borrow occurs in the calculation result or the calculation result becomes 0 is set in the PS.
Output to W group 5.

N PSWs from PSW0 to PSWn
Each time an operation is performed in the arithmetic circuit 3, the PSW group 5 includes the operation state flag stored in the PSW0 in the PSW1 and the operation state flag stored in the PSW1 in the PSW2. So the next stage PSW
The contents of the operation state flags held by the respective circuits are propagated (at this time, the operation state flags held by PSWn are discarded). Save in PSW0.

Each of PSW0 to PSWn operates as described above, whereby PSW0 has an operation state flag executed by operation circuit 3 immediately before, and PSW1 has an operation state flag executed by operation circuit 3 immediately before. The state flag is set in the PSW2, and the operation state flag executed by the operation circuit 3 two times before is set in the PSW2.
The operation state flag executed by the operation circuit 3 n times ago is stored in Wn. In other words, the PSW group 5 stores the operation state flags in the operation circuit 3 up to n times in order from the latest one.

In the present information processing apparatus, when the instruction stored in the instruction register 11 is an operation state flag control instruction, the operation state flag control instruction In the operation state flag mask circuit 6, the number of operation state flags to be inverted in the operation state flag inversion circuit 7, and the type of logical operation to be executed (logical product or logical sum) in the operation state flag logical operation circuit 8, respectively. Is output.

The operation state flag mask circuit 6 invalidates the operation state flags older than those specified by the operation state flag control instruction execution circuit 9 among the operation state flags input from the PSW group 5. The operation state flag mask circuit 6 selects how many previous operation state flags among the operation state flags stored in the PSW group 5 are used for the determination of the branch processing.

The operation state flag inverting circuit 7 inverts the operation state flags out of the operation state flags specified by the operation state flag control instruction execution circuit 9 among the operation state flags output from the operation state flag mask circuit 6, The operation state flag is output to the logic operation circuit 8. With this circuit, PS
By partially inverting the operation state flag stored in Wn and performing an operation in the operation state flag logic operation circuit 8, PS
Not only when all of PSW0 to PSWn stored in W group 5 are true, but also all the operation state flags of PSW0 to PSWm are true and PSWm + 1 to PSWm + 1
Conditional branch processing for a condition where the operation state flag up to SWn is false can be realized by one conditional branch instruction.

The operation state flag logical operation circuit 8 performs a logical operation instructed by the operation state flag control instruction execution circuit 9 on the operation state flag selected / inverted by the operation state flag mask circuit 6 and the operation state flag inversion circuit 7. And outputs the result to the instruction fetch circuit 10.

The instruction fetch circuit 10 includes an instruction register 1
If the instruction stored in 1 is a conditional branch instruction, the output of the operation state flag logical operation circuit 8 is referred to, and only when the output is true, the instruction acquisition address held by the instruction is read. The address is changed to the branch destination address specified by the register 11. If the output of the operation state flag logical operation circuit 8 is false, the instruction fetch circuit 10
Increments the instruction acquisition address held by itself by 1,
The address to acquire the next instruction.

As described above, the output of the operation state flag logical operation circuit 8 is the result of the logical operation of the operation state flag in the operation circuit 3 for the past several times. It is possible to execute a condition determination process determined by an instruction using one conditional branch instruction.

Hereinafter, the operation of the information processing apparatus will be described with a specific example. FIG. 2 is a diagram showing a program that branches only when all of the formulas 1 to 3 shown in Table 1 are satisfied using the present information processing apparatus, and FIG. 3 is used in the program of FIG. FIG. 4 is a diagram illustrating the meaning of each machine language instruction.

In the first to sixth lines of the program in FIG. 2, a comparison operation for confirming the expressions 1 to 3 in Table 1 is performed. By these comparison operations, PSW0 to PSW5
4A, 4B, and 4C, the operation states of the comparison operation performed by the operation circuit 3 are sequentially set. Execution of the operation state flag control instruction on the seventh line of the program in FIG.
The operation state flag inversion circuit 7 and the operation state flag logic operation circuit 8 are controlled as follows.

At the end of the comparison process between r3 and e in the sixth line of the program in FIG.
4C and FIG. 5 show the held contents of 0 to PSWn. In this state, when the operation state flag control instruction on the seventh line of the program is executed, the contents shown in FIG. As described above, the operation state flag mask circuit 6 outputs the PSW0 to PSW out of the operation state flags stored in the PSW group 5.
The latest six operation state flags stored in W5 are output to the operation state flag inversion circuit 7 as valid operation state flags.

The operation state flag inverting circuit 7 includes, among the operation state flags stored in the PSW0 to PSW5 output from the operation state flag mask circuit 6, as shown in FIG.
The operation state flags stored in PSW3 to PSW5 are inverted, and the latest three operation state flags stored in PSW0 to PSW2 are output to the operation state flag logic operation circuit 8 as they are (forward rotation). Operation state flag logic operation circuit 8
Takes the logical product of the operation state flags output from the operation state flag inversion circuit 7 and outputs the result to the instruction fetch circuit 10.

As described above, by executing the operation state flag control instruction on the seventh row in FIG.
Operation state flag and PS stored in PSW0 to PSW2
The result of the logical product of the inversion of the operation state flags stored in W3 to PSW5 is output. That is, as shown in FIG. 5, execution of the operation state flag control instruction on the seventh line of the program in FIG. The operation state flag logical operation circuit 8 outputs true to the instruction fetch circuit 10 only when all the operation state flags of the comparison operations in the sixth to sixth rows are false.

When the branch instruction on the eighth line of the program in FIG. 2 is set in the instruction register 11, the instruction fetch circuit 1
0 indicates that the output of the operation state flag logical operation circuit 8 is true, that is, all the operation state flags of the comparison operations executed in the first to third rows in FIG. ~ 6
Only when all the operation state flags of the comparison operation on the line are false, the address for acquiring the instruction is changed to the branch destination address label.
Change to l1.

[0038]

As described above, according to the present invention,
Since the branch judgment processing determined by a plurality of operation instructions can be realized by one (one-step) conditional branch instruction, the number of instructions required for the condition judgment processing and the instruction execution time can be reduced, and the number of instructions of the program can be reduced. Can be reduced. Further, since the number of instructions required for processing is reduced, according to the present invention, the processing time of the entire program can be reduced.

Furthermore, according to the present invention, the number of instructions to be executed is the same in both cases where the result of the condition judgment branches and when the condition judgment does not branch, so that the execution time required for the branch judgment processing becomes the same. Therefore, the program creator can create the program without being aware of the change in the execution time in the branch determination processing.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a program used in an embodiment of the present invention.

FIG. 3 is a diagram showing the meaning of machine language instructions in the program of FIG. 2;

FIG. 4 is a diagram showing a temporal change in the held content of a PSW group 5 in FIG. 1;

FIG. 5 is a flowchart of a calculation state flag of the main part of FIG. 1 when the program of FIG. 2 is executed.

FIG. 6 is a block diagram illustrating an example of a conventional information processing apparatus.

7 is an example of a program in the conventional example shown in FIG. 6;

FIG. 8 shows machine language instructions in the program of FIG. 7;

FIG. 9 is a block diagram of another example of a conventional information processing apparatus.

[Explanation of symbols]

 1, 2, 4 General-purpose register 3 Operation circuit (ALU) 5 PSW group 6 Operation state flag mask circuit 7 Operation state flag inversion circuit 8 Operation state flag logic operation circuit 9 Operation state flag control instruction execution circuit 10 Instruction fetch circuit 11 Instruction register 12 Instruction bus

Claims (6)

[Claims] 1. An instruction register for storing an instruction to be executed, an operation means for executing an operation based on an operation instruction from the instruction register and outputting an operation state flag together with an operation result, and storing the operation state flag. A plurality of registers connected in series, and a logical operation on a plurality of operation state flags from the latest one among the operation state flags sequentially stored in the plurality of registers in the order of operation by the operation means. A logic operation means for executing an operation state flag control instruction for decoding the contents of the instruction register and outputting a control signal to the logic operation means when the instruction fetched into the instruction register is an operation flag control instruction A circuit and an address for acquiring an instruction are held, and an instruction corresponding to the address is acquired from an instruction bus and output to the instruction register. Both have an instruction fetch circuit that, when the instruction acquired in the instruction register is a conditional branch instruction, refers to the output result of the logical operation means and determines the address of the instruction to be acquired next based on the truth or false. An information processing apparatus characterized by the above-mentioned. 2. The plurality of registers each transfer a storage operation state flag of each of the plurality of registers to a next-stage register each time an operation is performed by the operation unit, and
2. The information processing apparatus according to claim 1, wherein the storage operation state flag of the last stage register is discarded, and the latest operation state flag is held in the first stage register. 3. The logical operation means invalidates an operation state flag older than one designated by the operation state flag control instruction execution circuit from among the plurality of operation state flags respectively output from the plurality of registers. An inversion circuit that inverts a part of the valid operation state flags output from the mask circuit according to the specification of the operation state flag control instruction execution circuit, and outputs the remaining part in the normal direction. An operation state flag logic operation circuit for executing the operation specified by the operation state flag control instruction execution circuit on the output operation state flag of the inversion circuit, and outputting the operation result through the instruction fetch circuit. The information processing apparatus according to claim 1, wherein: 4. The operation state flag control instruction execution circuit, when the instruction fetched into the instruction register is an operation flag control instruction, sets the number of validity of the operation state flag to the mask circuit. 4. The information processing apparatus according to claim 3, wherein a number for inverting the operation state flag is output to an inversion circuit, and a type of a logical operation performed on the operation state flag is output to the operation state flag logical operation circuit. 5. The instruction fetch circuit refers to an output result of the logical operation means when an instruction stored in the instruction register is a conditional branch instruction, and only when the output is true, Change the instruction acquisition address held by itself to the branch destination address specified by the instruction register, and if the output result of the logical operation means is false, change the instruction acquisition address held by itself. 2. The information processing apparatus according to claim 1, wherein +1 is set as an address for acquiring the next instruction. 6. An instruction bus to which instruction data is sent, an instruction register for storing an instruction to be executed, a plurality of general-purpose registers for temporarily holding various data, and an instruction acquired by the instruction register is an arithmetic instruction. An operation circuit for executing an operation specified by the instruction register on the contents of the general-purpose registers and outputting an operation state flag together with the operation result; and storing a plurality of operation state flags connected in series. Each time an operation is performed by the arithmetic circuit,
Transferring the storage operation state flags of the plurality of operation state flag storage registers to the next stage operation state flag storage registers, and discarding the storage operation state flags of the final stage operation state flag storage registers; A register group for holding the latest operation state flag in a first stage operation state flag storage register, and an instruction for holding an instruction acquisition address, reading an instruction corresponding to the address from the instruction bus, and outputting the instruction to the instruction register A fetch circuit, and, if the instruction fetched into the instruction register is an operation flag control instruction, decode the contents of the instruction register and enable the operation state flag and the number of inversions of the operation state flag. An operation state flag control instruction execution circuit for outputting a type of logical operation to be performed on the operation state flag; and the plurality of operation state flags An operation state flag mask circuit for receiving the operation state flags stored in each of the storage registers as inputs and validating the number of operation state flags designated by the operation state flag control instruction execution circuit; The operation state flags output from the mask circuit are received as inputs, the number of operation state flags specified by the operation state flag control instruction execution circuit are inverted, and the operation state flags not specified are output as normal rotation. An operation state flag inverting circuit, receiving, as inputs, all operation state flags output from the operation state flag inverting circuit, and performing a logical operation indicated by the operation state flag control instruction execution circuit; An information processing apparatus, comprising: an operation state flag logical operation circuit for outputting.