JPH0876973A - Arithmetic processing unit and extended arithmetic unit - Google Patents

Abstract

PURPOSE: To attain high speed arithmetic processing by an arithmetic processing unit such as a microprocessor and a DSP even when there is much arithmetic processing volume like picture processing. CONSTITUTION: The arithmetic processing unit S can execute asynchronous processing operation based upon hand shaking and is constituted of a digital signal processor(DSP) e.g. The unit S is provided with external terminals t1a to t5a to be connected to an extended arithmetic unit P and the unit P is provided with external terminals t1b to t5b to be connected to the unit S. Both the units S, P are mutually connected so as to transfer data through the external terminals t1a to t5a and t1b to t5b. The unit P is provided with an extended arithmetic unit 17, and at the time of executing operation having much arithmetic processing volume like filter operation and matrix operation in picture processing, data are sent to the unit 17 and operation is executed by the unit 17 having high arithmetic capacity.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a microprocessor, D
The present invention relates to an arithmetic processing unit and an extended arithmetic unit that operate according to a program such as an SP (digital signal processor).

[0002]

2. Description of the Related Art As an arithmetic processing unit having an architecture for image processing, a German ITT company DSP: Da
ta-driven array processor (hereinafter referred to as DD.A.
Abbreviated as P.). Details of its architecture and operation are detailed in the following documents.

[Data-driven array processor for vide
o signal processing "Ulrich Schmidt Kunt Caesar Thomas Himmel IEEE Transaction on Consumer Electronics vol.36, n
o.3 p.327-33 1990 or same author, ICCE Digest of technical papers 1990 EPM-21.3 (p32
6-p327) Its architecture is called a data driven array processor configuration, and its features are briefly described below.

Instruction generator (program counter, instruction read, instruction decode), register file, input / output port, MAC (multiplier / accumulator), ALU (arithmetic and logic operator)
, Each of which is a pipeline processing structure. The input and output ports of the handshake operation are used for exchanging external data, but when a wait occurs for exchanging data, all pipeline processing is stopped midway. DD.AP describes this operation as a self-timed handshake.

A processor (DD.A.
P.) (expressed as cells in P.) are connected, individual programs are operated between cells, and data is transmitted and received, but by using the self-timed handshake, without being aware of the timing between cells, A program can be written.

Next, one cell portion of DD.AP is used as a conventional arithmetic processing unit, and its configuration is shown in FIG. In the figure, 1 is a program counter, 2 is an instruction read circuit,
3 is an instruction decoding circuit, 4 is a register file, 5-8
Are data buses, and here, A, B, C, D
Expressed as a bus. 9 is ALU, 10 is MAC,
11 is a multiplexer (hereinafter referred to as MUX), 1
2 and 13 are input ports having a handshake function (hereinafter referred to as handshake input ports), and 14 are MUs.
X and 15 are output ports having a handshake function (hereinafter referred to as handshake output ports).

First, the instruction generating portion including the program counter 1, the instruction reading circuit 2 and the instruction decoding circuit 3 will be described. The program counter 1 designates the address of the program to be executed and sequentially counts up from the address 0. The instruction reading circuit 2 reads the instruction corresponding to the address indicated by the program counter 1 from the RAM or the like. Further, the instruction decoding circuit 3 performs a decoding process, and the register file 4, the arithmetic units 9 and 10, the MUXs 11 and 1 are processed.
4, controlling the input / output ports 12, 13, 15 and the buses 5-8.

Next, each part controlled by the instruction decoding circuit 3 will be sequentially described. The register file 4 is composed of a plurality of registers. One of the write data is ALU9,
Alternatively, it is data on the D bus 8 to which the calculation result of the MAC 10 is output. The other is A bus 5 or B bus 6 MUX1
It is the data selected in 1. The data on the A bus 5 and the B bus 6 include output data from the register file 4, output data from the handshake input ports 12 and 13, constants directly output from the instruction reading circuit 2, and the like. On the other hand, as reading of the register file 4, A
It has two systems, bus 5 and B bus 6. As described above, the register file 4 has a 4-port structure with two input systems and two output systems.

The ALU 9 and the MAC 10 respectively input the data on the A bus 5 and the B bus 6, and selectively output the calculation result to the C bus 7 or the D bus 8. Each of the handshake input ports 12 and 13 has a system for outputting to the handshake output port 15 via the MUX 14, in addition to the output system to the A bus 5 and the B bus 6. The handshake output port 15 is the data on the C bus 7 or MUX.
Input the output data from 14. The handshake input ports 12 and 13 and the handshake output port 15 exchange data with the outside by handshake. Therefore, when any one of the handshakes falls into a waiting state, the driving clocks of all the pipelines are stopped, the entire block shown in FIG. 4 is stopped, and the handshake operation is restored.

[0010]

Generally, when image processing is performed using an arithmetic processing unit that operates according to a program such as a DSP, most of the processing is product-sum operation, and the arithmetic processing is performed. The amount of data to be done is huge. Therefore, the amount of arithmetic processing to be performed by the MAC 10 becomes very large, the arithmetic processing time becomes long, and, for example, real-time processing cannot be performed.

DS having the above conventional architecture
In P (one cell of DD.AP), there is only one MAC, and it is conceivable to increase the operation processing speed by using a high-speed system clock of several times to 10 times for high-speed operation. However, the speeding up of the clock is technically unfeasible under the present circumstances because there is a manufacturing difficulty in the process in the case of a circuit and in the case of an IC.

Further, an attempt has been actually made to increase the operation processing speed by providing a plurality of DSPs (cells) and allowing each DSP to share the operation processing for time division processing. However, the time-division processing by a plurality of DSPs inevitably increases the size of the hardware due to the increase in the DSPs, and also has a cost problem.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an arithmetic processing unit and an extended arithmetic unit capable of high-speed processing even if the amount of arithmetic processing is large, such as image processing. To do.

[0014]

According to a first aspect of the present invention, the arithmetic processing device is provided with an external terminal for connecting the extended arithmetic device.

According to a second aspect of the present invention, the extended arithmetic device is provided with an external terminal for connecting to the arithmetic processing device.
According to a third aspect of the present invention, an arithmetic instruction unit that issues a predetermined arithmetic instruction, an arithmetic unit that performs arithmetic processing on data input based on the arithmetic instruction from the arithmetic instruction unit, and outputs the arithmetic operation unit; A main operation processing device having a storage unit for storing output data output from the unit, inputs an operation command from the operation instruction unit, and converts the input data input via the main operation processing device into the input data. An extended arithmetic unit for performing arithmetic processing and outputting to the main arithmetic processing unit is externally attached.

According to another aspect of the present invention, there is provided an operation command unit for instructing a predetermined operation command, a first command bus for transmitting the operation command from the operation command unit to the outside, and the operation command unit. An arithmetic unit for performing arithmetic processing on input data input based on an arithmetic instruction from the output unit, a storage unit for storing output data output from the arithmetic unit, and for outputting the input data to the outside. An arithmetic command from a first instruction bus of the main arithmetic processing unit to a main arithmetic processing unit having a first data bus of the above and a second data bus for inputting an arithmetic result from the outside. A second instruction bus for inputting data, an input data bus for inputting input data from the first data bus, and an input data bus based on an operation instruction input via the second instruction bus. Enter Provided with an arithmetic unit for performing arithmetic processing on the input data to be output and outputting the output data output from the arithmetic unit to a second data bus of the main arithmetic processing unit. The arithmetic unit was attached externally via an external terminal.

According to a fifth aspect of the present invention, an arithmetic instruction unit for instructing a predetermined arithmetic instruction to the arithmetic processing unit, and a first instruction bus for transmitting the arithmetic instruction from the arithmetic instruction unit to the outside. An arithmetic unit for performing arithmetic processing on input data input based on an arithmetic instruction from the arithmetic instruction unit and outputting the input data; a storage unit for storing output data output from the arithmetic unit; A first data bus for outputting the data and a second data bus for inputting the operation result from the outside.

According to a sixth aspect of the invention, an instruction bus for inputting an arithmetic instruction from an external arithmetic processing unit to the extended arithmetic unit and input data for inputting input data from the external arithmetic processing unit. A bus, an arithmetic unit for performing arithmetic processing on input data input from an input data bus based on an arithmetic instruction from the instruction bus, and outputting the output data output from the arithmetic unit to the external arithmetic processing device; And an output data bus for

According to a seventh aspect of the present invention, an instruction bus for inputting an arithmetic instruction from an external arithmetic processing unit to the extended arithmetic unit, an arithmetic instruction decoding circuit connected to the instruction bus, and the external arithmetic processing. A coefficient data bus for inputting coefficient data from the device, a storage device for storing the coefficient data input via the coefficient data bus, and an input data bus for inputting input data from the external arithmetic processing device. A multiplier / adder for performing arithmetic processing on coefficient data stored in the storage device and input data input from an input data bus based on an arithmetic instruction input to an arithmetic instruction decoding circuit via the instruction bus; An output data bus for outputting the calculation result by the multiplier / adder to an external calculation processing device is provided.

According to an eighth aspect of the present invention, in the extended arithmetic unit according to the seventh aspect, the multiplication / adder can selectively execute a filter arithmetic function and a matrix arithmetic function.

[0021]

According to the first aspect of the present invention, it becomes possible to connect the extended arithmetic unit to the arithmetic processing unit via the external terminal.

According to the second aspect of the invention, the extended arithmetic unit can be connected to the arithmetic processing unit via the external terminal. According to the invention described in claim 3, the main arithmetic processing unit includes an arithmetic instruction unit, an arithmetic unit, and a storage unit,
Input data is input to the extended arithmetic unit via the main arithmetic processing unit, and the extended arithmetic unit performs arithmetic processing to be performed on the input data on behalf of the main arithmetic processing unit based on the arithmetic instruction from the arithmetic instruction unit.

According to a fourth aspect of the present invention, the main arithmetic processing unit includes an arithmetic instruction section, an arithmetic unit and a storage section,
Input data is input from the main arithmetic processing unit to the arithmetic unit in the extended arithmetic unit via the first data bus and the input data bus. The arithmetic unit performs arithmetic processing to be performed on the input data on behalf of the main arithmetic processing unit based on the arithmetic instruction input from the arithmetic instruction unit of the main arithmetic processing unit via the first and second instruction buses.

According to the invention described in claim 5, the arithmetic processing unit comprises an arithmetic instruction unit, an arithmetic unit and a storage unit, and the arithmetic instruction unit can transmit the arithmetic instruction to the outside through the first instruction bus. It becomes possible to output the input data to the outside through the first data bus, and further, it becomes possible to input the operation result from the outside through the second data bus.
Therefore, it is possible to attach the extended arithmetic device externally.

According to the invention described in claim 6, it is possible to input an arithmetic instruction from the external arithmetic processing unit via the instruction bus, and input the input data from the external arithmetic processing unit via the input data bus. It will be possible. Further, the output data of the arithmetic unit, which is obtained by performing the arithmetic processing on the input data based on the arithmetic instruction, can be output to the external arithmetic processing device through the output data bus.

According to the invention described in claim 7, it is possible to input an arithmetic instruction from the external arithmetic processing unit to the arithmetic instruction decoding circuit via the instruction bus, and from the external arithmetic processing unit via the coefficient data bus. It becomes possible to input the coefficient data of the above into the storage device. Further, it becomes possible to input the input data from the external arithmetic processing unit via the input data bus. Based on the arithmetic instruction, the multiplier / adder performs arithmetic processing on the coefficient data and the input data stored in the storage device. It is possible to output the calculation result by the multiplier / adder to the external calculation processing device via the output data bus.

According to the eighth aspect of the present invention, the filter operation function and the matrix operation function are selectively executed by the multiplication / adder provided in the extended operation device.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows the configuration of an arithmetic processing unit according to the present invention.
Since each unit 1 to 15 in FIG. 1 is the same as the configuration described in FIG. 4 in the related art, the same reference numerals are given and the description thereof is omitted, and only different points will be described.

As shown in FIG. 1, the arithmetic processing unit S including the respective units 1 to 15 is formed on one chip, and the extended arithmetic unit P is formed on a chip different from the chip. . The two chips constituting the arithmetic processing unit S and the extended arithmetic unit P are external terminals t1a, t on the same substrate.
They are arranged in a state of being connected via 1b to t5a and t5b.

In the arithmetic processing unit S, an instruction bus 16 is newly added from the instruction reading circuit 2 to the conventional configuration, and external terminals t1a to t are provided at the ends of the buses 5 to 8 and 16, respectively.
5a are provided respectively.

The extended arithmetic unit P includes an extended arithmetic unit 17
And external terminals t1a to t5a provided in the arithmetic processing unit S
There are provided external terminals t1b to t5b that can be connected to.
The external terminals t1b to t5b are connected to the buses 5 to 5 in the arithmetic processing unit S, respectively.
The buses 5a to 8a and 16a corresponding to 8 and 16 are connected.

The arithmetic processing unit S and the extended arithmetic unit P are connected by connecting the external terminals t1a to t5a and the external terminals t1b to t5b, and the data transmission between the arithmetic processing unit S and the extended arithmetic unit P. Is possible. The extended arithmetic unit 17 inputs data on the A bus 5a, B bus 6a and instruction bus 16a, and outputs the arithmetic result to the C bus 7a or D.
The data is selectively output to the bus 8a.

FIG. 2 shows the configuration of the extended arithmetic unit 17. As shown in the figure, the instruction decoding unit 18 fetches an instruction set from the instruction decoder 3 via the instruction buses 16 and 16a and performs various decoding processes. This decoding process includes "coefficient input", "A bus input", "B bus input", "tap number setting", "mode setting", "clear", "calculation execution", "C bus output", " D bus output "
9 types are set.

"Coefficient input" is the RA in the arithmetic processing unit S.
The M (not shown) is instructed to input the coefficient data stored in advance for use in the sum of products operation. "A bus input" is
It is instructed to input the coefficient data from the A bus 5a.
The "B bus input" command inputs the coefficient data from the B bus 6a. “Tap number setting” commands the reading of the number M of terms to be sum-accumulated in the sum-of-products calculation to be executed. The “mode setting” specifies whether the arithmetic processing to be executed is a filter arithmetic or a matrix arithmetic. “Clear” commands the clearing of data. "Calculation"
Command the execution of the operation. “C bus output” specifies the output of data to the C bus 7a. “D bus output” specifies data output to the D bus. The above instruction codes are output from the instruction decoding unit 18.

"Coefficient input", "A bus input", "B bus input", "tap number setting", "clear", "calculation execution"
The decoding result at is output to the RAM address counter 19. The RAM address counter 19 outputs to the RAM bank counter 20 a bank signal designating a RAM 21 to which coefficient data is to be written based on the input code, and a step signal (designating a write address of coefficient data to each RAM 21). Hereinafter, referred to as an address signal) (b) is output. The RAM bank counter 20 outputs a write signal (a) for instructing the RAM 21 designated by the bank signal to write the coefficient data on the A bus 5a or the B bus 6a. Further, the RAM address counter 19 outputs a read signal (d) to each RAM 21 based on the application of the instruction code “1” from the “execution of operation” of the instruction decoding unit 18. The RAM 21 has the maximum degree N (the number of taps for filter calculation, the number of matrix dimensions for matrix calculation)
N pieces are provided so as to correspond to the calculation of.

The mode selection circuit 22 includes an instruction decoding unit 1
From 8 to 8, an instruction code is applied as each decoding result in "mode setting" and "calculation execution".
The mode selection circuit 22 inputs the input data from the B bus 6a by applying each instruction code "1", and sets the input data to the designated operation mode, that is, according to the filter operation or the matrix operation. The data is sequentially output at the output timing.

The configuration of the mode selection circuit 22 is shown in FIG.
As shown in the figure, the mode selection circuit 22 includes (N-1) D flip-flops (hereinafter referred to as DFF) 29.
And (N-1) multiplexers (hereinafter referred to as “MUX”).
30). Operation execution instruction code from the instruction decoding unit 18 (arrow (a) in FIG. 3) "1"
Is input to each DFF 29. The input data on the B bus 6a input from the arrow (f) in FIG. 3 is output from (c) in FIG. 3 and at the beginning of the (N-1) DFFs 29 arranged in series. The data are sequentially input from the above, and are directly input to each MUX 30. The data sequentially delayed via the DFF 29 is output to each corresponding MUX 30. This delay time is set in synchronization with the reading timing of the coefficient data from each RAM 21.

Each MUX 30 outputs the data signal A shown in FIG. 3 when the mode designation code from the instruction decoding unit 18 input from the arrow (b) in FIG. 3 is "0" and the mode designation code is "1". At this time, the data signal B in the figure is selectively output to (c) to (e) in FIG.

As shown in FIG. 2, the output data from the mode selection circuit 22 is output to each of N MACs (multiply accumulators) 23. The MAC 23 performs a multiplication and accumulation operation in which coefficient data from each RAM 21 and output data from the mode selection circuit 22 are sequentially integrated and accumulated, and the operation result is a D flip-flop (hereinafter DFF).
It will be output to 24). DFF
24 are provided corresponding to each MAC 23, and each MAC is
MUX2 at the same timing as the calculation result performed in 23.
6 has the function of outputting. The output counter 25 inputs the tap number code “M” from the “tap number setting” of the instruction decoding unit 18 and the output designation codes “0” and “1” from the “C bus output” and the “D bus output”. To do. The output counter 25 outputs a designation signal for output selection to the MUX 26 when the output designation code "1" is input.

The MUX 26 outputs the input data from the DFF 24 designated based on the designation signal from the output counter 25 among the input signals from each DFF 24. MUX
The output data from 26 is input to two buffers 27 and 28 having a high impedance output function. Each of the buffers 27 and 28 outputs an output designation code “0” from “C bus output” and “D bus output” of the instruction decoding unit 18.
When "1" is input and the output designation code "1" is applied, the side connected to the designated bus is opened.

Next, the operation of the arithmetic processing device configured as described above will be described. The extended arithmetic unit P is the arithmetic processing unit S
It is used when filter calculation or matrix calculation that exceeds the calculation processing capacity on the side is required. The extended operation unit 17 operates based on the instruction sent from the instruction decoding circuit 3 via the instruction buses 16 and 16a, and the coefficient data and the image data sent via the A buses 5 and 5a or the B buses 6 and 6a. The sum-of-products operation is performed and the operation result is output to the C bus 7a or the D bus 8a.

At the stage before the execution of the arithmetic processing by the extended arithmetic unit 17, the RAM address counter 19, the RAM bank counter 20, the MAC 2 in the extended arithmetic unit 17
3 and the output counter 25 are reset in advance.

At the start of the operation of the extended arithmetic unit 17,
First, it is set whether the operation mode to be executed is filter operation or matrix operation. That is, in the case of the filter calculation, the mode selection circuit 22 in FIG.
The mode setting code "1" is applied to (b), and the mode setting code "0" is applied to (b) of the mode selection circuit 22 in the case of matrix calculation. As a result, the output timing from the mode selection circuit 22 to each MAC 23 is set according to the arithmetic mode to be executed. At the same time, the tap number M is set, and the frequency division numbers of the RAM address counter 19, the RAM bank counter 20, and the output counter 25 are set to M counts, respectively.
Initialization of each count range is performed.

Next, the coefficient data is sent from the arithmetic processing unit S to the extended arithmetic unit 17 via the A bus 5, 5a or the B bus 6, 6a. This coefficient data is written in each RAM 21 in the extended arithmetic unit 17. Prior to this writing, it is set in advance whether the bus to which the coefficient data is sent to the RAM address counter 19 is the A bus 5a or the B bus 6a. For example, if coefficient data is sent from the A bus 5a, the instruction data unit 18 applies "1" as the A bus input code and "0" as the B bus input code to the RAM address counter 19.

In this way, when the coefficient data is sent to the extended arithmetic unit 17 via the A buses 5 and 5a, the instruction decoding unit 18 outputs the RAM address counter 19 and RA.
The coefficient input code “1” is applied to the M bank counter 20. Based on this application, the output of the address signal (b) from the RAM address counter 19 to each RAM 21 is started, and the RAM bank counter 20 outputs each RAM 2
The write signal (a) is output to the RAM 21 to be written out of the ones.

First, a case where the operation executed by the extended operation unit 17 is a filter operation will be described as an example. In the case of filter calculation, the same coefficient data is written in each RAM 21. A write signal (a) is simultaneously output from the RAM bank counter 20 to each RAM 21 in which coefficient data should be written, and the coefficient data input from the A bus 5 is simultaneously and concurrently written in each RAM 21. In addition to this writing method, for example, the write signal (a) is sequentially output to each RAM 21 to output the same coefficient data to each RAM 21.
It is also possible to adopt a method of sequentially writing in 21. Coefficient data (a ₀ , a ₀ ,
a ₁ , a ₂ , ..., A _M ) are respectively written.

When the writing of the coefficient data to each RAM 21 is completed in this way, the image data (x ₀ , x ₁ , x ₂ , ..., X _M ) to be filtered next is sent via the B bus 6a. . At this time, “1” is previously stored as the operation execution code from the instruction decoding unit 18 in the RAM address counter 1
9 and the mode selection circuit 22. Based on this application, a read signal (d) is output from the RAM address counter 19 to each RAM 21, and based on this read signal (d), the coefficient data is written from each RAM 21 in the same order and in parallel at the same time. Output to each MAC 23.

On the other hand, in the mode selection circuit 22, each DFF 29 operates based on the applied operation execution code "1". As shown in Fig. 3, the data input from (f) is M
Directly input to UX30 (input data A),
The data is sequentially delayed via each DFF 29 and input to each MUX 30 (input data B). Since the mode setting code “1” is applied to each MUX 30 from (b), the data B input via each DFF 29 among the two input data A and B is selectively output. Thus, the mode selection circuit 2
Data that is not delayed is output from (c) from 2
From (d) to (e), delayed data is sequentially output in synchronization with the read interval from each RAM 21. as a result,
Each MAC 23 reads coefficient data (each R in the filter calculation) read from the corresponding RAM 21 at a predetermined read interval.
The coefficient data from AM is the same data value) and the data delayed in synchronization with the reading interval are sequentially input via the mode selection circuit 22, and the products thereof are sequentially accumulated M times. The product-sum operation result is output from each MAC 23,
It is latched by each DFF 24.

The operation result latched by the DFF 24 is MU.
The data is selected in X26 in the data order (the output order from the top of each DFF 24 in FIG. 2) and output from the MUX 26 via the buffers 27 and 28 to either the C bus 7a or the D bus 8a. The selection control of the MUX 26 follows the output counter 25, and the progress of this counter is a signal obtained by decoding the operation result reading instruction of the extended operation unit 17 transferred via the instruction bus 16a (“C in the instruction decoding unit 18”).
Bus output ”,“ D bus output ”). The number of calculation results read out is determined every M based on the count number of the output counter 25.

Then, the extended arithmetic unit 17
The case in which the queue operation is executed will be described. For example, A bus 5
coefficient data (a_Ten, A₁₁, A₁₂,…,
a_1M), (A₂₀, A_{twenty one}, A_{twenty two}, ..., a_2M), (A₃₀, A
₃₁, A₃₂, ..., a_3M), ..., (a _M0, A_M1, A_M2,
…, A_MM) Is sent, the coefficient data for each R
Sequentially written in AM21. Coefficient data to each RAM21
Data writing is done by address signal (b) and write signal
It is carried out based on (a). First in one RAM21
M coefficient data (a_Ten, A₁₁, A₁₂, ..., a_1M) Is written
Once loaded, the RAM 21 of the next bank will receive the next M entries.
Numerical data (a₂₀, A_{twenty one}, A_{twenty two}, ..., a_2M) Is written
It All of the coefficient data sent in this way is stored in each RAM.
21 (signal (c) in the figure). Like this
When performing a trix operation, each RAM 21 has a different function.
Numerical data is stored. In this way, the coefficient data is stored in each RAM 21.
Data (a_Ten, A ₁₁, A₁₂, ..., a_1M), (A₂₀, A_{twenty one},
a_{twenty two}, ..., a_2M), (A₃₀, A₃₁, A₃₂, ..., a_3M),
…, (A_M0, A_M1, A_M2, ..., a_MM) Each write
Get caught.

Next, the image data (x
₀ , x ₁ , x ₂ , ..., X _M ) are sent via the B bus 6a. This image data (x ₀ , x ₁ , x ₂ , ..., x
_M ) is sequentially input to the mode selection circuit 22, and sequentially output from the mode selection circuit 22 to each MAC 23 in parallel at the same time. At this time, in the mode selection circuit 22, as shown in FIG. 3, the MUX 30 stores the image data A that is not delayed,
The delayed data B is input through the DFF 29, and the undelayed data A is selectively output.

Further, each RAM corresponding to each MAC 23
The coefficient data sequentially read at a predetermined read interval from 21 is input. As a result, in each MAC 23, each coefficient data (a ₁₀ , a ₁₁ , a ₁₂ , ..., A _1M ), (a ₂₀ ,
_{a 21, a 22, ...,} a 2M), (a 30, a 31, a 32, ..., a
_3M ), ..., (a _M0 , a _M1 , a _M2 , ..., a _MM ) and the image data (x ₀ , x ₁ , x ₂ , ..., X _M ) are summed. Calculation result data (a ₁₀ · x ₀ + a ₁₁ · x ₁ + a ₁₂ · x ₂ + ... + a _1M from each MAC 23
.X _M ), ..., (a _{M0.x 0} + a _{M1.x 1} + a _{M2.x 2}
+ ... + a _MM · x _M ) is output respectively. This M
The individual calculation result data are latched by each DFF 24 and selectively output from the MUX 26 in the order corresponding to the original image data (x ₀ , x ₁ , x ₂ , ..., X _M ). The operation result data output from the MUX 26 is output to the specified C bus 7a or D bus 8a via the buffers 27 and 28 and transferred to the operation processing device S side.

As described above in detail, according to this embodiment, the arithmetic processing unit S is provided with the external terminals t1a to t5a for connecting to the extended arithmetic unit P and the extended arithmetic unit P is connected to the arithmetic unit S. Since the external terminals t1b to t5b are provided for this purpose, the extended arithmetic unit P can be connected as necessary. Therefore, for example, even when the arithmetic processing device S is used for image processing with a large amount of arithmetic processing, the extended arithmetic device P
It becomes unnecessary to adopt a configuration in which a plurality of arithmetic processing devices S are provided in order to secure the arithmetic processing capacity by connecting the. That is, it is possible to add only insufficient computing units as needed.

As a result, even in the data waiting state, it is possible to prevent the driving of the arithmetic processing unit S from being stopped until the entire arithmetic processing unit S is restored, so that the arithmetic processing can be performed at high speed. Moreover, since it is not necessary to add a chip such as a DSP or LSI having a brain to supplement the arithmetic processing capability,
The chip occupies a small area and the cost is low.

In addition, the number N of RAs corresponding to the maximum degree N of calculation is set in the expanded arithmetic unit 17 which constitutes the expanded arithmetic unit P.
Since the M21 and the MAC 23 are provided and the respective product-sum operations are executed in parallel substantially in parallel, the filter operation or the matrix operation is executed at the processing speed of <result output of 1 sample / 1 instruction step> regardless of the order. be able to. Therefore, in image processing, even if a large amount of calculation processing such as filter calculation or matrix calculation is processed, high-speed processing can be realized.

The present invention is not limited to the above-mentioned embodiments, and the structure can be modified as follows, for example, without departing from the gist of the invention. (1) The calculation performed by the extended calculation device P may be a product-sum calculation other than the filter calculation and the matrix calculation. Furthermore, an arithmetic process other than the sum of products operation may be executed.

(2) Two or more extended arithmetic units P may be connected to one arithmetic processing unit S. The invention grasped from the above-mentioned embodiment and not described in the scope of claims is described below together with its effect.

(A) D which operates asynchronously by handshake
The expansion computing unit was equipped with an external terminal for connecting to the SP.
It is possible to asynchronously operate the arithmetic processing unit in which the extended arithmetic unit and the DSP are connected.

[0059]

As described above in detail, according to the invention described in claim 1, the extended arithmetic unit can be connected to the arithmetic processing unit through the external terminal.

According to the second aspect of the invention, the extended arithmetic unit can be connected to the arithmetic processing unit via the external terminal. According to the third and fourth aspects of the invention, it is possible to cause the extended arithmetic unit to perform arithmetic processing in place of the main arithmetic processing unit.

According to the fifth aspect of the present invention, it is possible to output the operation command and the input data to the outside, and the operation result can be input. Therefore, it is possible to attach the extended operation device to the operation processing device. You can

According to the sixth and seventh aspects of the invention, the extended arithmetic unit can be connected to the external arithmetic processing unit. According to the invention described in claim 8, it is possible to cause the multiplier / adder provided in the expansion arithmetic unit to selectively execute the filter arithmetic function and the matrix arithmetic function.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an arithmetic processing unit according to an embodiment of the present invention.

FIG. 2 is a block circuit diagram of an extended arithmetic unit.

FIG. 3 is a block circuit diagram of a mode selection circuit.

FIG. 4 is a block circuit diagram of a conventional arithmetic processing unit.

[Explanation of symbols]

2 ... Instruction read circuit forming operation instruction unit 3 ... Instruction decode circuit forming operation instruction unit 4 ... Register file as storage unit 5, 6 ... Data bus as first data bus 5a, 6a ... Input data bus And data bus 7, 8 as coefficient data bus ... Data bus 7a, 8a as second data bus ... Data bus as output data bus 9 ... ALU 10 constituting arithmetic unit ... MAC 16 constituting arithmetic unit ... An instruction bus 16a as a first instruction bus ... An instruction bus as a second instruction bus 17 ... An extended arithmetic unit 18 as an arithmetic unit while constituting an extended arithmetic unit ... An arithmetic decoding unit 21 as an arithmetic instruction decoding circuit 21 ... RAM 23 as a storage device ... MAC t1a to t5a as a power adder ... External terminals t1b to t5b ... External end S ... processor P ... extended arithmetic unit as a main processor and an external processing unit

Claims (8)

[Claims] 1. An arithmetic processing device comprising an external terminal for connecting an extended arithmetic device. 2. An extended arithmetic unit having an external terminal for connecting to an arithmetic processing unit. 3. An operation command unit for instructing a predetermined operation command, and an operation unit for performing operation processing on data input based on the operation command from the operation instruction unit and outputting the data.
An input that inputs a calculation command from the calculation command unit to a main calculation processing device that includes a storage unit that stores output data that is output from the calculation unit, and that is input through the main calculation processing device. An arithmetic processing device externally provided with an extended arithmetic device for performing arithmetic processing on data and outputting the data to the main arithmetic processing device. 4. An operation instruction unit for instructing a predetermined operation instruction, a first instruction bus for transmitting an operation instruction from the operation instruction unit to the outside, and an operation instruction from the operation instruction unit. An arithmetic unit for performing arithmetic processing on input input data and outputting the input data, a storage unit for storing output data output from the arithmetic unit, and a first data bus for outputting the input data to the outside. A second instruction for inputting an arithmetic instruction from a first instruction bus of the main arithmetic processing unit to a main arithmetic processing unit having a second data bus for inputting an arithmetic result from the outside A bus, an input data bus for inputting input data from the first data bus, and an input data input via the input data bus based on an operation instruction input via the second instruction bus. An extended arithmetic unit including an arithmetic unit for performing arithmetic processing and outputting the output data output from the arithmetic unit to a second data bus of the main arithmetic processing unit is provided as an external terminal. An arithmetic processing unit externally attached via. 5. An operation instruction unit for instructing a predetermined operation instruction, a first instruction bus for transmitting an operation instruction from the operation instruction unit to the outside, and an operation instruction from the operation instruction unit. An arithmetic unit that performs arithmetic processing on input input data and outputs the input data, a storage unit that stores output data output from the arithmetic unit, and a first data bus for outputting the input data to the outside. And a second data bus for inputting a calculation result from the outside. 6. An instruction bus for inputting an arithmetic instruction from an external arithmetic processing unit, an input data bus for inputting input data from the external arithmetic processing unit, and an arithmetic instruction from the instruction bus. Extended operation provided with an arithmetic unit that performs arithmetic processing on input data input from an input data bus and outputs the output data, and an output data bus for outputting output data output from the arithmetic unit to the external arithmetic processing device. apparatus. 7. An instruction bus for inputting an arithmetic instruction from an external arithmetic processing device, an arithmetic instruction decoding circuit connected to the instruction bus, and a coefficient data bus for inputting coefficient data from the external arithmetic processing device. A storage device for storing coefficient data input via the coefficient data bus; an input data bus for inputting input data from the external operation processing device; and an operation instruction decode circuit via the instruction bus. A multiplication / adder for performing an arithmetic operation on the coefficient data stored in the storage device and the input data input from the input data bus based on the input arithmetic instruction, and the arithmetic result by the multiplication / adder to an external arithmetic processing device. An extended arithmetic unit having an output data bus for outputting. 8. The extended arithmetic unit according to claim 7, wherein the multiplier-adder can selectively execute a filter arithmetic function and a matrix arithmetic function.