JP3454776B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3454776B2 JP3454776B2 JP2000125379A JP2000125379A JP3454776B2 JP 3454776 B2 JP3454776 B2 JP 3454776B2 JP 2000125379 A JP2000125379 A JP 2000125379A JP 2000125379 A JP2000125379 A JP 2000125379A JP 3454776 B2 JP3454776 B2 JP 3454776B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductivity type
- forming
- film
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000012535 impurity Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims 1
- 230000000873 masking effect Effects 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 40
- 230000015556 catabolic process Effects 0.000 description 14
- -1 phosphorus ions Chemical class 0.000 description 9
- 239000000758 substrate Substances 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置とその
製造方法に関し、更に言えば、高耐圧ＭＯＳトランジス
タの耐圧を損なうことなく、低オン抵抗化を図る技術に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique for achieving a low on-resistance without impairing the breakdown voltage of a high breakdown voltage MOS transistor.
【０００２】[0002]
【従来の技術】以下、従来の半導体装置について図面を
参照しながら説明する。2. Description of the Related Art A conventional semiconductor device will be described below with reference to the drawings.
【０００３】図８において、５１は例えばＰ型の半導体
基板で、５２はＮ型ウエル領域で、このＮ型ウエル領域
５２内にＬＰ層５３（ドリフト領域を構成する。）が形
成されている。５４Ａ，５４ＢはＬＯＣＯＳ法により形
成された選択酸化膜（ゲート酸化膜を構成する。）及び
ＬＯＣＯＳ酸化膜（素子分離膜を構成する。）である。In FIG. 8, 51 is a P-type semiconductor substrate, 52 is an N-type well region, and an LP layer 53 (forming a drift region) is formed in the N-type well region 52. 54A and 54B are a selective oxide film (which constitutes a gate oxide film) and a LOCOS oxide film (which constitutes an element isolation film) formed by the LOCOS method.
【０００４】５５はゲート酸化膜で、５６は前記ゲート
酸化膜５５から選択酸化膜５４Ａ上にまたがるように形
成されたゲート電極で、５７，５８は前記ゲート電極５
６に隣接するように形成されたＰ型のソース領域及びゲ
ート電極５６と離間された位置に形成されたＰ型のドレ
イン領域である。Reference numeral 55 is a gate oxide film, 56 is a gate electrode formed so as to extend from the gate oxide film 55 onto the selective oxide film 54A, and 57 and 58 are the gate electrodes 5.
6 is a P- type source region formed adjacent to 6 and a P- type drain region formed at a position separated from the gate electrode 56.
【０００５】上記した従来の半導体装置は、図８に示す
ように高耐圧化を図るために、前記ドレイン領域５８を
取り囲むように深く拡散したドリフト領域（ＬＰ層５
３）を有したＬＤＤ構造を採用していた。In the conventional semiconductor device described above, a drift region (LP layer 5) which is deeply diffused so as to surround the drain region 58 in order to increase the breakdown voltage as shown in FIG.
The LDD structure having 3) was adopted.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記ド
リフト領域（ＬＰ層５３）の濃度とソース・ドレイン間
耐圧（ＢＶＤＳ）には、図９に示す相関関係があり、従
って、このドリフト領域（ＬＰ層５３）の濃度には上限
値が存在し、それ以上はドリフト領域（ＬＰ層５３）の
抵抗値を下げられなかった。However, there is a correlation shown in FIG. 9 between the concentration of the drift region (LP layer 53) and the source-drain breakdown voltage (BVDS). the concentration of the 53) there is an upper limit value, more were Tsu or a lowered resistance value of the drift region (LP layer 53).
【０００７】[0007]
【課題を解決するための手段】そこで、上記課題に鑑み
本発明の半導体装置（高耐圧ＭＯＳトランジスタ）は、
第１導電型の半導体層上に形成された第１のゲート酸化
膜から第２のゲート酸化膜上にまたがるように形成され
たゲート電極と、このゲート電極に隣接するように形成
された第２導電型のソース領域と、前記ゲート電極と離
間された位置に形成された第２導電型のドレイン領域
と、このドレイン領域を取り囲むように形成された第２
導電型のドリフト領域とを有し、当該ドリフト領域内に
より高濃度な第２導電型不純物層を形成することで、ド
リフト領域の抵抗値を低下させることを特徴とする。In view of the above problems, the semiconductor device (high voltage MOS transistor) of the present invention is
A gate electrode formed so as to extend from the first gate oxide film formed on the semiconductor layer of the first conductivity type to the second gate oxide film, and a second electrode formed so as to be adjacent to the gate electrode. A conductive type source region, a second conductive type drain region formed at a position separated from the gate electrode, and a second drain region formed so as to surround the drain region.
And a drift region of a conductive type, and by forming a higher concentration second conductivity type impurity layer in the drift region, the resistance value of the drift region is reduced.
【０００８】また、前記第２導電型不純物層は、少なく
とも前記ドレイン領域の一端部から前記ゲート電極の一
端部に隣接するように形成されていることを特徴とす
る。The second conductivity type impurity layer is formed so as to adjoin at least one end of the drain region to one end of the gate electrode.
【０００９】更に、上記半導体装置の製造方法は、第１
導電型の半導体層内に第２導電型不純物をイオン注入し
拡散させることで第２導電型層を形成する。そして、前
記半導体層上の所定領域に耐酸化性膜を形成し、更に、
前記耐酸化性膜を含む前記半導体層上の所定領域にレジ
スト膜を形成する。続いて、前記耐酸化性膜及び前記レ
ジスト膜をマスクに第２導電型不純物をイオン注入して
前記半導体層上の所定領域にイオン注入層を形成し、前
記レジスト膜を除去した後に前記耐酸化性膜をマスクに
半導体層をＬＯＣＯＳ酸化して選択酸化膜を形成すると
共に前記イオン注入層を拡散させて第２導電型不純物層
を形成する。次に、前記選択酸化膜をマスクに前記半導
体層上を熱酸化してゲート酸化膜を形成し、前記ゲート
酸化膜から選択酸化膜上にまたがるようにゲート電極を
形成する。そして、前記ゲート電極及びに前記選択酸化
膜をマスクに第２導電型不純物をイオン注入して前記ゲ
ート電極に隣接するように第２導電型のソース領域を形
成すると共に、前記ゲート電極と離間された位置に第２
導電型のドレイン領域を形成する工程とを有することを
特徴とする。Further, the first method of manufacturing the semiconductor device is
A second conductivity type layer is formed by ion-implanting and diffusing a second conductivity type impurity into the conductivity type semiconductor layer. Then, an oxidation resistant film is formed in a predetermined region on the semiconductor layer, and further,
A resist film is formed on a predetermined region of the semiconductor layer including the oxidation resistant film. Then, using the oxidation resistant film and the resist film as a mask, second conductivity type impurities are ion-implanted to form an ion-implanted layer in a predetermined region on the semiconductor layer, and after removing the resist film, the oxidation-resistant film is formed. The semiconductor layer is LOCOS-oxidized using the conductive film as a mask to form a selective oxide film, and the ion-implanted layer is diffused to form a second conductivity type impurity layer. Next, the semiconductor layer is thermally oxidized using the selective oxide film as a mask to form a gate oxide film, and a gate electrode is formed so as to extend from the gate oxide film onto the selective oxide film. Then, second-conductivity-type impurities are ion-implanted into the gate electrode and the selective oxide film as a mask to form a second-conductivity-type source region adjacent to the gate electrode, and the source region is separated from the gate electrode. Second position
And a step of forming a conductivity type drain region.
【００１０】また、前記第２導電型不純物層は、通常耐
圧のＭＯＳトランジスタの素子分離膜下に形成するチャ
ネルストッパ層形成工程を転用することで、同一工程で
形成されていることを特徴とする。Further, the second conductivity type impurity layer is formed in the same step by diverting the step of forming a channel stopper layer formed under the element isolation film of a MOS transistor having a normal breakdown voltage. .
【００１１】[0011]
【発明の実施の形態】以下、本発明の半導体装置とその
製造方法に係る一実施形態について図面を参照しながら
説明する。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.
【００１２】図１乃至図７は、本発明の高耐圧ＭＯＳト
ランジスタの製造方法を各工程順に示した断面図であ
り、一例としてＰチャネル型の高耐圧ＭＯＳトランジス
タ構造について図示してある。尚、Ｎチャネル型の高耐
圧ＭＯＳトランジスタ構造についての説明は省略する
が、導電型が異なるだけで、同様な構造となっているの
は周知の通りである。1 to 7 are cross-sectional views showing a method of manufacturing a high breakdown voltage MOS transistor according to the present invention in the order of steps, showing a P-channel type high breakdown voltage MOS transistor structure as an example. Although the description of the N-channel type high breakdown voltage MOS transistor structure is omitted, it is well known that the structure is the same except that the conductivity types are different.
【００１３】先ず、図１において、例えばＰ型半導体基
板１の所望領域にＮ型不純物をイオン注入し、拡散させ
ることでＮ型ウエル領域２が形成されている。尚、本工
程では、Ｎ型不純物として、例えばリンイオンをおよそ
１６０ＫｅＶの加速電圧で、５×１０12／ｃｍ2の注入
条件で行い、このリンイオンをおよそ１２００℃、１６
時間で熱拡散させている。First, in FIG. 1, an N-type well region 2 is formed by ion-implanting and diffusing N-type impurities into a desired region of a P-type semiconductor substrate 1, for example. In this step, phosphorus ions, for example, are used as N-type impurities at an accelerating voltage of approximately 160 KeV and under an implantation condition of 5 × 10 12 / cm 2 , and the phosphorus ions are approximately 1200 ° C. and 16
Heat is diffused in time.
【００１４】続いて、前記基板１上に形成したレジスト
膜３をマスクに前記基板１の所望領域にＰ型不純物をイ
オン注入してイオン注入層４Ａを形成する。そして、図
２に示すように前記イオン注入した不純物を拡散させる
ことで、低濃度のＰ型層４（以下、ＬＰ層４と称す。）
を形成する。ここで、前記ＬＰ層４はドリフト領域を構
成することになる。尚、本工程では、Ｐ型不純物とし
て、例えばボロンイオンをおよそ８０ＫｅＶの加速電圧
で、１．２×１０13／ｃｍ2の注入条件で行い、このボ
ロンイオンをおよそ１１００℃、４時間で熱拡散させて
いる。Then, using the resist film 3 formed on the substrate 1 as a mask, P-type impurities are ion-implanted into a desired region of the substrate 1 to form an ion-implanted layer 4A. Then, as shown in FIG. 2, by diffusing the ion-implanted impurities, the low-concentration P-type layer 4 (hereinafter referred to as the LP layer 4).
To form. Here, the LP layer 4 constitutes a drift region. In this step, as a P-type impurity, for example, boron ions are implanted at an accelerating voltage of about 80 KeV and an implantation condition of 1.2 × 10 13 / cm 2 , and the boron ions are thermally diffused at about 1100 ° C. for 4 hours. I am letting you.
【００１５】次に、図３において、前記基板１の所定領
域上にシリコン窒化（ＳｉＮ）膜５及びレジスト膜６を
それぞれパターニング形成する。Next, in FIG. 3, a silicon nitride (SiN) film 5 and a resist film 6 are patterned and formed on predetermined regions of the substrate 1.
【００１６】更に、前記シリコン窒化膜５及びレジスト
膜６をマスクにＰ型不純物をイオン注入してイオン注入
層７を形成する。そして、図５に示すように前記レジス
ト膜６を除去した後に、前記シリコン窒化膜５をマスク
に基板表面をＬＯＣＯＳ酸化して、およそ８００ｎｍ程
度の膜厚の選択酸化膜８Ａ（ゲート酸化膜を構成す
る。）及びＬＯＣＯＳ酸化膜８Ｂ（素子分離膜を構成す
る。）を形成する。このＬＯＣＯＳ酸化処理時に、前記
イオン注入層７内のボロンイオンが拡散されて、ドリフ
ト領域（ＬＰ層４）内にＦＰ層７Ａが形成され、素子分
離膜（ＬＯＣＯＳ酸化膜８Ｂ）下に不図示のチャネルス
トッパ層が形成される。即ち、当該ＦＰ層７Ａは、通常
耐圧（例えば、５Ｖ）のＮチャネル型ＭＯＳトランジス
タ（図示省略）の素子分離膜下に形成するチャネルスト
ッパ層の形成工程を転用しているため、ＦＰ層７Ａの形
成用に新たに製造工程数が増大するといったことはな
い。尚、本工程では、Ｐ型不純物として、例えばボロン
イオンをおよそ８０ＫｅＶの加速電圧で、１．２×１０
１３／ｃｍ２の注入条件で行い、ＬＯＣＯＳ酸化時の熱
処理（およそ１０００℃）で当該ボロンイオンを熱拡散
させている。Further, P-type impurities are ion-implanted using the silicon nitride film 5 and the resist film 6 as a mask to form an ion-implanted layer 7. Then, as shown in FIG. 5, after removing the resist film 6, the substrate surface is LOCOS-oxidized by using the silicon nitride film 5 as a mask to form a selective oxide film 8A (gate oxide film having a thickness of about 800 nm). And a LOCOS oxide film 8B (which constitutes an element isolation film). During this LOCOS oxidation process, boron ions in the ion-implanted layer 7 are diffused to form the FP layer 7A in the drift region (LP layer 4), and the FP layer 7A is formed under the element isolation film (LOCOS oxide film 8B) ( not shown ). Channels
A topper layer is formed. That is, since the FP layer 7A is diverted from the step of forming the channel stopper layer formed under the element isolation film of an N-channel type MOS transistor (not shown) having a normal breakdown voltage (for example, 5V), the FP layer 7A is formed. There is no increase in the number of manufacturing steps for forming. In this step, for example, boron ions are used as the P-type impurities at an acceleration voltage of about 80 KeV and 1.2 × 10.
The boron ions are thermally diffused by heat treatment (about 1000 ° C.) during LOCOS oxidation under the implantation conditions of 13 / cm 2 .
【００１７】続いて、図６において、前記基板１上を熱
酸化して前記選択酸化膜８Ａ及び前記ＬＯＣＯＳ酸化膜
８Ｂ以外の領域におよそ４５ｎｍ程度の膜厚のゲート酸
化膜９を形成し、このゲート酸化膜９から選択酸化膜８
Ａ上にまたがるようにゲート電極１０をおよそ４００ｎ
ｍ程度の膜厚で形成する。尚、本実施形態のゲート電極
１０は、ＰＯＣｌ3を熱拡散源にしてリンドープし導電
化を図ったポリシリコン膜から構成されている。更に言
えば、このポリシリコン膜の上にタングステンシリサイ
ド（ＷＳｉｘ）膜等が積層されて成るポリサイド電極と
しても良い。Then, in FIG. 6, the substrate 1 is thermally oxidized to form a gate oxide film 9 having a thickness of about 45 nm in a region other than the selective oxide film 8A and the LOCOS oxide film 8B. Gate oxide film 9 to selective oxide film 8
Approximately 400n of the gate electrode 10 so as to extend over A
It is formed with a film thickness of about m. The gate electrode 10 of this embodiment is made of a polysilicon film which is made conductive by being phosphorus-doped using POCl 3 as a thermal diffusion source. Moreover, a polycide electrode may be formed by stacking a tungsten silicide (WSix) film or the like on the polysilicon film.
【００１８】続いて、図７において、前記ゲート電極１
０，前記選択酸化膜８Ａ及び前記ＬＯＣＯＳ酸化膜８Ｂ
をマスクにＰ型不純物を注入してＰ型拡散領域１１（以
下、ソース領域１１と称す。）及びＰ型拡散領域１２
（以下、ドレイン領域１２と称す。）を形成する。尚、
本工程では、例えばボロンイオンをおよそ３５ＫｅＶの
加速電圧で、１×１０15／ｃｍ2の注入量で注入し、更
に、例えばニフッ化ボロンイオンをおよそ８０ＫｅＶの
加速電圧で、２×１０15／ｃｍ2の注入量で注入するこ
とで、いわゆるＤＤＤ構造のソース・ドレイン領域を形
成している。更に言えば、前記ソース・ドレイン領域１
１，１２は、上記ＤＤＤ構造に限定されるものではな
く、いわゆるＬＤＤ構造であっても構わない。Next, referring to FIG. 7, the gate electrode 1
0, the selective oxide film 8A and the LOCOS oxide film 8B
Is used as a mask to implant a P-type impurity into the P-type diffusion region 11 (hereinafter referred to as the source region 11) and the P-type diffusion region 12.
(Hereinafter, referred to as the drain region 12) is formed. still,
In this step, for example, boron ions are implanted with an accelerating voltage of about 35 KeV and an implantation amount of 1 × 10 15 / cm 2 , and further, for example, boron difluoride ions are implanted with an accelerating voltage of about 80 KeV of 2 × 10 15 / cm 2. The source / drain region having a so-called DDD structure is formed by implanting the implanted amount of 2 . Furthermore, the source / drain region 1
The elements 1 and 12 are not limited to the above DDD structure, and may have a so-called LDD structure.
【００１９】以下、図示した説明は省略するが、基板全
面に層間絶縁膜を形成し、当該層間絶縁膜を介してソー
ス電極、ドレイン電極を形成した後に、不図示のパッシ
ベーション膜を形成して半導体装置を完成させる。Although not shown in the drawings, an interlayer insulating film is formed on the entire surface of the substrate, a source electrode and a drain electrode are formed through the interlayer insulating film, and then a passivation film (not shown) is formed to form a semiconductor. Complete the device.
【００２０】以上説明したように、本発明ではゲート電
極１０下のチャネル領域１３近傍から前記ドレイン領域
１２を取り囲むように形成されるドリフト領域（ＬＰ層
４）のある領域内に、より高濃度の不純物層（ＦＰ層７
Ａ）を形成することで、耐圧劣化を生じさせることな
く、当該ドリフト領域の抵抗値を下げられる。従って、
高耐圧ＭＯＳトランジスタのオン抵抗を減少させること
ができる。As described above, according to the present invention, a higher concentration is provided in the region including the drift region (LP layer 4) formed so as to surround the drain region 12 from the vicinity of the channel region 13 below the gate electrode 10. Impurity layer (FP layer 7
By forming A), the resistance value of the drift region can be reduced without causing breakdown voltage deterioration. Therefore,
The ON resistance of the high voltage MOS transistor can be reduced.
【００２１】更に言えば、上述したように低オン抵抗化
が可能になるため、当該高耐圧ＭＯＳトランジスタのゲ
ート幅（ＧＷ）サイズを小さくでき、トランジスタの占
有面積の縮小化を可能にすることができる。Furthermore, since it is possible to reduce the on-resistance as described above, the gate width (GW) size of the high breakdown voltage MOS transistor can be reduced, and the area occupied by the transistor can be reduced. it can.
【００２２】また、本発明では、前記ＦＰ層７Ａの形成
工程が、通常耐圧のＭＯＳトランジスタ（例えば、５Ｖ
のＮチャネル型ＭＯＳトランジスタ）の素子分離膜下に
形成するチャネルストッパ層形成工程を転用し、同一工
程で形成されるために製造工程数が増大することはな
い。Further, in the present invention, the step of forming the FP layer 7A is performed by using a MOS transistor having a normal breakdown voltage (for example, 5V).
The N-channel type MOS transistor) is formed in the same step by diverting the step of forming the channel stopper layer under the element isolation film, so that the number of manufacturing steps does not increase.
【００２３】[0023]
【発明の効果】本発明によれば、ドレイン領域を取り囲
むように形成されるドリフト領域内のある領域に、より
高濃度の不純物層を形成することで、耐圧劣化を生じさ
せることなく、当該ドリフト領域の抵抗値を下げること
ができ、低オン抵抗化が可能になる。According to the present invention, a higher concentration impurity layer is formed in a certain region within the drift region formed so as to surround the drain region, so that the drift can be prevented without causing breakdown voltage deterioration. The resistance value of the region can be reduced, and the low on-resistance can be achieved.
【００２４】また、上述したように低オン抵抗化が可能
になるため、トランジスタのゲート幅（ＧＷ）サイズを
小さくでき、当該トランジスタの占有面積の縮小化が図
れる。Further, as described above, the on-resistance can be reduced, so that the gate width (GW) size of the transistor can be reduced and the area occupied by the transistor can be reduced.
【００２５】更に、本発明ではドリフト領域内に形成さ
れる高濃度の不純物層の形成工程を、通常耐圧のトラン
ジスタの素子分離膜下に形成するチャネルストッパ層形
成工程を転用しているため、製造工程数が増大するとい
う問題は発生しない。Further, in the present invention, the process of forming the high-concentration impurity layer formed in the drift region is diverted from the process of forming the channel stopper layer formed under the element isolation film of the transistor having the normal breakdown voltage. The problem of increasing the number of steps does not occur.
【図１】本発明の一実施形態の半導体装置の製造方法を
示す断面図である。FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施形態の半導体装置の製造方法を
示す断面図である。FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device of the embodiment of the present invention.
【図３】本発明の一実施形態の半導体装置の製造方法を
示す断面図である。FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device of the embodiment of the present invention.
【図４】本発明の一実施形態の半導体装置の製造方法を
示す断面図である。FIG. 4 is a cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.
【図５】本発明の一実施形態の半導体装置の製造方法を
示す断面図である。FIG. 5 is a cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.
【図６】本発明の一実施形態の半導体装置の製造方法を
示す断面図である。FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.
【図７】本発明の一実施形態の半導体装置の製造方法を
示す断面図である。FIG. 7 is a cross-sectional view showing the method for manufacturing the semiconductor device of the embodiment of the present invention.
【図８】従来の半導体装置を示す断面図である。FIG. 8 is a sectional view showing a conventional semiconductor device.
【図９】従来技術の課題を説明するための図である。FIG. 9 is a diagram for explaining a problem of the conventional technique.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平６−120497（ＪＰ，Ａ) 特開 昭60−198780（ＪＰ，Ａ) 特開 平７−283409（ＪＰ，Ａ) 特開 平５−343675（ＪＰ，Ａ) 特表 平10−506755（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-6-120497 (JP, A) JP-A-60-198780 (JP, A) JP-A-7-283409 (JP, A) JP-A-5- 343675 (JP, A) Special table 10-506755 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 29/78
Claims (3)
１のゲート酸化膜から第２のゲート酸化膜上にまたがる
ように形成されたゲート電極と、このゲート電極に隣接
するように形成された第２導電型のソース領域と、前記
ゲート電極と離間された位置に形成された第２導電型の
ドレイン領域と、このドレイン領域を取り囲むように形
成された第２導電型のドリフト領域とを有する半導体装
置において、 前記ドレイン領域に隣接するように第２導電型不純物層
が形成されており、前記第２導電型不純物層は、少なく
とも前記ドレイン領域の一端部から前記ゲート電極の一
端部に隣接するように形成されていることを特徴とする
半導体装置。 1. A gate electrode formed to extend from a first gate oxide film formed on a semiconductor layer of the first conductivity type to a second gate oxide film, and adjacent to the gate electrode. The formed second conductivity type source region, the second conductivity type drain region formed at a position separated from the gate electrode, and the second conductivity type drift region formed so as to surround the drain region. A second conductivity type impurity layer is formed so as to be adjacent to the drain region, and the second conductivity type impurity layer is
Both ends of the gate electrode from one end of the drain region.
Characterized by being formed so as to be adjacent to the end portion
Semiconductor device.
純物をイオン注入し拡散させることで第２導電型層を形
成する工程と、 前記半導体層上の所定領域に耐酸化性膜を形成する工程
と、 前記耐酸化性膜を含む前記半導体層上の所定領域にレジ
スト膜を形成する工程と、 前記耐酸化性膜及び前記レジスト膜をマスクに第２導電
型不純物をイオン注入して前記半導体層上の所定領域に
イオン注入層を形成する工程と、 前記レジスト膜を除去した後に前記耐酸化性膜をマスク
に半導体層をＬＯＣＯＳ酸化して選択酸化膜を形成する
と共に前記イオン注入層を拡散させて第２導電型不純物
層及びチャネルストッパ層を形成する工程と、 前記選択酸化膜をマスクに前記半導体層上を熱酸化して
ゲート酸化膜を形成する工程と、 前記ゲート酸化膜から選択酸化膜上にまたがるようにゲ
ート電極を形成する工程と、 前記ゲート電極及び前記選択酸化膜をマスクに第２導電
型不純物をイオン注入して前記ゲート電極に隣接するよ
うに第２導電型のソース領域を形成すると共に前記ゲー
ト電極と離間された位置に第２導電型のドレイン領域を
形成する工程とを有する半導体装置の製造方法。 2. A semiconductor layer of the first conductivity type is formed in the semiconductor layer of the second conductivity type.
The second conductivity type layer is formed by ion-implanting and diffusing a pure substance.
And a step of forming an oxidation resistant film in a predetermined region on the semiconductor layer
At a predetermined region on the semiconductor layer including the oxidation resistant film.
And forming a second conductive film using the oxidation resistant film and the resist film as a mask.
Type impurities are ion-implanted into a predetermined region on the semiconductor layer.
Forming an ion-implanted layer, and masking the oxidation resistant film after removing the resist film
LOCOS oxidize the semiconductor layer to form a selective oxide film
With the second conductivity type impurity by diffusing the ion implantation layer.
A layer and a channel stopper layer, and thermally oxidizing the semiconductor layer with the selective oxide film as a mask.
A step of forming a gate oxide film and a step of forming a gate oxide film over the selective oxide film are performed.
Forming a gate electrode and using the gate electrode and the selective oxide film as a mask to form a second conductive film.
-Type impurities are ion-implanted to adjoin the gate electrode.
And forming a source region of the second conductivity type,
A drain region of the second conductivity type at a position separated from the contact electrode.
A method of manufacturing a semiconductor device, the method including the step of forming.
素子分離膜下に形成 するチャネルストッパ層形成工程と
同一工程であることを特徴とする請求項２に記載の半導
体装置の製造方法。 3. The step of forming the second conductivity type impurity layer,
A step of forming a channel stopper layer under the element isolation film ,
The semiconductor device according to claim 2, wherein the steps are the same.
Body device manufacturing method.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000125379A JP3454776B2 (en) | 2000-04-26 | 2000-04-26 | Semiconductor device and manufacturing method thereof |
| TW090103346A TW512533B (en) | 2000-04-26 | 2001-02-15 | Semiconductor device and its manufacturing process |
| US09/789,163 US6638827B2 (en) | 2000-04-26 | 2001-02-20 | Semiconductor device and method of manufacturing it |
| CNB011113464A CN1223007C (en) | 2000-04-26 | 2001-03-12 | Semiconductor device and mfg. method thereof |
| KR10-2001-0012568A KR100393153B1 (en) | 2000-04-26 | 2001-03-12 | Semiconductor device and method of manufacturing the same |
| US10/651,855 US7087961B2 (en) | 2000-04-26 | 2003-08-29 | Semiconductor device with reduced on-state resistance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000125379A JP3454776B2 (en) | 2000-04-26 | 2000-04-26 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001308316A JP2001308316A (en) | 2001-11-02 |
| JP3454776B2 true JP3454776B2 (en) | 2003-10-06 |
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ID=18635347
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|---|---|---|---|
| JP2000125379A Expired - Fee Related JP3454776B2 (en) | 2000-04-26 | 2000-04-26 | Semiconductor device and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP3454776B2 (en) |
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| Publication number | Publication date |
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| JP2001308316A (en) | 2001-11-02 |
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