JP3446645B2 - INFORMATION PROCESSING SYSTEM, PERIPHERAL DEVICE SEARCH PROCESSING METHOD USED FOR THE SAME, AND RECORDING MEDIUM RECORDING ITS CONTROL PROGRAM - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system, a peripheral device search processing method used therein, and a recording medium recording a control program therefor, and more particularly to a search processing method for peripheral devices connected to an IO (input / output) bus. .

[0002]

2. Description of the Related Art Conventionally, in information processing systems, C
A plurality of peripheral devices are connected to a PU (Central Processing Unit) via an IO bus. Peripheral device probing (searching) processing is performed to know this system configuration. However, when performing the probing processing, only one of the CPUs installed in the system is Probing is being performed.

Although this depends on the architecture of the bus, generally, a special access, which is different from the normal IO access, which is a configuration access for the probe processing of the peripheral device to set the connection to the bridge or the like, is used. Because there are many. A typical example of this special access is PCI (Peripheral).
There is a configuration cycle on the Component Interconnect bus.

The above-mentioned configuration access has a limitation that only one CPU can access the peripheral device at the same time. In this case, if multiple CPUs simultaneously access peripheral devices,
Information such as connection settings may be destroyed by configuration access performed by multiple CPUs.
Its operation is not guaranteed.

Since this is a limitation on the configuration specifications, when performing the probe processing of the peripheral device, only one of the plurality of CPUs mounted in the system performs the probe processing. ing.

[0006]

In the above-described conventional information processing system, a single CPU performs probing of peripheral devices, but the number of peripheral devices mounted is 2 to 3.
In the case of a small-scale system such as a single wafer, no problem occurs in probe processing by a single CPU. However, in recent years, the scale of the system has increased and more than 10
It is not uncommon to have a system with dozens of peripheral devices (for example, a data warehouse).

In the case of such a large-scale server system,
When a single CPU executes the probe processing, the time required for the processing increases, which causes a problem that the startup performance of the system is significantly reduced.

In other words, the probe processing of peripheral devices is performed by a single CPU, but as a result, the system startup time is increased in a system having a large number of peripheral devices.

Therefore, an object of the present invention is to solve the above problems and to provide an information processing system capable of shortening the time required for probe processing, a peripheral device search processing method used therefor, and a recording medium recording the control program thereof. To provide.

[0010]

An information processing system according to the present invention includes a plurality of central processing units and a plurality of peripheral devices connected to each of the plurality of central processing units via an input / output bus. An information processing system for performing probe processing of the peripheral device to know the configuration, comprising a system bus connected to each of the plurality of central processing units, and the system bus corresponding to each of the plurality of central processing units. A system bus bridge for dividing the system to logically divide the system into a plurality of systems, and means for controlling the system bus bridge so as to divide the system bus when the probe processing is executed, and divide the system bus. In this state, each of the plurality of central processing units is configured to perform the probe processing.

Peripheral device search processing according to the present inventionMethod
Is a plurality of central processing units and each of the plurality of central processing units
Multiple peripheral devices, each connected via an I / O bus
To know the system configuration of the information processing system including and
Peripheral device search for probe processing of the peripheral device
ProcessingMethodAnd connect to each of the plurality of central processing units.
A continuous system bus to each of the plurality of central processing units
Correspondingly divide and logically divide the system into multiple systems
It has a step of dividing,
The plurality of central processing units are separated with the system bus separated.
Each unit is made to perform the probe processing.

A recording medium recording a peripheral device search processing control program according to the present invention includes a plurality of central processing units and a plurality of peripheral devices connected to each of the plurality of central processing units via an input / output bus. In order to know the system configuration of the information processing system, a recording medium recording a peripheral device search processing control program for causing a specific central processing unit of the plurality of central processing units to perform probe processing of the peripheral device. The peripheral device search processing control program causes the specific central processing unit to divide the system bus connected to each of the plurality of central processing units so as to correspond to each of the plurality of central processing units. Is logically divided into a plurality of systems, and the system bus is divided when the probe processing is executed. And to perform the probing to the central processing unit each number.

That is, the method of accelerating the peripheral device search processing according to the present invention is implemented on a CPU in a system including a CPU, a main memory, an IO bus bridge, and hardware (HW) such as peripheral devices. The present invention relates to speeding up of a search process of a peripheral device connected to an IO bus by operating control firmware (FW) or OS (operating system).

Method for speeding up peripheral device search processing according to the present invention
According to the method , the search process, which has been conventionally performed by a single CPU, is simultaneously processed by a plurality of CPUs, thereby realizing a high-speed search process.

More specifically, a control firmware for executing system startup processing, various service processing for the OS, exception processing, etc., or an OS for controlling system operation is operating on a plurality of CPUs.

Which of the control firmware and the OS operates depends on the operating state of the system at any given time. The control firmware or the OS executes a probe process for confirming the presence or absence of the connection of the plurality of peripheral devices respectively connected to the plurality of IO buses under the plurality of IO bus bridges in the process of each processing.

Conventionally, when performing the probe processing of peripheral devices, among the plurality of CPUs mounted in the system,
Only one of the CPUs is performing the probe processing. This depends on the bus architecture, but in general, the probing processing of peripheral devices often uses a special access called a configuration access, which is different from a normal IO access. A typical example of this special access is a configuration cycle on the PCI bus.

The configuration access has a limitation that only one CPU can access the peripheral device at the same time. If a plurality of CPUs simultaneously access peripheral devices, their operations are not guaranteed. Therefore, since the probe processing of peripheral devices is performed by a single CPU, the system startup time increases.

The present invention enables probe processing to peripheral devices under the control of the IO bus by a plurality of CPUs at the same time, thereby realizing high-speed probe processing and shortening system startup time.

That is, in order to deal with the problem that the system startup time is increased, the system is logically divided into a plurality of systems only during the configuration so that the probe processing of the peripheral devices from the plurality of CPUs does not conflict. Install a bridge that divides on the system bus. With this bridge, a plurality of CPUs can perform the probe processing at the same time, and the probe time can be shortened.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an information processing system according to an embodiment of the present invention. In the figure, an information processing system according to an embodiment of the present invention includes two CPUs 1-0 and 1-1 in which a control firmware and an OS (operating system) operate, and a main memory 2 that holds and stores system information. , CPU1-
0, 1-1 and main memory 2 and peripheral devices 50-0 to 5n
I / O bus bridges 3-0 and 3-1 which control the interface with 0-0 and 50-1 to 5n-1, a system bus bridge 4, and peripheral devices 50-0 to 5n-0 and 5
It is composed of 0-1 to 5n-1, a system bus 100, and IO buses 110 and 120.

The system bus bridge 4 separates the CPU 1-0 and the IO bus bridge 3-0 from the CPU 1-1 and the IO bus bridge 3-1.
Implemented on.

IO buses 110 and 120 are connected under the IO bus bridges 3-0 and 3-1 respectively. IO
N peripheral devices 5 are provided on each of the buses 110 and 120.
0-0 to 5n-0 and 50-1 to 5n-1 are connected.

FIG. 2 is a block diagram showing the configuration of the system bus bridge 4 of FIG. In the figure, a system bus bridge 4 includes transaction determination units 41 and 44 that determine whether a transaction that flows on the system bus 100 is a configuration access, and a configuration bridge 42 that divides the configuration access that flows on the system bus 100. ON / OFF of the function of the configuration bridge 42 (ON / OF
F) The bridge control unit 43 is in charge of control.

FIG. 3 is a block diagram showing the configuration of the CPUs 1-0 and 1-1 shown in FIG. In the figure, CPU1-0,
Control firmware (FW) 10-0,1 on 1-1
0-1 or OS is running. In FIG. 3, the control firmware 10-0, 10-1 is the CPU 1-0, 1
Although it is provided inside -1, it is also possible to provide a control memory on the system bus 100 and store a program such as an OS in the control memory. As the control memory, a ROM (read only memory), an IC (integrated circuit) memory, or the like can be used.

FIG. 4 is a block diagram showing the configuration of the main memory 2 of FIG. In the figure, in the main memory 2, the CPU 1-0 is connected to the peripheral device 50-0 connected under the IO bus 3-0.
~ 5n-0 probe result storage unit 20 for storing the result of the probe processing, and CPU 1-1 IO bus 3-1.
A probe result storage unit 21 for storing the results of the probe processing of the peripheral devices 50-1 to 5n-1 connected thereunder is provided.

FIG. 5 is a flow chart showing the probe processing in one embodiment of the present invention. The probe processing according to the embodiment of the present invention will be described in detail with reference to FIGS. In the processing operation shown in FIG. 5, programs such as the control firmware 10-0 and 10-1 are executed by the CPU 1.
It is realized by executing −0,1-1.

The control firmware 10-0 and 10-1 operate on the CPUs 1-0 and 1-1, respectively, and the control firmware 10-0 plays a main role in system startup processing at system startup. (Figure 5 Step A
1). The control firmware 10-1 waits until there is a signal from the control firmware 10-0 to start probe processing to the peripheral devices 50-1 to 5n-1 under the control of the IO bridge 3-1 (step B1 in FIG. 5).

The CPU 1-0 starts the probe processing of the system (step A2 in FIG. 5). First, CPU1-
0 instructs the bridge controller 43 in the system bus bridge 4 to divide the configuration access from the CPU 1-0 (step A3 in FIG. 5).

As a result, the bridge controller 43 thereafter controls the configuration bridge 42 so that the configuration access flowing on the system bus 100 is divided (see FIGS. 2 and 3).

2 and 3, it can be seen that the configuration bridge 42 logically divides the information processing system according to the present embodiment into two systems, a 0 system and a 1 system.

The CPU 1-0 is
It is instructed to start the probe processing under the O-bus bridge 3-1 (step A4 in FIG. 5). In response to this instruction, the CPU 1-1 ends the waiting state and starts probe processing for the peripheral devices 50-1 to 5n-1 under the IO bus bridge 3-1 (steps B2 and B in FIG. 5).
3).

At the same time, the CPU 1-0 executes a probe process for the peripheral devices 50-0 to 5n-0 under the IO bus bridge 3-0 (step A5 in FIG. 5). In reality, the CPU 1-0 uses the IO bus bridge 3-0, and the C
PU1-1 is not aware of IO bus bridge 3-1. In the system logically divided by the system bus bridge 4, the CPUs 1-0 and 1-1 probe under the IO bus bridge of the system to which each belongs.

In the present embodiment, the configuration bridge 42 executes the probe processing for the peripheral devices 50-0 to 5n-0 under the control of the IO bus bridge 3-0 belonging to the 0 system in which the CPU 1-0 is logically divided. To do. Further, the CPU 1-1 executes probe processing for the peripheral devices 50-1 to 5n-1 under the control of the IO bus bridge 3-1 belonging to the 1st system.

During the probe processing, the CPUs 1-0 and 1-1 access the main memory 2. CPU 1-0, 1-
When an access from 1 to the main memory 2 occurs, a transaction for the access flows on the system bus 100. When the transaction discriminating units 41 and 44 receive a transaction that has flowed on the system bus 100, whether the transaction is a configuration access or another transaction (for example, access to the main memory 2 or peripheral devices 50-0 to 50-0).
5n-0, 50-1 to 5n-1, etc.) are separated.

For configuration access,
The transaction is sent to the upper path in the system bus bridge 4 (see FIG. 3). Further, in the case other than the configuration access, the transaction is sent to the lower bus in the system bus bridge 4 (see FIG. 4). As a result, in the configuration access flowing through the upper bus, no data flows from 0 system to 1 system or from 1 system to 0 system across systems. On the other hand, transactions such as access to the main memory flowing through the lower bus flow across the systems, so that the main memory 2 can be accessed.

Next, the CPU 1-0 stores the result of the probe processing in the probe result storage section 20 on the main memory 2 (step A6 in FIG. 5). Further, the CPU 1-1 stores the result of the probe processing in the probe result storage unit 21 (step B4 in FIG. 5). The CPU 1-0 merges the probe results stored in the CPUs 1-0 and 1-1 into one (step A7 in FIG. 5). It goes without saying that this merged result is the same as that which was conventionally probed by a single CPU.

Finally, after the probe processing is completed, the CPU1-
0 instructs the bridge controller 43 in the system bus bridge 4 to cancel the divided state (step A8 in FIG. 5), and completes the probe processing (step A in FIG. 5).
9). As a result, the bridge control unit 43 controls the configuration bridge 42 so as to release the divided state of the system bus 100 in order to allow the configuration access to flow on the system bus 100.

As described above, the peripheral devices 50-0 to 5n-0, 50- connected under the IO buses 110 and 120 are connected.
In the probe processing for 1 to 5n-1, what was conventionally performed by a single CPU is replaced by a plurality of CPUs at the same time.
The time required for the probe processing can be shortened by carrying out 1-0 and 1-1.

This is the CPU which constitutes the information processing system
This is because by using 1-0, 1-1, IO bridges 3-0, 3-1 and system bus bridge 4, the system is logically divided into two systems only at the time of configuration. As a result, at the same timing, CP
U1-0 is a peripheral device 50 under the IO bridge 3-0.
CPU1-1 executes probe processing for -0 to 5n-0.
Is a peripheral device 50-1 to 5 under the IO bridge 3-1.
The probe processing for n-1 can be performed respectively.

FIG. 6 is a block diagram showing the configuration of an information processing system according to another embodiment of the present invention. In the figure,
An information processing system according to another embodiment of the present invention includes a CPU 1-0 to 1-n in which control firmware and an OS operate.
And a main memory 2 for holding and storing information of the information processing system
And an IO bus bridge 3-0 that controls the interfaces between the CPUs 1-0 to 1-n and the main memory 2 and the peripheral devices 50-0 to 5n-0, ..., 50-n to 5n-n.
3-n and system bus bridges 4-0 to 4- (n-
1), the system bus 100, and the IO buses 110 to 1n
0 and peripheral devices 50-0 to 5n-0, ..., 50-
n to 5n-n.

The configuration of the information processing system according to the embodiment of the present invention is as follows: peripheral devices 50-0 to 5n-0, 50-1.
2 CPUs that perform probe processing for 5n-1
The information processing system according to the other embodiment of the present invention has no limitation on the number of CPUs and IO bridges, although it has 0, 1-1 and two IO bridges 3-0, 3-1.

An information processing system according to another embodiment of the present invention has n + 1 system bus bridges 4 for n + 1 CPUs 1-0 to 1-n and IO bridges 3-0 to 3-n.
By arranging −0 to 4- (n−1), it is possible to speed up the probe processing.

FIG. 7 is a block diagram showing the configuration of the CPUs 1-0 to 1-n shown in FIG. In the figure, CPU 1-0
The control firmware 10-0 to 10-n or the OS is operating on 1-n. Although the control firmware 10-0 to 10-n is provided inside the CPUs 1-0 to 1-n in FIG. 7, a control memory is provided on the system bus 100 and a program such as an OS is stored in the control memory. It is also possible to do so. A ROM, an IC memory or the like can be used as this control memory.

FIG. 8 is a block diagram showing the structure of the main memory 2 of FIG. In the figure, CPU 1-0 to main memory 2
Peripheral devices 50-0 to 5n-0, ..., 50-n to 5, each of which 1-n are connected under the IO bus 3-0 to 3-n
Probe result storage units 20 to 2n are provided for storing the results of the nn probe processing.

Although not shown, the system bus bridge 4- of the information processing system according to another embodiment of the present invention.
Each of 0 to 4- (n-1) has the same configuration as the system bus bridge 4 according to the embodiment of the present invention shown in FIG.

The probe processing in the information processing system according to another embodiment of the present invention will be described with reference to FIGS. 6 to 8. The control firmware 10-0 to 1
0-n are operating on the CPUs 1-0 to 1-n, respectively.

At system startup, control firmware 1
0-0 takes the lead in the process of starting up the information processing system. When the CPU 1-0 starts the probe processing in the information processing system, the CPU 1-0 causes all the system bus bridges 4-0 to 4-0 mounted in the information processing system.
CP to the bridge controller 43 in 4- (n-1)
Instruct to disconnect the configuration access from U1-0 to 1-n.

As a result, all system bus bridges 4
The bridge controller 43 in -0 to 4- (n-1) is
All system bus bridges 4 to divide the configuration access flowing on the system bus 100.
It controls the configuration bridge 42 in -0 to 4- (n-1) (see FIG. 7). Referring to FIG.
The information system according to the present embodiment is logically divided into 0 system to n system by the configuration bridge 42.

The CPU 1-0 has an IO bus bridge 3-for all CPUs 1-1 to 1-n other than the CPU 1-0.
Peripheral devices 50-1 to 5n-1, subordinate to 1 to 3-n, ...
.., 50-n to 5n-n are instructed to start probe processing.

As a result, all the CPUs 1-0 to 1-n are to the peripheral devices 50-0 to 5n-0, ..., 50-n to 5n-n under the control of the respective IO bus bridges 3-0 to 3-n. Start probe processing.

After completion of the probe processing, all CPUs 1-0
-CPU1-n stores the result of the probe processing in the probe result storage units 20-2n on the main memory 2. CPU1-0
Merges the probe results stored in all the CPUs 1-0 to 1-n into one. This merge result is conventionally a single C
It goes without saying that the same result as when the PU was performing probe processing was obtained (see FIG. 8).

Finally, after the probe processing is completed, the CPU1-
0 is all system bus bridges 4-0 to 4- (n-
The bridge controller 43 of 1) is instructed to cancel the divided state, and the probe processing is completed.

As a result, even in the other embodiment of the present invention, the system is logically divided into n + 1 systems by the n system bus bridges 4-0 to 4- (n-1) only at the time of configuration. C at the same timing
PUs 1-0 to 1-n are peripheral devices under control of the IO bridges 3-0 to 3-n 50-0 to 5n-0, ..., 50-n to
Since the probe processing for each of 5n-n can be performed, the time required for the probe processing can be shortened.

[0055]

As described above, according to the present invention, a plurality of central processing units and a plurality of peripheral devices connected to each of the plurality of central processing units via input / output buses are provided.
In an information processing system that performs peripheral device probe processing in order to know the system configuration, when performing probe processing, the system bus connected to each of the multiple central processing units is divided corresponding to each of the multiple central processing units. By having each of the plurality of central processing units perform the probe processing in a state where the system is logically divided into a plurality of systems, there is an effect that the time required for the probe processing can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an information processing system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a system bus bridge of FIG.

FIG. 3 is a block diagram showing a configuration of a CPU of FIG.

FIG. 4 is a block diagram showing a configuration of a main memory of FIG.

FIG. 5 is a flowchart showing a probe process in an embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of an information processing system according to another embodiment of the present invention.

7 is a block diagram showing a configuration of a CPU of FIG.

8 is a block diagram showing a configuration of a main memory of FIG.

[Explanation of symbols]

1-0 to 1-n CPU 2 main memory 3-0 to 3-n IO bridge 4-0-4- (n-1) system bus bridge 10-0 to 10-n control firmware 20-2n probe result storage 41,44 Transaction discriminator 42 configuration bridge 43 Bridge controller 50-0 to 5n-0, ..., 50-n to 5n-n peripheral devices 100 system bus 110-1n0 IO bus

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Claims (7)

(57) [Claims] 1. A plurality of central processing units, and a plurality of peripheral devices connected to each of the plurality of central processing units via an input / output bus. Probe processing of the peripheral devices is performed to know a system configuration. An information processing system to perform, wherein the system bus is connected to each of the plurality of central processing units, and the system bus is divided corresponding to each of the plurality of central processing units to logically divide the system into a plurality of systems. A system bus bridge for dividing, and a means for controlling the system bus bridge so as to divide the system bus when the probe processing is executed, and in each of the plurality of central processing units with the system bus divided. An information processing system characterized by being configured to perform the probe processing. 2. The system bus bridge is instructed to determine whether a transaction flowing on the system bus is a configuration access of the probe processing, and an instruction to divide the system bus, and the determination means The information processing system according to claim 1, further comprising a configuration bridge that divides the system bus when the configuration access is determined. 3. A storage means for storing a result of the probe processing of each of the plurality of central processing units, and a means for connecting contents of the storage means when the probe processing is completed. Alternatively, the information processing system according to claim 2. 4. A peripheral device in order to know a system configuration of an information processing system including a plurality of central processing units and a plurality of peripheral devices connected to each of the plurality of central processing units via an input / output bus. A peripheral device search processing method for performing probe processing, wherein a system bus connected to each of the plurality of central processing units is divided corresponding to each of the plurality of central processing units to logically divide the system into a plurality of systems. A peripheral device search processing method comprising a step of dividing, wherein each of the plurality of central processing units is made to perform the probe processing while the system bus is divided when the probe processing is executed. 5. The step of dividing the system bus includes a step of determining whether a transaction flowing on the system bus is a configuration access of the probe processing, and an instruction to divide the system bus and the configuration. 5. The peripheral device search processing method according to claim 4, further comprising the step of dividing the system bus when it is determined that the peripheral access is performed. 6. The method according to claim 1, further comprising a step of storing the probe processing result of each of the plurality of central processing units, and a step of linking the stored probe processing result when the probe processing is completed. The peripheral device search processing method according to claim 4 or claim 5. 7. In order to know a system configuration of an information processing system including a plurality of central processing units and a plurality of peripheral devices connected to each of the plurality of central processing units via an input / output bus, the plurality of central processing units are provided. A recording medium recording a peripheral device search processing control program for causing a specific central processing unit of the central processing units to perform probe processing of the peripheral device, wherein the peripheral device search processing control program is the specific central processing unit. The processing unit divides a system bus connected to each of the plurality of central processing units in correspondence with each of the plurality of central processing units to logically divide the information processing system into a plurality of systems, and performs the probe processing. When the system bus is divided during execution, each of the plurality of central processing units is made to perform the probe processing. A recording medium on which a side device search processing control program is recorded.