JP2000207345A - Information processing system, peripheral device retrieval processing method for the system and storage medium recording its control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing system which can shorten time required for probe processing. SOLUTION: A bridge control section 43 in a system bus bridge 4 controls a configuration bridge 42 to cut the configuration access flowing on a system bus 100 into pieces when transaction discriminating sections 41 and 44 discriminate a transaction flowing on the bus 100 as the configuration access upon receiving an instruction from a CPU 1-0 to cut the configuration access into pieces.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system, a peripheral device search processing system used therefor, and a recording medium on which a control program is recorded, and more particularly, to a peripheral device search processing method connected to an IO (input / output) bus. .

[0002]

2. Description of the Related Art Conventionally, in information processing systems, C
A plurality of peripheral devices are connected to a PU (Central Processing Unit) via an IO bus. In order to know the system configuration, a probe (search) process of the peripheral device is performed, but when performing the probe process, only one of the plurality of CPUs mounted on the system is used. Probe processing is being performed.

[0003] Although this depends on the bus architecture, in general, probe processing of a peripheral device uses special access different from ordinary IO access, ie, configuration access for setting connection to a bridge or the like. Because there are many. A typical example of this special access is PCI (Peripheral).
There is a configuration cycle on the Component Interconnect bus.

The above configuration access has a limitation that only one CPU can access a peripheral device at the same time. In this case, if multiple CPUs access the peripheral device at the same time,
Since information such as connection settings may be destroyed by configuration access performed by multiple CPUs,
Its operation is not guaranteed.

Since this is a limitation in the specification of the configuration, when performing the probe processing of the peripheral device, only one of a plurality of CPUs mounted in the system performs the probe processing. ing.

[0006]

In the above-described conventional information processing system, a single CPU performs a probe process of a peripheral device, but the number of mounted peripheral devices is two to three.
In the case of a small-scale system of about one, no problem occurs in the probe processing by a single CPU. However, in recent years, the scale of the system has increased, and more than 10
It is not unusual for a system to be equipped with several tens of peripheral devices (for example, a data warehouse).

In the case of such a large-scale server system,
When a single CPU performs the probe process, the time required for the process increases, which causes a problem that the system startup performance is greatly reduced.

That is, although the peripheral device is probed by a single CPU, a system in which a large number of peripheral devices are mounted causes a problem of an increase in system start-up time.

Accordingly, an object of the present invention is to provide an information processing system capable of solving the above problems and reducing the time required for probe processing, a peripheral device search processing method used therefor, and a recording medium storing a control program therefor. To provide.

[0010]

An information processing system according to the present invention includes a plurality of central processing units and a plurality of peripheral devices connected to each of the plurality of central processing units via an input / output bus. An information processing system for performing a probe process of the peripheral device to know a configuration, comprising: a system bus connected to each of the plurality of central processing units; and a system bus corresponding to each of the plurality of central processing units. A system bus bridge for dividing and logically dividing the system into a plurality of systems; and a means for controlling the system bus bridge so as to divide the system bus during the execution of the probe processing, wherein the system bus is divided. In this state, the plurality of central processing units are configured to perform the probe processing.

A peripheral device search processing system according to the present invention is a system configuration of an information processing system including a plurality of central processing units and a plurality of peripheral devices connected to each of the plurality of central processing units via an input / output bus. A peripheral device search processing method for performing probe processing of the peripheral device in order to know a system bus, wherein a system bus connected to each of the plurality of central processing units is divided corresponding to each of the plurality of central processing units. Is logically divided into a plurality of systems, and the probe processing is performed by each of the plurality of central processing units in a state where the system bus is divided at the time of performing the probe processing.

A recording medium storing a peripheral device search processing control program according to the present invention includes a plurality of central processing units, and a plurality of peripheral devices connected to each of the plurality of central processing units via an input / output bus. A recording medium storing a peripheral device search processing control program for causing a specific central processing unit of the plurality of central processing units to perform a probe process of the peripheral device in order to know a system configuration of the information processing system. The peripheral device search processing control program causes the specific central processing unit to divide the system bus connected to each of the plurality of central processing units corresponding to each of the plurality of central processing units, and Is logically divided into a plurality of systems, and the system bus is divided while executing the probe processing. And to perform the probing to the central processing unit each number.

That is, the method for speeding up the peripheral device search processing according to the present invention is based on a system including a CPU, a main memory, an IO bus bridge, and hardware (HW) such as a peripheral device. The present invention relates to speeding up a process of searching for peripheral devices connected to an IO bus by operating control firmware (FW) or an OS (operating system).

In the method for speeding up the peripheral device search processing according to the present invention, the search processing conventionally performed by a single CPU is simultaneously processed by a plurality of CPUs, thereby increasing the speed of the search processing. It will be realized.

More specifically, control firmware for executing system start-up processing, various service processing for the OS, exception processing, and the like, and an OS for managing the system operation are operated on a plurality of CPUs.

Whether the control firmware or the OS operates depends on the operation state of the system at an arbitrary time. In the course of each processing, the control firmware or the OS performs probe processing for confirming whether or not a plurality of peripheral devices respectively connected to a plurality of IO buses under the plurality of IO bus bridges are connected.

Conventionally, when performing a probe process of a peripheral device, of a plurality of CPUs mounted on the system,
Only one of the CPUs performs the probe process. Although this depends on the bus architecture, the probe processing of the peripheral device generally uses a special access called a configuration access, which is different from a normal IO access. A typical example of this special access is a configuration cycle on a PCI bus.

The configuration access has a limitation that only one CPU can access a peripheral device at the same time. If a plurality of CPUs simultaneously access a peripheral device, the operation is not guaranteed. Therefore, the probe processing of the peripheral device is performed by a single CPU, so that the system start-up time increases.

According to the present invention, a plurality of CPUs can simultaneously perform probe processing on peripheral devices under the control of the IO bus, thereby realizing high-speed probe processing and shortening the system startup time.

In other words, in order to cope with the problem that the system start-up time is increased, the system is logically divided into a plurality of systems only at the time of configuration so that probing of peripheral devices from a plurality of CPUs does not conflict. Install a bridge on the system bus. With this bridge, a plurality of CPUs can simultaneously execute the probe process, and the probe time can be reduced.

[0021]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an information processing system according to one embodiment of the present invention. Referring to FIG. 1, an information processing system according to an embodiment of the present invention includes two CPUs 1-0 and 1-1 on which a control firmware and an OS (operating system) operate, a main memory 2 for holding and storing system information, respectively. , CPU1-
0, 1-1 and main memory 2 and peripheral devices 50-0 to 5n
−0, 50-1 to 5n−1, an IO bus bridge 3-0, 3-1 for controlling an interface between the system bus bridge 4, and peripheral devices 50-0 to 5n-0, 5,
0-1 to 5n-1, a system bus 100, and IO buses 110 and 120.

The system bus bridge 4 separates the CPU 1-0 and the IO bus bridge 3-0 from the CPU 1-1 and the IO bus bridge 3-1.
Implemented above.

Under the control of the IO bus bridges 3-0 and 3-1 are connected IO buses 110 and 120, respectively. IO
On each of the buses 110 and 120, n peripheral devices 5
0-0 to 5n-0 and 50-1 to 5n-1 are connected.

FIG. 2 is a block diagram showing the configuration of the system bus bridge 4 of FIG. In the figure, a system bus bridge 4 includes transaction determining units 41 and 44 for determining whether a transaction flowing on the system bus 100 is a configuration access, and a configuration bridge 42 for dividing the configuration access flowing on the system bus 100. ON / OFF of the function of the configuration bridge 42 (ON / OF)
And F) a bridge control unit 43 for controlling.

FIG. 3 is a block diagram showing the configuration of the CPUs 1-0 and 1-1 of FIG. In the figure, CPUs 1-0,
On 1-1, control firmware (FW) 10-0,1
0-1 or OS is running. In FIG. 3, the control firmware 10-0, 10-1 is replaced by the CPU 1-0, 1
-1, but it is also possible to provide a control memory on the system bus 100 and store a program such as an OS in the control memory. As the control memory, a ROM (Read Only Memory), an IC (Integrated Circuit) memory, or the like can be used.

FIG. 4 is a block diagram showing the configuration of the main memory 2 of FIG. In the figure, a main memory 2 stores a CPU 1-0 in a peripheral device 50-0 connected under the control of an IO bus 3-0.
The probe result storage unit 20 for storing the results of performing the probe processing of .about.5n-0 and the CPU 1-1 is connected to the IO bus 3-1.
A probe result storage unit 21 is provided for storing a result of performing a probe process on the peripheral devices 50-1 to 5n-1 connected under the device.

FIG. 5 is a flowchart showing the probe processing in one embodiment of the present invention. The probe processing according to one embodiment of the present invention will be described in detail with reference to FIGS. Note that the processing operation shown in FIG.
This is realized by executing −0, 1-1.

The control firmware 10-0 and 10-1 operate on the CPUs 1-0 and 1-1, respectively, and when the system is started up, the control firmware 10-0 is mainly responsible for executing system start-up processing. (FIG. 5 step A
1). The control firmware 10-1 waits until there is a signal from the control firmware 10-0 to start the probe processing to the peripheral devices 50-1 to 5n-1 under the IO bridge 3-1 (step B1 in FIG. 5).

The CPU 1-0 starts a system probe process (step A2 in FIG. 5). First, CPU1-
0 instructs the bridge controller 43 in the system bus bridge 4 to disconnect the configuration access from the CPU 1-0 (step A3 in FIG. 5).

As a result, the bridge control unit 43 thereafter controls the configuration bridge 42 so that the configuration access flowing on the system bus 100 is divided (see FIGS. 2 and 3).

Referring to FIGS. 2 and 3, it can be seen that the information processing system according to the present embodiment is logically divided by the configuration bridge 42 into two systems, system 0 and system 1.

The CPU 1-0 sends a signal I to the CPU 1-1.
It instructs to start the probe processing under the O bus bridge 3-1 (FIG. 5, step A4). Upon receiving this instruction, the CPU 1-1 ends the waiting state and starts a probe process for the peripheral devices 50-1 to 5n-1 under the IO bus bridge 3-1 (steps B2 and B in FIG. 5).
3).

At the same time, the CPU 1-0 performs a probe process on the peripheral devices 50-0 to 5n-0 under the IO bus bridge 3-0 (step A5 in FIG. 5). Actually, the CPU 1-0 connects the IO bus bridge 3-0 with
The PU 1-1 does not recognize the IO bus bridge 3-1. In the system logically divided by the system bus bridge 4, the CPUs 1-0 and 1-1 probe the subordinates of the IO bus bridge of the system to which they belong.

In this embodiment, the configuration bridge 42 causes the CPU 1-0 to perform probe processing on the peripheral devices 50-0 to 5n-0 under the IO bus bridge 3-0 belonging to the logically separated system 0. I do. Further, the CPU 1-1 performs a probe process on the peripheral devices 50-1 to 5n-1 under the IO bus bridge 3-1 belonging to the first system.

During the probe process, the CPUs 1-0 and 1-1 access the main memory 2. CPU1-0,1-
When an access to the main memory 2 occurs from 1, a transaction for the access flows on the system bus 100. When receiving the transaction flowing on the system bus 100, the transaction determination units 41 and 44 determine whether the transaction is a configuration access or another transaction (for example, an access to the main memory 2 or a peripheral device 50-0 to a peripheral device 50-0).
5n-0, 50-1 to 5n-1).

In the case of configuration access,
The transaction is sent to the upper path in the system bus bridge 4 (see FIG. 3). In the case other than the configuration access, a transaction is sent to the lower bus in the system bus bridge 4 (see FIG. 4). As a result, in the configuration access flowing through the upper bus, data does not flow across the systems from system 0 to system 1 or system 1 to system 0. Conversely, transactions such as main memory access flowing through the lower bus flow across systems, so that access to the main memory 2 becomes possible.

Next, the CPU 1-0 stores the result of the probe processing in the probe result storage unit 20 in the main memory 2 (step A6 in FIG. 5). Further, the CPU 1-1 stores the result of the probe processing in the probe result storage unit 21 (step B4 in FIG. 5). The CPU 1-0 merges the probe results stored by the CPUs 1-0 and 1-1 into one (step A7 in FIG. 5). It goes without saying that this merge result is the same as the result of the conventional probe processing performed by a single CPU.

Finally, after the completion of the probe processing, the CPU 1-
0 instructs the bridge controller 43 in the system bus bridge 4 to release the disconnected state (Step A8 in FIG. 5), and completes the probe processing (Step A in FIG. 5).
9). As a result, the bridge controller 43 controls the configuration bridge 42 to release the divided state of the system bus 100 so that the configuration access flows on the system bus 100.

As described above, the peripheral devices 50-0 to 5n-0, 50- connected under the IO bus 110, 120
In the probe processing for 1 to 5n-1, what was conventionally performed by a single CPU is now replaced by a plurality of CPUs.
By performing the steps 1-0 and 1-1, the time required for the probe processing can be reduced.

This is a CPU constituting an information processing system.
This is because the system is logically divided into two systems only at the time of configuration by using 1-0, 1-1, IO bridges 3-0, 3-1 and system bus bridge 4. As a result, at the same timing, the CP
U1-0 is a peripheral device 50 under the IO bridge 3-0.
The probe processing for −0 to 5n-0 is performed by the CPU 1-1.
Are peripheral devices 50-1 to 50-5 under the IO bridge 3-1
Each of the probe processes for n-1 can be performed.

FIG. 6 is a block diagram showing the configuration of an information processing system according to another embodiment of the present invention. In the figure,
An information processing system according to another embodiment of the present invention includes CPUs 1-0 to 1-n on which control firmware and an OS operate.
And a main memory 2 for holding and storing information of the information processing system
And an IO bus bridge 3-0 that controls an interface between the CPUs 1-0 to 1-n and the main memory 2 and the peripheral devices 50-0 to 5n-0, ..., 50-n to 5n-n.
3-n and the system bus bridges 4-0 to 4- (n-
1), the system bus 100, and the IO buses 110 to 1n
0 and peripheral devices 50-0 to 5n-0, ..., 50-
n to 5n-n.

The configuration of the information processing system according to one embodiment of the present invention includes peripheral devices 50-0 to 5n-0, 50-1 to 50-n.
2 CPUs 1 to perform probe processing for 5n-1
0, 1-1 and two IO bridges 3-0, 3-1 are provided, but the number of CPUs and IO bridges is not limited in the information processing system according to another embodiment of the present invention.

An information processing system according to another embodiment of the present invention comprises n system bus bridges 4 for n + 1 CPUs 1-0 to 1-n and IO bridges 3-0 to 3-n.
By arranging −0−4− (n−1), the speed of the probe processing can be increased.

FIG. 7 is a block diagram showing the configuration of CPUs 1-0 to 1-n of FIG. Referring to FIG.
On 1-n, the control firmware 10-0 to 10-n or the OS is operating. In FIG. 7, the control firmware 10-0 to 10-n are provided inside the CPUs 1-0 to 1-n. However, a control memory is provided on the system bus 100, and a program such as an OS is stored in the control memory. It is also possible to do so. A ROM, an IC memory, or the like can be used as the control memory.

FIG. 8 is a block diagram showing the structure of the main memory 2 of FIG. In the figure, main memory 2 has CPUs 1-0 to
1-n, peripheral devices 50-0 to 5n-0,..., 50-n to 5 each connected under the control of IO buses 3-0 to 3-n
Probe result storage units 20 to 2n for storing the results of performing the nn probe processing are provided.

Although not shown, the system bus bridge 4 of the information processing system according to another embodiment of the present invention.
The configuration of each of 0 to 4- (n-1) is the same as that of the system bus bridge 4 according to the embodiment of the present invention shown in FIG.

The probe processing in the information processing system according to another embodiment of the present invention will be described with reference to FIGS. The control firmware 10-0 to 1
0-n operate on the CPUs 1-0 to 1-n, respectively.

When starting up the system, the control firmware 1
0-0 plays a leading role in executing the startup processing of the information processing system. When the CPU 1-0 starts probe processing in the information processing system, the CPU 1-0 executes all system bus bridges 4-0 to 0-0 mounted on the information processing system.
4- (n-1), the bridge control unit 43
An instruction is given to divide configuration access from U1-0 to 1-n.

As a result, all the system bus bridges 4
Thereafter, the bridge control unit 43 in −0−4− (n−1)
All system bus bridges 4 are used to separate configuration accesses flowing on the system bus 100.
It controls the configuration bridge 42 within -0 to 4- (n-1) (see FIG. 7). Referring to FIG.
The information system according to the present embodiment is logically divided by the configuration bridge 42 into 0 system to n system.

The CPU 1-0 sends an IO bus bridge 3 to all the CPUs 1-1 to 1-n other than the CPU 1-0.
Peripheral devices 50-1 to 5n-1 under 1 to 3-n, ...
.., Instructs to start the probe processing for 50-n to 5n-n.

As a result, all of the CPUs 1-0 to 1-n communicate with the peripheral devices 50-0 to 5n-0, ..., 50-n to 5n-n under the respective IO bus bridges 3-0 to 3-n. Start probe processing.

After the completion of the probe processing, all CPUs 1-0
CPU1-n store the results of the probe processing in the probe result storage units 20-2n on the main memory 2. CPU1-0
Merges the probe results stored by all the CPUs 1-0 to 1-n into one. The result of this merge is conventionally a single C
Needless to say, the result is the same as that when the PU performed the probe processing (see FIG. 8).

Finally, after the completion of the probe processing, the CPU 1-
0 indicates all system bus bridges 4-0 to 4- (n-
Instruct the bridge control unit 43 of 1) to release the divided state, and complete the probe processing.

Thus, in another embodiment of the present invention, the system is logically divided into n + 1 systems by n system bus bridges 4-0 to 4- (n-1) only at the time of configuration. At the same timing, C
PU1-0 to 1-n are peripheral devices 50-0 to 5n-0 under the control of IO bridges 3-0 to 3-n, ..., 50-n to
Since the probe processing for 5n-n can be respectively performed, the time required for the probe processing can be reduced.

[0055]

As described above, according to the present invention, a plurality of central processing units and a plurality of peripheral devices connected to each of the plurality of central processing units via an input / output bus are provided.
In an information processing system that performs probe processing of peripheral devices in order to know the system configuration, at the time of execution of probe processing, a system bus connected to each of the plurality of central processing units is divided corresponding to each of the plurality of central processing units. By causing each of the plurality of central processing units to perform the probe processing in a state where the system is logically divided into a plurality of systems, the time required for the probe processing can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a system bus bridge of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a CPU in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a main storage in FIG. 1;

FIG. 5 is a flowchart illustrating a probe process according to an embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of an information processing system according to another embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a CPU in FIG. 6;

FIG. 8 is a block diagram showing a configuration of a main storage of FIG. 6;

[Explanation of symbols]

 1-0 to 1-n CPU 2 Main memory 3-0 to 3-n IO bridge 4-0 to 4- (n-1) System bus bridge 10-0 to 10-n Control firmware 20 to 2n Probe result storage unit 41, 44 Transaction determination unit 42 Configuration bridge 43 Bridge control unit 50-0 to 5n-0, ..., 50-n to 5n-n Peripheral device 100 System bus 110 to 1n0 IO bus

Claims (7)

[Claims] An apparatus includes a plurality of central processing units and a plurality of peripheral devices connected to each of the plurality of central processing units via an input / output bus, and performs probe processing of the peripheral devices to know a system configuration. An information processing system for performing, wherein a system bus connected to each of the plurality of central processing units, and the system bus corresponding to each of the plurality of central processing units are divided to logically convert the system into a plurality of systems. A system bus bridge for splitting, and means for controlling the system bus bridge so as to divide the system bus at the time of execution of the probe process, wherein each of the plurality of central processing units is divided while the system bus is divided. An information processing system configured to perform the probe processing. 2. The system bus bridge according to claim 1, wherein said determination means determines whether a transaction flowing on said system bus is a configuration access for said probe processing, and said determination means is instructed to disconnect said system bus. 2. The information processing system according to claim 1, further comprising: a configuration bridge that disconnects the system bus when the configuration access is determined. 3. The apparatus according to claim 1, further comprising storage means for storing a result of said probe processing of each of said plurality of central processing units, and means for connecting the contents of said storage means when said probe processing is completed. Or the information processing system according to claim 2. 4. The information processing system comprising: a plurality of central processing units; and a plurality of peripheral devices connected to each of the plurality of central processing units via an input / output bus. A peripheral device search processing method for performing probe processing, wherein a system bus connected to each of the plurality of central processing units is divided corresponding to each of the plurality of central processing units to logically convert the system into a plurality of systems. A peripheral device search processing method, comprising a step of dividing, wherein the probe processing is performed by each of the plurality of central processing units in a state where the system bus is divided during the execution of the probe processing. 5. The step of dividing the system bus includes determining whether a transaction flowing on the system bus is a configuration access for the probe processing, and instructing the system bus to be divided, and 5. The peripheral device search processing method according to claim 4, further comprising the step of: dividing the system bus when the access is determined to be a translation access. 6. The method according to claim 1, further comprising the steps of: storing the results of the probe processing of each of the plurality of central processing units; and coupling the stored results of the probe processing when the probe processing is completed. A peripheral device search processing method according to claim 4 or 5. 7. An information processing system comprising: a plurality of central processing units; and a plurality of peripheral devices connected to each of the plurality of central processing units via an input / output bus. A recording medium storing a peripheral device search processing control program for causing a specific central processing unit of the central processing units to perform probe processing of the peripheral device, wherein the peripheral device search processing control program is configured to execute the specific central processing unit. A processor configured to divide a system bus connected to each of the plurality of central processing units in correspondence with each of the plurality of central processing units, to logically divide the information processing system into a plurality of systems; Wherein the plurality of central processing units perform the probe processing in a state where the system bus is divided at the time of execution. A recording medium on which an edge device search processing control program is recorded.