JPH0973436A - Operation mode switching system of multiplied computers - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an operation stitching system of multiplied computers which selectively switch between high-reliablity processing and high-performance processing. SOLUTION: This system has a memory 6, a system bus 10 which connects CPUs 2 and 22 through I/O bridges 8 and 28 having operation mode switching parts 8a and 28a and cache memories 4 and 24 having operation mode switching parts 4a and 24a, a memory 26, a system bus 30 which connects the CPUs 2 and 22 through the I/O bridge 8 and 28 and cache memories 4 and 24, a constitution control processor 42 which issues an instruction for switching to the operation mode of synchronous operation or parallel operation, and a signal line 46 which connects all the I/O bridges 8 and 28; and the constitution control processor 42 issues the switching instruction and then the operation mode is switched from the synchronous operation to the parallel operation or vice versa during the operation of the system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiple computer equipped with a plurality of tightly coupled CPUs and capable of operating in both synchronous and parallel operation modes, at a certain timing during system startup or during operation. The operation mode switching method in.

[0002]

2. Description of the Related Art Generally, data handled in a server system is required to have high reliability and high performance. For example, higher reliability is required for online processing performed in a computer that constitutes a server system, and higher performance is required for batch processing.

A computer for online processing is a CPU,
The hardware configurations such as a memory and an I / O bridge are multiplexed, the same transaction is executed in parallel in each CPU at the same time, and the execution results are compared to improve reliability. Also, by multiplexing the hardware configuration, it is possible to avoid a system failure due to a partial failure.

On the other hand, the computer for batch processing is CP
The hardware configuration of U, cache memory, memory, etc. is multiplexed and one transaction is executed by each CPU. However, since multiple CPUs are installed, multiple transactions are executed independently and in parallel. Will be executed. By simultaneously processing a plurality of transactions in this way, the processing speed as a computer is improved.

Conventionally, by using a general-purpose computer in which a plurality of clusters formed by hardware necessary for processing functions of both CPU and memory are mounted and multiplexed, and the processing speed is extremely high, The requirements for one processing function were realized by one computer.

[0006]

However, even if both processing functions can be executed by one computer,
In the conventional general-purpose computer configuration, when data is processed by either online processing or batch processing,
Until the system was rebooted, only the processing in the operating mode in operation could be performed. This is because conventionally, it is necessary to notify the cache memory or the I / O bridge of the operation mode to be operated in advance, but conventionally there was no means for issuing an instruction to switch the operation mode.

The operation modes include synchronous operation and parallel operation. The synchronous operation means that the same transaction is simultaneously issued to the respective system buses connected to the I / O bridge to cause the CPU to execute the same processing, and the parallel operation is connected to the I / O bridge and selected. It means issuing one transaction to only one system bus and having a single CPU execute the transaction.
The online processing operates in the synchronous operation mode, and the batch processing operates in the parallel operation mode.

The present invention has been made to solve the above problems, and an object of the present invention is to switch an operation mode in a multiplexed computer capable of selectively switching between high reliability processing and high performance processing. To provide a method.

[0009]

In order to achieve the above object, a first aspect of the present invention is to connect a plurality of CPUs and a main storage device to a plurality of system buses, respectively, and perform both synchronous operation and parallel operation. In a multiplex computer capable of operating in any of the above operation modes, a plurality of auxiliary storage means connected to any of the CPUs and all of the system buses and operating in the instructed operation mode, a shared external storage device and all of the above A plurality of external storage device connecting means connected to the system bus and operating in the instructed operation mode.

[0010] The second invention is the above-mentioned first invention, wherein:
It is characterized by having a configuration control means for issuing an instruction to switch to either the synchronous operation mode or the parallel operation mode.

A third invention is the same as the second invention,
A signal line for connecting all the external storage device connecting means is provided, and each external storage device connecting means notifies each other via the signal line that one of the system buses has been secured. To do.

According to a fourth aspect of the present invention, in a multiplex computer in which a plurality of CPUs and a main storage device are connected to a plurality of system buses, respectively, and which can operate in both synchronous operation mode and parallel operation mode, either CPU or A plurality of auxiliary storage means connected to all the system buses and operating in a preset operation mode for each transaction, a shared external storage device, and all the system buses, and preset for each transaction A plurality of external storage device connecting means operating in the operation mode.

A fifth aspect of the invention is the same as the fourth aspect of the invention.
The auxiliary storage means has an operation mode storage unit for storing an operation mode of a transaction to be processed.

A sixth invention is based on the fourth invention.
The external storage device connection means includes an operation mode storage unit that stores an operation mode of a transaction to be processed.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings. Each of the embodiments described below is divided according to the difference in operation mode switching or setting timing. In the drawings used for the description in each embodiment, the same reference numerals are given to the same elements.

Embodiment 1 FIG. 1 is a diagram showing an embodiment of the configuration of a multiplexing computer adopting the operation mode switching system according to the present invention. As shown in FIG. 1, in the present embodiment, the CPU 2, the cache memory 4, the memory 6 and the I / O bridge 8, the CPU 22, the cache memory 24, the memory 26 and the I / O bridge 28.
The hardware configuration is duplicated by forming a cluster in each. The system bus 10 includes the memory 6 and I
The CPUs 2 and 22 are connected via the / O bridges 8 and 28 and the cache memories 4 and 24. System bus 30
Connects the CPUs 2 and 22 via the memory 26, the I / O bridges 8 and 28, and the cache memories 4 and 24.
Further, it has a configuration control processor 42 as a configuration control means for controlling the operation mode switching function, such as issuing an instruction to switch to either the synchronous operation mode or the parallel operation mode during operation. Furthermore, the signal line 46 is
It is provided so as to connect the O bridges 8 and 28.

The cache memories 4 and 24 in this embodiment are connected to the CPUs 2 and 22 and all the system buses 10 and 30, respectively, and the configuration control processor 42 is used.
Is an auxiliary storage unit having operation mode switching units 4a and 24a for switching to the operation mode instructed by. The I / O bridges 8 and 28 are connected to the disk 44 and all the system buses 10 and 30, and have external storages having operation mode switching units 8a and 28a for switching to the operation mode instructed by the configuration control processor 42, respectively. It is a device connection means. The CPUs 2, 22 and the memories 6, 26 may be the conventional central control unit and main storage unit.

The disk 44 is shared by the present multiplex computer, and has an operating system (OS) and a CPU.
It stores various data to be processed by 2 and 22. O
S, etc. are the disk controller 48, the IO buses 12, 3
2, loaded into the memories 6 and 26 connected to the respective system buses 10 and 30 via the I / O bridges 8 and 28.

A feature of this embodiment is that the configuration control processor 42 and the operation mode switching units 4a and 2 are provided.
Since 4a, 8a, and 28a are provided, the operation mode can be switched while the system is operating without rebooting the system.

FIG. 2 is a flow chart showing a switching process from synchronous operation to parallel operation during operation in the present embodiment, and the processing will be described based on this figure.

When switching the operation mode, the configuration control processor 42 simultaneously issues the switching instruction to each of the CPUs 2, 22, the cache memories 4, 24 and the I / O bridges 8, 28 (step 101). C
Upon receiving the operation mode switching instruction (step 102), the PUs 2, 22 are in a state of waiting for a parallel operation start signal from the cache memories 4, 24 (step 10).
3). The cache memories 4 and 24 write back cache data to the memories 6 and 26 if necessary,
In addition, cache flush is performed to invalidate the memory contents (step 104). Then, after selecting the system bus 10 or 30 used in parallel operation and switching to the parallel operation mode (step 105), a parallel operation start signal is issued to the connected CPUs 2 and 22 (step 106). Upon receiving the parallel operation start signal from the cache memories 4 and 24, the CPUs 2 and 22 recognize that they will operate in the parallel operation mode in the future (step 1).
07).

On the other hand, when the I / O bridges 8 and 28 receive the operation mode switching instruction, the I / O bridges 8 and 28 write the contents of the memories 6 and 26 to the disk 44, if necessary, and switch to the parallel operation mode (step 108). At this time, each I
The / O bridges 8 and 28 secure the system bus 10 or 30 to be used.

In this way, the operation mode can be switched from the synchronous operation to the parallel operation while the system is operating. In the case of switching to parallel operation, if the system bus to be used is selected, the cache memories 4, 24 and I /
It is not necessary to synchronize with the O bridges 8 and 28. Since the CPUs 2 and 22 only execute predetermined transactions in a predetermined order, the above-mentioned processing for switching the operation mode may be omitted.

FIG. 3 is a flow chart showing a switching process from the parallel operation to the synchronous operation during the operation in the present embodiment, and the processing will be explained based on this figure.

When switching the operation mode, the configuration control processor 42 simultaneously issues the switching instruction to each of the CPUs 2, 22, the cache memories 4, 24 and the I / O bridges 8, 28 (step 111). C
Upon receiving the operation mode switching instruction (step 112), the PUs 2 and 22 enter a state of waiting for a synchronous operation start signal from the cache memories 4 and 24 (step 11).
3). The cache memories 4 and 24 write back cache data to the memories 6 and 26 if necessary,
In addition, cache flush is performed to invalidate the memory contents (step 114). Then, a parking process of bus arbitration is performed to select a system bus to be used at the time of synchronous operation (step 115), and after selecting which system bus each of the cache memories 4 and 24 uses, the mode is switched to the synchronous operation mode. (Step 116). And the connected CPU
A synchronous operation start signal is issued to Nos. 2 and 22 (step 117). The CPUs 2 and 22 are cache memories 4 and
When receiving the synchronous operation start signal from 24, it recognizes that it will operate in the synchronous operation mode in the future (step 118).

On the other hand, the I / O bridges 8 and 28 write the contents of the memories 6 and 26 to the disk 44, if necessary, when receiving the operation mode switching instruction. Then, a bus arbitration parking process is performed to secure a system bus used in the synchronous operation (step 119), and after selecting which system bus each I / O bridge 8 or 28 uses, the synchronous operation mode is performed. (Step 120). Here, since the synchronous operation issues the same transaction to all the connected system buses at the same time, it is necessary to synchronize all the I / O bridges 8 and 28. I / O bridge 8, 28
Sends a synchronization completion signal to each other via the signal line 46 to check whether synchronization is ready (step 121). When it is confirmed that all the I / O bridges 8 and 28 have switched to the synchronous operation, the computer can start processing in the synchronous operation mode for the first time here.

In this way, the operation mode can be switched from the parallel operation to the synchronous operation while the system is operating. In the case of switching to the synchronous operation, it is necessary to synchronize the respective clusters because the same transactions are concurrently executed in the respective CPUs 2 and 22. In the present embodiment, since the signal line 46 is provided, it is possible to ensure synchronization, and it is possible to reliably switch from parallel operation to synchronous operation even while the system is operating.

As described above, in the present embodiment,
The configuration control processor 42 is provided to issue the operation mode switching instruction. Furthermore, since the cache memory 4, 24 and the I / O bridges 8, 28 are provided with the operation mode switching function, the operation mode can be switched even while the system is operating. Therefore, it is not necessary to reboot the system when operating the computer so that the operation mode is switched and used at a predetermined time.

Embodiment 2 FIG. 4 is a diagram showing another embodiment of the configuration of the multiplexing computer adopting the operation mode switching system according to the present invention. As shown in FIG. 4, the cache memories 104 and 124 according to the present embodiment are
It has operation mode storage units 104b and 124b for storing the operation mode of the transaction to be processed, and also I / O
The bridges 108 and 128 store operation modes of transactions to be processed by the operation mode storage units 108b and 1b.
It is characterized by having 28b. By providing this configuration, in the present embodiment, the I / O bridge 10 is based on the operation mode set for each transaction.
The operation modes of the cache memories 128 and 128 and the cache memories 104 and 124 can be switched to operate. That is, in the first embodiment, it is necessary to collectively execute transactions that operate in the same operation mode to some extent, but in the present embodiment, it is not necessary to continuously execute transactions in the same operation mode. It will be good.

FIG. 5 is a flow chart showing the switching processing from the synchronous operation to the parallel operation during the operation in the present embodiment, and the processing will be explained based on this figure.

First, in this embodiment, the I / O bridges 108 and 128 and the cache memories 104 and 1 are used.
24 operation mode storage units 104b, 124b, 108
The operation mode of each transaction is preset in b and 128b. That is, all the operation mode storage units 104b, 12
The same information is set in 4b, 108b, and 128b. This processing is performed by the configuration control processor 142.
Do. The need to switch the operation mode from synchronous operation to parallel operation is that a transaction executed in a certain synchronous operation mode is processed next to a transaction executed in a parallel operation mode.

The cache memories 104 and 124 enter the parallel operation mode by comparing the information set in the operation mode storage units 104b and 124b with the name of the transaction processed next on the system buses 10 and 30. You will find out that it is necessary to switch. Of course, if the order of transactions is fixed, it is possible to judge in that order.

When switching to the parallel operation, the cache memories 104 and 124 perform write-back of cache data to the memories 6 and 26, if necessary, and perform cache flush to invalidate the memory contents (step 201). . Then, the system bus 10 or 30 used in parallel operation is selected and switched to the parallel operation mode (step 202).

On the other hand, the I / O bridges 108 and 128 are
By comparing the information set in the operation mode storage units 108b and 128b with the transaction name received from the disk 44, it is known that switching to the parallel operation mode is necessary. The I / O bridges 108 and 128 write the contents of the memories 6 and 26 to the disk 44 if necessary,
The mode is switched to the parallel operation mode (step 203). At this time, each I / O bridge 8 or 28 secures the system bus 10 or 30 to be used.

In this way, the operation mode can be switched from the synchronous operation to the parallel operation according to the operation mode set for each transaction even while the system is operating. Since the CPUs 2 and 22 only execute predetermined transactions in a predetermined order, processing for switching operation modes is unnecessary.

FIG. 6 is a flowchart showing the switching process from the parallel operation to the synchronous operation during the operation in the present embodiment, and the processing will be described based on this figure.

The cache memories 104 and 124 have the operation mode storage units 104b and 124b in the same manner as described above.
By comparing the information set in (1) with the name of the transaction to be processed next flowing on the system buses 10 and 30, it is known that the switching to the synchronous operation mode is necessary. Note that the cache memory 104,
The switching process of 124 to the synchronous operation is the same as that of the first embodiment described with reference to FIG.

On the other hand, the I / O bridges 108 and 128 are
Similar to the above, the operation mode storage units 108b, 12
By comparing the information set in 8b with the transaction name received from the disk 44, it is known that the switching to the synchronous operation mode is necessary. After that, I /
The process of switching the O bridges 108 and 128 to the synchronous operation is the same as in the case of the first embodiment described with reference to FIG.

In this way, the operation mode can be switched from the parallel operation to the synchronous operation according to the operation mode set for each transaction even while the system is operating. Since the CPUs 2 and 22 only execute predetermined transactions in a predetermined order, processing for switching operation modes is unnecessary.

By the way, the present embodiment is characterized in that the operation mode is designated for each transaction and each transaction is executed in accordance with the designated operation mode. In the above embodiment, the I / O bridges 108 and 128 and the cache memories 104 and 12 are used.
4, operation mode storage units 104b, 124b, 108b, 128 for presetting the operation mode of each transaction.
By providing b, the operation mode can be voluntarily switched. However, if the operation mode switching time and the like are not taken into consideration, a configuration such as the configuration control processor in the first embodiment is provided. Even if the sequential operation mode is set to the I / O bridges 108 and 128 and the cache memories 104 and 124 from the outside, the same effect can be obtained.

Embodiment 3 FIG. 7 is a configuration diagram showing a main part of the computer according to the present embodiment. A memory 6, an I / O bridge 8 and cache memories 4 and 24 are connected to each system bus 14, and a memory 26, an I / O bridge 28 and cache memories 4 and 24 are connected to the system bus 34. . The disk 44 according to the present embodiment stores two or more OSs having different configuration control parameters. The memory capacity setting, the operation mode designation, and the like are set in the configuration control parameters. In this embodiment, it is assumed that two OSs having different operation modes are stored.

The present embodiment is different from each of the above-mentioned embodiments in that it operates in the operation mode selected at the time of system boot.

FIG. 8 is a flow chart showing the operation in this embodiment, and the operation will be described based on this figure.

A boot request is issued when the system is started up (step 301). At this time, in the present embodiment, which OS is to be started up is selected (step 302). As described above, each OS has a configuration control parameter in which an operation mode is specified, and the operation modes of the I / O bridges 8 and 28 and the cache memories 4 and 24 are set according to the specified operation mode. . The setting of the operation mode can be realized by firmware or software prepared in advance. You may make it set by the structure control processor in the said embodiment. If the operation mode of the selected OS is synchronous operation (step 303), I / O
The bridges 8 and 28 and the cache memories 4 and 24 are set to the synchronous operation mode, and if the selected OS operation mode is the parallel operation, the I / O bridges 8 and 28 and the cache memories 4 and 24 are The operation mode of parallel operation is set (steps 304 and 305).

As described above, the I / O bridges 8 and 28 and the cache memories 4 and 24 can be set in the operation mode selected at the time of system boot, and the computer can be operated in the selected operation mode. The present embodiment is scheduled so that the synchronous operation and the parallel operation are clearly separated in time, and is effective when the operation mode to be operated at the time of system boot is known.

As described above, in each of the above-described embodiments, the example of the double hardware configuration has been shown, but other multiple configurations such as triple and quadruple can also be realized. .

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a multiplexing computer according to a first embodiment which adopts an operation mode switching system according to the present invention.

FIG. 2 is a flowchart showing a switching process from synchronous operation to parallel operation during operation in the first embodiment.

FIG. 3 is a flowchart showing a switching process from a parallel operation during operation to a synchronous operation in the first embodiment.

FIG. 4 is a diagram showing a configuration of a multiplexing computer according to a second embodiment which employs an operation mode switching system according to the present invention.

FIG. 5 is a flowchart showing a switching process from a synchronous operation during operation to a parallel operation in the second embodiment.

FIG. 6 is a flowchart showing a switching process from parallel operation to synchronous operation during operation in the second embodiment.

FIG. 7 is a diagram showing a configuration of a multiplexing computer in a third exemplary embodiment adopting an operation mode switching system according to the present invention.

FIG. 8 is a flowchart showing an operation selection process when the system starts up in the third embodiment.

[Explanation of symbols]

2,22 CPU, 4,24,104,124 cache memory, 4a, 24a, 8a, 28a, 104a,
124a, 108a, 128a Operation mode switching unit, 1
04b, 124b, 108b, 128b Operation mode storage unit, 6, 26 memory, 8, 28, 108, 128 I
/ O bridge, 10, 30, 12, 32, 14, 34
System bus, 42, 142 configuration control processor, 4
4 disks, 46 signal lines, 48 disk controllers.

Claims (6)

[Claims] 1. A plurality of system buses each having a plurality of Cs.
In a multiplexed computer that connects a PU and a main memory and can operate in both synchronous and parallel operation modes, is connected to any CPU and all the system buses, and operates in the instructed operation mode A multiplexing computer, comprising: a plurality of auxiliary storage means; a plurality of external storage devices connected to a shared external storage device and all the system buses, and a plurality of external storage device connection means operating in an instructed operation mode. Operation mode switching method. 2. The operation mode switching system for a multiplexed computer according to claim 1, further comprising configuration control means for issuing an instruction to switch to either the synchronous operation mode or the parallel operation mode. Operation mode switching method in. 3. The operation mode switching system for a multiplexed computer according to claim 2, wherein a signal line for connecting all the external storage device connecting means is provided, and each external storage device connecting means is one of the systems. An operation mode switching system in a multiplex computer, which notifies each other via the signal line that a bus has been secured. 4. A plurality of Cs for a plurality of system buses, respectively.
In a multiplexed computer that is capable of operating in both synchronous and parallel operation modes by connecting a PU and a main storage device, an operation that is connected to any CPU and all the system buses and that is preset for each transaction A plurality of auxiliary storage devices operating in a mode, a plurality of external storage devices connected to a shared external storage device and all the system buses, and operating in a preset operation mode for each transaction. Operation mode switching method in a multiplex computer. 5. The operation mode switching method for a multiplexed computer according to claim 4, wherein the auxiliary storage means has an operation mode storage unit for storing an operation mode of a transaction to be processed. Operation mode switching method. 6. The operation mode switching method for a multiplexed computer according to claim 4, wherein the external storage device connection means has an operation mode storage unit for storing an operation mode of a transaction to be processed. Operation mode switching method in a computer.