JP3440508B2 - Image data conversion device and digital image recording device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data conversion apparatus having a function of shuffling or deshuffling image data, and a digital image recording apparatus equipped with such an image data conversion apparatus.

[0002]

2. Description of the Related Art Generally, in a digital image recording apparatus, for example, a digital VTR, shuffling is performed at the time of recording in order to disperse an error portion appearing at the time of reproduction and improve error correction capability. Is a function for improving the image compression efficiency by reducing the variation of the quantization step in the quantization after the DCT conversion in the recording system in the image compression recording system digital VTR which performs the image compression by the DCT conversion and records. It is also adopted as an important signal processing because it has

Such image compression recording type digital VTR
Shuffling and deshuffling operations (hereinafter referred to as a digital VTR) will be described based on the signal processing block circuit of the recording system and the reproducing system shown in FIG.

In this figure, in the recording system, Y, R
The input component video signal composed of each of the -Y and BY signals is first supplied to the AD converters 1 to 3, where the sampling frequency is 13.5 MH for the Y signal.
For the z and color difference signals, AD conversion is performed with a sampling frequency of 1/4 thereof. Next, these Y, RY, B-
Each effective area from the AD conversion output of the Y signal (for example, in the NTSC system, 23H in an odd field)
To 262H of 240 lines and 285H to 524H of 240 lines in the even field, the effective scanning period of each line) (hereinafter, these data are referred to as D
Y, DR, and DB) are extracted and supplied to the circuit 4 for blocking and shuffling.

In this circuit, the effective area data DY, DR and DB are blocked and shuffled for each field. That is, (1) in FIG.
720 samples in the horizontal direction, DY for one field composed of 240 lines in the vertical direction, and 180 samples in the horizontal direction and 2 in the vertical direction shown in (2) of FIG.
DR and DB for 1 field consisting of 40 lines
With respect to the above, one block is divided into 8 samples in the horizontal direction and 4 samples in the vertical direction (a block composed of 8 samples in the horizontal direction and 4 samples in the vertical direction is referred to as a DCT block).

Thus, for DY, the horizontal direction 9
A total of 5400 DCT blocks of 0, 60 in the vertical direction, and 22.5 DCT blocks in the horizontal direction of DR and DB, 60 in the vertical direction, 1350 in total are obtained. The signal thus blocked is shuffled in order to improve the compression efficiency of image data and to disperse an error portion during reproduction as described above.

Next, a concrete mode of the shuffling is shown in FIG.
Will be explained. This figure shows the data for one field of DY, DR, or DB described above, and the vertical and horizontal directions in this figure respectively correspond to the vertical and horizontal directions of the actual one-field screen. Then, as shown in the figure, the data for one field is divided into five areas A in the horizontal direction.
To F, and the area divided into 5 is further divided into 10 sub-areas in the vertical direction to obtain 50 sub-areas A0-A9, B0-B9, F0-F9, D0. D9,
E0 to E9 are formed.

Regarding the shuffling operation performed by dividing the data for one screen in this way, first, the case of DR will be described. In the case of DR, the whole one screen is composed of 1350 DCT blocks, so each of the above sub-areas is composed of 27 DCT blocks (however,
In the right end portion of the screen, only half of the DCT blocks are formed, so it is assumed that upper and lower adjacent blocks are combined to form one DCT block).

Here, 2 included in one sub-area
The seven DCT blocks are represented by adding i-j to the lowercase letters of the alphabet of the subarea (where i = 0, 1,
2, ..., 9, j = 1, 2, ..., 27). For reference, the first DCT block and the 27th DCT block in each sub-area of A0, B0, F0, D0, and E0 are simplified and shown in each sub-area. Then, the shuffling is executed by reading out and recording the DCT blocks that compose the data for one field in the order shown in the lower part of the figure.

That is, according to the order of F, B, D, A, E, first, the first DCT blocks f0-1, b0-1, d0 of each of the sub-areas F0, B0, D0, A0, E0.
Read -1, a0-1, and e0-1. Next, the second DCT block f0-2, b0- of these sub-areas
2, d0-2, a0-2, e0-2 are read, and further
When the reading of the third and subsequent DCT blocks is sequentially advanced and the reading of the 27th DCT block is completed, next, the sub-areas F1, B1, D1, A1, E
Similarly, the reading of the DCT block of 1 is executed. Then, by repeating these operations, the sub-areas F9, B9,
By ending the reading up to the 27th DCT block of D9, A9, and E9, the reading of all DRs for one field is completed.

In the shuffling operation of the DB, the DC of the DB for one field is also in the same order as in the DR.
Reading of the T block is executed. Further, in the shuffling operation of DY, DY has four times as much data amount as DR and each DY sub-area has four times as much DC as DR.
Since T blocks are included, reading DCT blocks from each subarea of DY requires four DCs at a time.
Read out the T block. That is, in this case, f0-1, b0-1, d0- read in FIG.
1, etc. are all composed of four DCT blocks.

The above shuffling operations for DY, DR, and DB are simultaneously performed in parallel, and these shuffling outputs are input to the next buffering memory 5.
In the memory 5, the data of the first field and the data of the second field are combined to form data for one frame in the non-interlaced format.
Specifically, for each of DY, DR, and DB, the DCT block of the first field and the DCT block of the second field corresponding to the same screen position are interpolated to obtain a DCT of 8 samples in the horizontal direction and 8 samples in the vertical direction. A block is formed.

The DCT block of 8 samples × 8 samples is composed of four DCT blocks of DY shown in (3) of FIG. 17 and one DCT block of each of DR and DB, which is a total of six DCT blocks. (This is called a macroblock, and each DCT block of DY, DR, and DB corresponds to the same position on the screen) is converted into time series data, and compression encoded from the buffering memory 5. Input to the circuit 6. Then, after being subjected to DCT conversion, quantization, Huffman coding, and other processing in the compression coding circuit 6 to compress the data, it passes through a recording modulation circuit 7, a recording amplifier, etc., and a recording head in the form of a predetermined recording code. And recorded on tape.

In the processing of the reproduction system, the data reproduced by the head is input to the image compression / decoding circuit 13 via the reproduction amplifier, the demodulation circuit 14, etc., and the data decoded here is interlaced in the buffering memory 12. After being converted into a signal, it is supplied to the circuit 11 for de-shuffling and de-blocking. This circuit 11
The signal returned to the normal television scanning format in the above is supplied to the DA converters 8 to 10, and the original Y signal and R signal are supplied.
The -Y signal and the BY signal are taken out.

In the digital VTR having the recording / reproducing system as described above, the circuit 4 for blocking and shuffling is conventionally constructed as shown in FIG.
Explaining this circuit, the inputs DY, DR, and DB are respectively a pair of field memories 27, 28, 29, and 3.
0, 31, 32, and these field memories are controlled in operation by a write controller and a read controller consisting of 33, 34 or 35, 36.

FIG. 20 shows the write / read operation in each of the pair of field memories in the case of DY. As shown here, while writing the input data for one field into one of the field memories,
Data for one field is read from the other field memory in the order described with reference to FIG.

Next, the write / read operation in each field memory of FIG. 19 will be described in detail. Figure 2
1 shows the relationship between the write address and the read address in one field memory. In this figure, an input video signal for one field from 23H to 262H (this signal is one of DY, DR, and DB) is equally divided into 10 sections from 0 to 9 and shown in the upper left. There is. Correspondingly, the address space from the start address to the end address of the area for storing one field of data in the field memory is equally divided into ten areas M0 to M9.

Here, the section n (n = 0,
The data of 1, 2, ..., 9) are configured to be stored in the area Mn of the field memory, and this relationship is represented by the hatched line α in the figure. On the other hand, regarding the read address for extracting the shuffling output, the shuffling output for one field is set to 1 as shown in the lower right of this figure.
If it is equally divided into 0 sections S0 to S9, the signal in the section S0 reads out the signals in the sub-areas F0, B0, D0, A0, and E0 in FIG. 18, as is apparent from FIG.

As can be seen from the correspondence between the sub-areas in FIG. 18 and the memory addresses in FIG. 21, the signal in sub-area F0 has the address in area M2 and the signal in B0 has the address in area M6. , The signal of D0 has an address in the area M8, the signal of A0 has an address in the area M0, and the signal of E0 has an address in the area M4. In order to take out, the data of the addresses in the areas M2, M6, M8, M0 and M4 are read, and the read address exists in the halftone dot area shown in the upper part of the section S0 in FIG. Similarly, the read addresses of the signals in the section S1 are present in the areas M3, M7, M9, M1 and M5, and hereinafter, the read addresses of the signals of S2 to S9 are also in the halftone dot area shown in FIG. Exists in.

Field memories A and B for DY
22 is a timing chart showing the relationship between the write and read addresses in FIG. As shown in this figure, input video signal field 1, field 2, ...
.. are written alternately in the memories A and B for each field according to the write characteristic .alpha., And the data of the address in the halftone dot area is read from these memories alternately for each field, and shuffling output .. are extracted (hereinafter, in this specification, the shuffling output of the field N of the input video signal is referred to as field [N]).

The de shuffling and de shuffling of the reproduction system
The circuit 11 for blocking is configured so that the shuffling form DCT block data strings of DY, DR, and DB from the buffering memory 12 are input to a pair of field memories in the same manner as the circuit 4 described above. , In this case, D for one field written sequentially
The operation of reading the CT block data is performed in the order in which the output signal of the normal television scanning format is obtained.

[0022]

As described above, in the conventional device for digitizing and recording or reproducing the video signal, in the processing circuit for shuffling or deshuffling, It uses a pair of field memories for each input signal to be processed,
Therefore, a large amount of memory capacity is required for the entire system. This is a big problem in realizing the downsizing and cost reduction of the device.

[0023]

According to the present invention, there is provided a memory for storing image data for one screen or for one screen or more, a write control means for controlling an operation of writing image data to the memory, and a memory for controlling the operation. Read control means for controlling the read operation of the image data, and corresponding to each of a plurality of sections formed by dividing one screen from the memory in which the image data for one screen is written. In the image data conversion device in which the image data converted into a predetermined pattern by taking out the image data to be read out in the predetermined order by the read-out control means is taken out, one screen is equally divided and M ×
While forming Q sections, the memory has M × Q storage areas for storing one section of image data, and further corresponds to a section at a predetermined position on the N-th screen of the input image data. The storage area in which the image data is written is P × (N) with respect to the storage area in which the image data of the predetermined section in the first screen of the input image data is written.
-1) A storage area shifted by mod M (where P is a constant determined according to the section of the predetermined position), and the writing control means completes reading of one screen of image data by the reading control means. Before that, the operation of writing the image data of one section in the image data forming the next one screen to the storage area of the image data of one section for which the read operation is executed by the read control means is executed. It is characterized by

In this case, one screen is equally divided to form M × Q sections, and the memory has M × Q storage areas for storing image data for one section. The storage area in which the image data corresponding to the section at the predetermined position on the N-th screen of the input image data is written is the storage area in which the image data of the predetermined section on the first screen of the input image data is written. On the other hand, by configuring the read control means and the write control means so that the storage area is shifted by P × (N−1) modM (where P is a constant determined according to the predetermined partition), The image data converted into the pattern can be taken out.

In addition to this, of the storage areas in which the image data of the next screen can be written by the execution of the read operation by the read control means, the next 1 is stored in the storage area in which the read operation is performed earliest. The writing control means may be configured so that the image data for one section on the screen is written. Further, by making the memory storage capacity larger than the image data for one screen, it is possible to give a margin to the writing / reading operation.

Further, according to the present invention, an image signal A is input.
A digital circuit including an A / D conversion circuit, a shuffling circuit to which an output signal of the A / D conversion circuit is input, and a signal processing circuit to which an output signal of the shuffling circuit is input and which outputs a recording code. In the image recording apparatus, the shuffling circuit controls a memory that stores image data for one screen, a write control unit that controls writing of the image data to the memory, and a control of reading image data from the memory. And a read control unit to divide the one screen equally to form M × Q sections, and the memory has M × Q storage areas for storing image data for one section. The storage area in which the image data corresponding to the section at the predetermined position on the N-th screen of the input image data is written is the predetermined area on the first screen of the input image data. P × (N−1) modM (where P
Is a storage area shifted by a constant determined according to the section of the predetermined position, and shuffled by reading from the memory in which the image data for one screen is written in a predetermined order by the read control means. And outputting the image data, and the writing control means outputs the image for one section for which the reading operation is performed by the reading control means before the reading control means finishes reading the image data for one screen. It is characterized in that the operation of writing the image data of one section in the image data forming the next one screen to the data storage area is executed.

[0027]

In one image memory, the operation of writing the image data of the next screen is executed while the image data of one screen is being read for shuffling or de-shuffling. The odd field of the shuffling output and the subsequent even field are output without a gap.

[0028]

FIG. 23 shows the basic configuration of a circuit for shuffling or de-shuffling according to the present invention. The present invention enables shuffling or deshuffling by using only one field memory as shown in this figure by devising control of write address and read address of the field memory. The memory used can be halved.

An embodiment in which the above basic structure is applied to a shuffling circuit will be described first with reference to the timing charts of FIGS. 1 and 2. In FIG. 1, an input video signal of field 1 to field 3 is shown in the upper part, and a field [1] and a field [2] which are shuffling outputs of the field 1 and the field 2 are shown in the lower part. Further, an address space of the field memory is provided on the left side, an address area A for storing the data of the area A in FIG. 18 of the input video signal, an address area B for storing the data of the area B, and an address for storing the data of the area F. An area F, an address area D for storing the data of the area D, and an address area E for storing the data of the area E are divided into five areas, and each area is divided into 10 areas 0 to 9 and shown. There is. The areas from 0 to 9 are called sub areas, and each becomes an address area for storing data for one sub area in FIG.

Further, in this figure, there are shown 50 sub-regions of the memory and a large number of sections subdivided into a rectangular shape by broken lines or solid lines in accordance with sections 0 to 9 of each field of the input video signal. However, in these sections, the sections in which numbers are entered indicate that the data for one subarea in the area in the input video signal section is stored at the address of the subarea, The numbers entered in this section represent the sub-area numbers of the data stored in this sub-area (the numbers written in each sub-area in FIG. 18).

For example, in the section 0 of the field 1 of the input video signal, the sub area 0 of the address area A is shown in FIG.
Data of sub area A0 of
Of sub-area B4, data of sub-area F8 of sub-area 0 of address area F, data of sub-area D2 of sub-area 0 of address area D, sub-area 0 of sub-area 0 of The data in the sub area E6 is stored. That is, the data included in the input video signal of the field 1 is stored in each address area in the order of the data in each area as shown in FIG.

Further, in this figure, in the section in which the letter "R" is entered, the data stored in the sub-area of this section is read in order to obtain the shuffling output in the signal section of this section. It means that.

For example, when the input video signal is DR, in the period between the section 9 of field 1 and the section 0 of field 2, the sub area 2 of the address area F is displayed.
Data of sub-area F0 stored in sub-area F0, data of sub-area B0 stored in sub-area 6 of address area B, data of sub-area D0 stored in sub-area 8 of address area D, address area A One DCT block is read from each data in the order of the data of the sub-area A0 stored in the sub-area 0 and the data of the sub-area E0 stored in the sub-area 4 of the address area E. Then, by repeating this read operation 27 times, the signal of the section 0 of the field [1] which is the shuffling output is taken out.

Then, in the next section, that is, in the section 0 of the field 2, the input video signal data of this section is stored in each sub-area in which the above-mentioned read operation is performed, and at the same time, in this section. A read operation for extracting the signal of the section 1 of the field [1] which is the shuffling output is also executed.

As described above, in the sub-region of the field memory of this embodiment, when the data for one sub-area is read in one section, the input video signal of the next field is immediately obtained in the next section. The storage operation of the data for one sub area is executed. As a result, the shuffling can be performed without overtaking between the write operation and the read operation even by using only one field memory.

In FIG. 2, the writing / reading operation for the input video signal from field 4 to field 6 following the input video signal up to field 3 shown in FIG. 1 and the field [shuffling output]. 3] to [5] are shown.

As is apparent from the above description, in the present embodiment, the write address for data other than the area A is shifted to a different address for each field, and the address for writing individual data is always fixed. It is significantly different from the conventional shuffling circuit used.

Therefore, in this embodiment, a different write address must be set for each field. Regarding this point, referring to the write address of the input video signal in the field 6 in FIG. The write address is completely the same as the write address of the input video signal in field 1 of FIG. That is, since the write address change pattern in this embodiment has a cycle of 5 fields, a device capable of designating addresses for 5 fields may be used as the write address control device.

The periodicity can be explained as follows. That is, the sub-region of the data written in the address region E is displaced to the sub-region whose number is 4 larger than that of the field immediately before. Therefore, the sub-area in which the data of the field N is written is 4 × (N−1) mod with respect to the sub-area in which the data of the field 1 is written.
It will be displaced by 10. Similarly, for writing data to the address area D, 8 × (N−1) m
od10, 2 × (N−1) mod10 for writing data to the address area F, and 6 × (N−1) mod10 for writing data to the address area B when the sub-area is field 1 It will be displaced compared to. Since the minimum value of N at which all of these displacements are 0 is 6, it coincides with the writing sub-region of the field 1 in the 6th field.

The above is the digital VT for the NTSC system.
Regarding shuffling in R, PAL
In the digital VTR of the system, the effective video data of the Y signal for one field is composed of 720 samples in the horizontal direction and 288 lines in the vertical direction as shown in FIG. The shuffling pattern is evenly divided into areas A, B, F, D, and E in the horizontal direction and is equally divided into 12 sub-areas in the vertical direction. The amount of data per sub-area is N
It is set to be equal to the case of the TSC system.

One embodiment of the write / read pattern of the field memory according to the present invention for realizing the shuffling in the PAL system is shown in FIGS. In this figure, the field memory is equally divided into areas A to F, and each area is further equally divided into 12 sub areas.
Also, each field of the input video signal is 1 from 0 to 11.
Fields [1] and [fields], which are shuffled outputs, are equally divided into two sections, and the respective data of areas A to F in FIG. 3 included in each section are written and read in the respective sub areas described above. 2], ... Are taken out.

In the writing / reading pattern shown in this figure, when the displacement amount of the sub-region in which the data is written in each of the regions A to F is obtained in the same manner as in the case of the NTSC system, 4 × (N-1) is obtained for the region E. ) Mod12, 8 × (N−1) mod12 for region D, 2 × (N−1) mod12 for region F, 6 × for region B
It is represented by (N-1) mod12. Since the minimum number of N for which all of these displacement amounts are 0 is 7, it can be seen that the change in the write address has the periodicity of 6 fields.

In the embodiments relating to the NTSC system and the PAL system described above, there is always a gap (no signal period) between adjacent fields of the shuffling output. In order to extract a continuous one-frame shuffling output in which there is no gap between the odd field and the even field, unlike the output, in the case of the NTSC system, the write / read pattern of the field memory is shown in FIG. ~ It may be done as shown in FIG.

In the write / read pattern shown here, the timing of writing an odd field signal and then reading the written signal is shown in FIGS. 1 and 2.
By delaying by one section as compared with the case of 1, the rear end of the shuffled output of the odd field signal is in contact with the front end of the shuffled output of the even field signal. Further, in order to prevent the signal of the next field from being unable to be written due to the delay of the read timing in this way, the number of sub-regions in each of the regions A to F of the memory is increased by two, and each sub-region is increased to twelve. The storage capacity is increased so as to have the sub-region (the field memory for PAL described above can be used as such a field memory).

In this writing / reading pattern, the signals from section 0 of field 1 to section 1 of field 2 are sequentially written to sub-areas in which no data has been written yet. For the subsequent signals, write control is performed so that writing is performed to the earliest read sub-region among the sub-regions that have already been read and can be written. By selecting the sub area in which the input video signal is to be written in this way, it is possible to lengthen the time interval from the reading of data in each sub area to the writing of the next data. It is possible to give a margin to the read / write operation of the field memory.

In this writing / reading pattern, the write address of the input video signal in field 7 is exactly the same as the write address in field 1, and the write address has a periodicity of 6 fields. FIG. 10 shows an example of another write / read pattern for extracting the shuffling output in which there is no gap between the odd field and the even field. This figure shows sub-regions 0 and 1 in regions AF of FIGS.
7 shows a write / read pattern for the first three fields when sub-regions 2 and 3 are replaced, and the shuffling output similar to that in FIG. 7 is obtained.

In addition to this example, the same shuffling output can be obtained even if the sub-regions 0 and 1 in FIGS. 7 to 9 are replaced with any two sub-regions other than the sub-regions 2 and 3. It is obvious that various embodiments can be constructed by thus providing the storage capacities of the respective areas A to F with the margins of two sub-areas.

Further, in the PAL system as well, in order to extract the shuffling output in which there is no gap at the boundary between the odd field and the even field, the write / read pattern may be as shown in FIGS. 11 to 13. . In these figures, the shuffling is performed by advancing the timing of reading the odd field signal written in the memory by one section and the timing of reading the even field signal by two sections as compared with the case of FIGS. 4 to 6. There is no gap between the odd and even fields in the output.

Also in this writing / reading pattern, the selection of the sub-area in which the signal in each section after the field 2 is written is the same as in the case of FIG. 7 to FIG. The writing operation is controlled so that the writing is performed to the sub-region in which the reading is performed earliest. Also in this write / read pattern, the write address of field 7 matches the write address of field 1, and the periodicity of the write address is 6 fields.

Next, an embodiment in which the present invention is applied to a deshuffling circuit will be described. Write / deshuffle for the shuffling output of the NTSC system extracted by the write / read operation of FIGS. 1 and 2.
The read pattern is shown in FIG. This figure shows the first three
The writing / reading pattern for the fields is shown. In each area A to F of the field memory, the data up to the sub area 9 is written in order starting from the data in the sub area 0 of the input signal, and the reading is performed. It is performed according to the order of the sub areas of each area shown in FIG.

In this figure, when the displacement amount of the sub-region in which the data is written is calculated, 6 × (N−
1) mod10, 2 × (N-1) mod for area D
d10, 8 × (N−1) mod10 for the region F,
Since the area B has 4 × (N−1) mod10, the write address cycle is the same 5 fields as in the case of FIGS. 1 and 2.

Further, FIG. 15 shows a write / read pattern for de-shuffling the shuffling output of the PAL system extracted by the write / read operation of FIGS. This figure shows a write and read pattern for the first two fields, and the displacement amount of the sub region in which the data is written is 8 × for the region E.
For (N-1) mod12 and area D, 4 * (N-
1) mod 12, 10 × (N−1) m for area F
mod12, 6 × (N−1) mod12 for area B
Therefore, the write address cycle is as shown in FIGS.
The same 6 fields as in the case of.

The various shufflings and de-shufflings have been described above, but these are merely examples of the present invention, and the invention is not limited to these and within the scope of the present invention. Various shuffling and de shuffling configurations can be adopted.

[0054]

The shuffling and the deshuffling of the image data can be executed by using only one field memory, and the miniaturization of the device and the reduction of the manufacturing cost can be realized.

[Brief description of drawings]

FIG. 1 is field 1 of field memory in an embodiment for performing shuffling of NTSC signals according to the present invention.
FIG. 6 is a diagram for explaining write / read operations in FIG.

FIG. 2 is a diagram for explaining write / read operations in fields 4 to 6 in the same embodiment.

FIG. 3 is a diagram illustrating a shuffling pattern of a PAL signal.

FIG. 4 is a diagram for explaining write / read operations in fields 1 and 2 of a field memory in an embodiment for performing shuffling of a PAL signal according to the present invention.

FIG. 5 is a diagram for explaining a write / read operation in fields 3 and 4 in the embodiment.

FIG. 6 is a diagram explaining a write / read operation in fields 5 to 7 in the embodiment.

FIG. 7 shows a write / read operation in fields 1 to 3 in an embodiment in which, in shuffling of an NTSC signal according to the present invention, no gap is created between an odd field of a shuffling output and an even field following it. It is a figure explaining.

FIG. 8 is a diagram for explaining write / read operations in fields 4 and 5 in the embodiment.

FIG. 9 is a diagram for explaining write / read operations in fields 6 and 7 in the same Example;

FIG. 10: In the shuffling of an NTSC signal according to the present invention, writing and reading in fields 1 to 3 in another embodiment in which a gap is not generated between an odd field and a subsequent even field of the shuffling output. It is a figure explaining operation.

FIG. 11 shows a write / read operation in fields 1 and 2 in an embodiment in which, in the shuffling of a PAL signal according to the present invention, a gap is not created between an odd field of a shuffling output and an even field following the shuffle output. It is a figure explaining.

FIG. 12 is a diagram for explaining write / read operations in fields 3 and 4 in the same Example;

FIG. 13 is a diagram for explaining write / read operations in fields 5 to 7 in the same embodiment.

FIG. 14 is a diagram for explaining the write / read operation of the field memory in the embodiment for deshuffling the NTSC signal according to the present invention.

FIG. 15 is a diagram for explaining the write / read operation of the field memory in the embodiment for deshuffling the PAL signal according to the present invention.

FIG. 16 is a digital VT to which an embodiment of the present invention is applied.
It is a block diagram which shows the structure of the signal processing circuit of R.

FIG. 17 is a diagram illustrating a blocking pattern and a macro block.

FIG. 18 is a diagram illustrating a shuffling pattern.

FIG. 19 is a diagram showing a specific configuration of a conventional shuffling circuit.

FIG. 20 is a diagram illustrating a write / read operation in a conventional shuffling circuit.

FIG. 21 is a diagram explaining a write / read operation in one field memory in the conventional shuffling circuit.

FIG. 22 is a diagram illustrating a write / read operation in a pair of field memories in a conventional shuffling circuit.

FIG. 23 shows a shuffling circuit or a de shuffling circuit according to the present invention.
It is a figure which shows the basic composition of a shuffling circuit.

[Explanation of symbols]

16 ... Field memory, 22 ... Write control device,
23 ... Read-out control device,

Claims (4)

(57) [Claims] (1) (1) One screenOr more than one screenof
A memory for storing image data, (2) Control the operation of writing image data to the memory
Write control means, (3) Control the operation of reading image data from the memory
Read control means for And the image data for one screen has been written.Up
RecordFormed by dividing one screen from memory
Image data corresponding to each of a plurality of sections is
Read control means to read in a predetermined order
Take out the image data that has been converted into a more specific pattern
In the image data conversion device,Forming M × Q sections by dividing one screen equally
In addition, the memory stores the image data for one section.
It has M × Q storage areas, and the input image data
The image data corresponding to the section at the predetermined position on the Nth screen
The storage area in which the data is written is 1 of the input image data.
The image data of the specified section on the second screen is written
P × (N−1) modM (however,
However, P is only a constant determined according to the section at the above-mentioned predetermined position)
The shifted storage area, The write control means is based on the read control means.
Before the reading of the image data for one screen is completed,
The read operation was performed by the read control means 1
Configure the next one screen in the storage area of image data for a section
A motion to write image data for one section of image data
Image data transformation characterized by the fact that
Exchange device. 2. A section of the next one screen in a storage area in which the read operation is performed earliest among the storage areas in which the image data of the next screen can be written by executing the read operation by the read control means. 2. The image data conversion device according to claim 1, wherein minute image data is written. 3. The image data conversion device according to claim 1, wherein the storage capacity of the memory is larger than the image data for one screen and smaller than the image data for two screens. 4. (1) A / D conversion to which an image signal is input
Circuit, (2) A shuff to which the output signal of the A / D conversion circuit is input
A ring circuit, (3) When the output signal of the shuffling circuit is input,
A signal processing circuit for outputting a recording code to the
In the tar image recording device, The shuffling circuit stores image data for one screen
Memory and the writing of image data to the memory
Write control means and image data from the memory
Read control means for controlling the read ofBy dividing the one screen into equal parts, M × Q sections are formed.
The memory stores image data for one section
It has M × Q storage areas to store the input image data.
Image corresponding to the section at the specified position on the N-th screen
The storage area where the image data is written is the input image data.
The image data of the specified section on the first screen of
P × (N−1) modM for the storage area
(However, P is a constant determined according to the section at the above-mentioned predetermined position)
It is a storage area shifted only by From the memory in which the image data for one screen is written,
The read control means may read in a predetermined order.
Output the image data shuffled by Moreover, the write control means is the read control means.
Before reading one screen of image data by
Read operation is executed by the read control means.
The next one screen is created in the storage area of the image data for one section.
Write the image data for one section of the image data to be created
Digit characterized by performing an action
Tal image recording device.