JP3435869B2 - Pulse width measuring device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for demodulating a pulse width modulated signal. 2. Description of the Related Art A conventional pulse width measuring apparatus is shown in FIG. 3 (Japanese Patent Laid-Open No. 1-277768). In the figure, 1 is a counter for counting the pulse width, 2 is a register for holding the count value of the counter, and 3 is a circuit for detecting an edge of the input pulse. Now, if the high (hereinafter, H) state of the width modulation input pulse (hereinafter, referred to as input pulse) is made valid, the counter 1 counts while the input is H. The edge detection circuit 3 detects the falling edge of the input pulse and clears the counter 1. The register 2 is loaded with a count value immediately before the counter 1 is cleared, and its output is read by an external circuit (not shown) as necessary. However, in the prior art, if the input pulse edge cannot be detected, the state of the input is not reflected on the output of the register. FIG. 4 shows such a state. However, when the duty of the input pulse becomes 0% or 100% or more, those states do not appear in the output of the register, and the previous value is retained. become. Even if the input pulse duty is 0% or 100%
However, if it is very close to this, the edge detection may fail depending on the configuration method of the edge detection circuit, and the same result is obtained. This problem becomes remarkable especially when synchronization is not established between the measured system and the measurement system. Therefore,
The present invention provides a means for obtaining an approximate value corresponding to the state of an input pulse from a register within a predetermined time even if the duty of the input pulse becomes 0% or 100% or more, and even if an edge cannot be detected. The purpose is to provide. [0004] In order to solve the above-mentioned problems, the present invention measures the pulse width of an input pulse.
Is cleared at the falling edge of the input pulse and reaches the maximum value.
Counter that stops counting up if possible and time limit
Is equal to or slightly larger than the pulse cycle time of the input pulse.
Threshold value and the rise of the input pulse
Initialized by a falling edge or a falling edge,
If the next edge is not detected within the time limit,
A timed timer for outputting an out signal, and a counter for the counter.
When the timeout signal is generated.
If the input pulse is L, it is cleared, and if it is H,
A preset register is provided, and if no rising or falling edge is detected within a predetermined time, the register is cleared or preset according to an input binary signal. According to the above means, if the input is low (hereinafter referred to as L) for a predetermined time or more, the duty is regarded as 0%,
If the input is H for a certain time or more, the duty is 1
Therefore, even if the duty of the input pulse becomes 0% or 100% or more, even if the edge cannot be detected, an approximate value corresponding to the state of the input pulse can be determined within a predetermined time. Obtained from a register. An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In FIG. 1, 1 is a counter for counting the pulse width, and 2 is a register holding the count value of the counter 1 and having a clear and preset function. Reference numeral 3 denotes an edge detection circuit for detecting the rising and falling edges of the input pulse. 4 is a timed timer. The counter 1 counts up while the input pulse A is at H, and is cleared by the falling edge signal D. Also, counting up is stopped at the maximum value to prevent overflow.
The count value B is loaded into the register 2 immediately before the counter 1 is cleared. The time limit L of the time timer 4 is set to a value equal to or slightly larger than the pulse cycle time K of the input pulse. 5 is an OR circuit. The timed timer 4 is cleared by the timed clear signal F, and generates a timeout signal G if the next edge is not detected within the timed time. Reference numerals 6 and 7 are AND circuits. The register 2 is cleared when the input pulse A is L when the timeout signal G is generated, and is preset when it is H. The register output C is read as required by an external circuit. As described above, according to the present invention, even if the duty of the input pulse becomes 0% or 100% or more,
In addition, even if the edge cannot be detected, an approximate value corresponding to the state of the input pulse can be obtained from the register within a predetermined time.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing an input pulse and a signal of each circuit in the embodiment of the present invention. FIG. 3 is a conventional pulse width measuring apparatus. FIG. 4 shows an input pulse of a conventional pulse width measuring device and a signal of each part of the circuit. [Description of References] 1 Counter 2 Register 3 Edge detection circuit 4 Timed timer 5 OR circuit 6, 7 AND circuit

Claims (1)

(57) In the pulse width measuring unit for demodulating the Patent Claims 1. A pulse width modulated signal, said input pulse with measuring the pulse width of the input pulse
Counted when the signal is cleared at the falling edge of
A counter that stops the up and timed time is the same as the pulse cycle time of the input pulse
Is set to a slightly larger value and the input
Initialized by the rising or falling edge of
When the next edge is not detected within the time limit,
A timed timer for outputting a time-out signal, and holds the count value of the counter, the time-out
If the input pulse is L when a signal is generated,
A pulse width measuring device comprising: a register which is preset when H is set .