JP2609888B2 - Signal transmission system and its equipment - Google Patents

Description

The present invention relates to a signal transmission system and a device therefor, which can improve the transmission speed in an asynchronous serial transmission system, has a simpler circuit configuration than that of performing synchronous transmission, and has a current asynchronous transmission circuit. The purpose of the present invention is to provide a signal transmission method that can be realized by changing the signal level. When the “high” level is held for one bit period, the signal is set to “1”. When the signal level changes from the “low” level to the “low” level, the signal is set to “0” and a “low” level of 1 bit width is always inserted at the end of one transmission unit, and the bit cycle is counted from the rising edge to the falling edge of the signal. The signal is determined by sampling based on the counting result.

[Industrial applications]

The present invention relates to a signal transmission system and an apparatus thereof, and more particularly to a signal transmission system and an apparatus thereof for improving a transmission speed in an asynchronous serial transmission system.

[Conventional technology]

Normally, a coaxial cable is used to realize long-distance signal transmission between a processor (hereinafter referred to as CPU) and a workstation (hereinafter referred to as WS), and synchronous transmission is used for high-speed transmission. Asynchronous transmission is used for high-speed transmission or low-speed transmission.

[Problems to be Solved by the Invention]

Conventionally, for medium- and low-speed transmission, WS is connected in an immodular manner by one coaxial cable, and asynchronous serial transmission is carried out. However, since the signal is asynchronous serial, the signal is pulse width modulated as shown in FIG. 5. To increase the transmission speed, one bit period must be shortened. Then, it is difficult to increase the transmission speed, and conversely, if synchronous transmission is adopted to increase the transmission speed, the circuit becomes complicated and the cost becomes high.

The present invention has been made in view of such a problem, and can improve a transmission speed in an asynchronous serial transmission system, has a simpler circuit configuration than that of performing synchronous transmission, and has a current asynchronous transmission circuit. It is an object of the present invention to provide a signal transmission method and a device that can be realized by changing the number of signals.

[Means for solving the problem]

In the present invention, a means for solving the above-mentioned problem is that a signal transmission method for asynchronously transmitting two states of a "low" level and a "high" level by a coaxial cable during one bit period. When the "high" level is held, the signal is "1". When the duty is 50% during the period, the signal changes from "high" level to "low" level. The signal is "0". This is based on a signal transmission method in which a "low" level with a width of 1 bit is always inserted, the bit period is counted from the rising edge to the falling edge of the signal, and the signal is judged by sampling based on the counting result. Therefore, during 1 bit period,
A signal determination unit that determines a signal “1” when the “high” level is held and a signal “0” when the duty is changed from “high” level to “low” level at a duty of 50% during the cycle; A sampling counter that generates a sampling signal every 3/4 of each bit cycle, and counting starts at the rising edge of the signal,
It is assumed that a signal transmission device including a period counter that is reset at a falling edge of a signal and counts a bit period during the period is used.

[Action]

Generally, in the asynchronous serial transmission system, it is necessary to satisfy the following conditions.

The three values of "1" signal, "0" signal or "no signal" can be distinguished.

A signal can be determined from the first bit of serial data.

Therefore, in the present invention, as shown in FIG. 1, the signal unit and the data string are defined as follows.

FIG. 1 (a) explains the signal unit, and is "low".
When the level is set to the “no signal” state and the “high” level is held for one bit period, the signal is set to “1”. During this period, the duty is 50% and the “high” level is changed to “low”. When the level changes, it is defined as signal "0".

FIG. 1 (b) is for explaining a data string, in which a signal starts from a rising waveform, and a word or a byte 1
It is specified that a 1-bit wide "low" level is always inserted at the delimiter of the transmission unit, and the end of the data string is always assembled with a falling waveform.

The signal in the data string defined in this way is determined as follows.

"0" when the signal at that time is "low" when sampling is performed after about 3/4 cycle has elapsed from the first rise of the signal.
And when it is “high”, it is “1”.

If "1" s continue, one bit period T is counted from the first rise, and sampling is performed after elapse of 3/4 period.

In order to make this determination accurately, it is necessary to guarantee a sampling cycle shift when "1" s are consecutive, so that the falling edge must be input within a range of one word (or one byte). A "low" level with a 1-bit width is always provided at the boundary of one transmission unit such as a word or a byte.

According to such a method, it is possible to shorten the 1-bit cycle of asynchronous serial transmission.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the signal transmission device of the present invention. In FIG. 1, a signal transmission device includes a signal determination unit 1 that determines “0” or “1” of input data based on a sampling signal, a sampling counter 2 that generates a sampling signal every 3/4 of each bit period, Counting starts at the rise of the signal, resets at the fall of the signal,
It is composed of a cycle counter 3 for counting the bit cycle in the meantime. When the signal according to the method of the present invention is input as input data, the signal determination unit 1 makes a determination,
Finally, a determination signal of “0” or “1” is output.

FIG. 3 is a flowchart showing the operation of the above-mentioned device, and FIG. 4 is a waveform diagram showing an example of a method of determining a transmission signal by the device. In both figures, when input data is input, the signal determination section 1 outputs a rising detection signal S1 to the sampling counter 2 and the cycle counter 3. The counters 2 and 3 start counting by the detection signal S1.

First, sampling counter 2 is 3/4 of 1 bit cycle.
At the point in time when counting is performed, a sampling ring signal S2 is output to the signal determination unit 1, and based on the sampling signal S2, the signal determination unit 1 determines “0” or “1” of the input data, and “0” or “1”. Outputs 1 "judgment signal.

If the "1" signal continues, the cycle counter 3 counts one bit cycle, outputs the cycle elapse signal S3 to the sampling counter 2, and the sampling counter 2 counts 3/4 cycle again from that time. After that, the sampling signal S2 is output to the signal determination unit 1.

When the above operation is repeated and the signal judging section 1 detects the falling edge of the data, the signal judging section 1 outputs the falling edge detection signal S4 to the period counter 3
The cycle counter 3 is reset by the detection signal S4. Since the falling detection signal S4 is detected both when "0" is input and when one word (or one byte) ends, the cycle counter 3 starts counting again from the next signal, The deviation of the sampling cycle when "1" continues is prevented.

In conventional pulse width modulation, even if "1" signals are continuous, a pulse interval must be placed between them, which causes data waste and makes the pulse interval unclear when trying to shorten the 1-bit period. Therefore, it is difficult to determine the pulse width, but in the present invention, even in the same asynchronous serial transmission, "0" or "1" is determined by the duty ratios of "high" and "low" levels. Therefore, there is no difficulty caused by the pulse interval, the 1-bit cycle can be easily shortened, and the transmission speed can be improved.

〔The invention's effect〕

As described above, according to the present invention, the transmission speed in the asynchronous serial transmission method can be improved,
It is possible to provide a signal transmission system and a device which are simpler in circuit configuration than synchronous transmission and can be realized by changing the current asynchronous transmission circuit.

[Brief description of the drawings]

FIG. 1 is a signal waveform diagram of the system of the present invention, FIG. 2 is a block diagram of one embodiment of the present invention, FIG. 3 is a flowchart of the operation of the embodiment, FIG. 5 and 5 are signal waveform diagrams in asynchronous serial transmission. 1; signal determination unit, 2; sampling counter, 3; cycle counter, S1; rising detection signal, S2: sampling signal, S3: cycle elapsed signal, S4: falling detection signal.

Claims (2)

(57) [Claims] In a signal transmission system for transmitting two states of a "low" level and a "high" level asynchronously and serially by a coaxial cable, a signal "high" level is maintained for one bit period. Set to 1 "and" Low "from" High "level with 50% duty during the period
When the level changes, the signal is set to “0”, a “low” level with a width of 1 bit is always inserted at the boundary of one transmission unit, and the bit cycle is counted from the rise to the fall of the signal. A signal transmission method characterized in that a signal is determined by sampling based on a signal. 2. A signal transmission system in which two states of "low" level and "high" level are asynchronously transmitted by a coaxial cable, and the "high" level is held for one bit period by a sampling signal. A signal determination unit (1) that determines a signal “0” when a change from a “high” level to a “low” level at a duty of 50% during the cycle is performed as a signal “1”; A sampling counter (2) that generates a sampling signal every 3/4 of the period, and a period counter (3) that starts counting at the rising edge of the signal, is reset at the falling edge of the signal, and counts the bit period in between. A signal transmission device, comprising: