JP3434918B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3434918B2 JP3434918B2 JP28492894A JP28492894A JP3434918B2 JP 3434918 B2 JP3434918 B2 JP 3434918B2 JP 28492894 A JP28492894 A JP 28492894A JP 28492894 A JP28492894 A JP 28492894A JP 3434918 B2 JP3434918 B2 JP 3434918B2
- Authority
- JP
- Japan
- Prior art keywords
- metallized wiring
- semiconductor element
- wiring layer
- insulating substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Description
【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明はコンピュータ等の情報処
理装置に搭載される半導体装置に関し、より詳細には半
導体素子を樹脂でモールドして成る半導体装置に関する
ものである。
【０００２】
【従来の技術】従来、コンピュータ等の情報処理装置に
搭載される半導体装置は図２に示すように枠体11に半導
体素子が固定される金属板12と多数のリード端子13とを
接合させたリードフレームＡを準備し、前記金属板12上
に半導体素子14を接着剤を介して接着固定し、次に前記
半導体素子14の各電極をリード端子13にボンディングワ
イヤ15を介して電気的に接続するとともに金属板12上に
固定された半導体素子14とリード端子13の一部を樹脂で
モールドし被覆体16となすことによって製作されてい
る。
【０００３】かかる従来の半導体装置は、半導体素子14
及びリード端子13の一部を樹脂から成る被覆体16でモー
ルドした後、リード端子13を枠体11より切断分離させ、
各々のリード端子13を電気的に独立させるとともに各リ
ード端子13を外部電気回路に接続することによって内部
の半導体素子14を外部電気回路に電気的に接続する。
【０００４】
【発明が解決しようとする課題】しかしながら、近時、
半導体素子は高密度化、高集積化が急激に進んで電極数
が大幅に増大してきており、これに伴って半導体素子の
各電極を外部電気回路に接続するリード端子も線幅が0.
15mm程度と細く、且つ隣接するリード端子の間隔も0.15
mmと極めて狭いものとなってきた。そのためこの従来の
半導体装置ではリード端子を外部電気回路に接続させる
際、リード端子に外力が印加されると該外力によって容
易に変形し、隣接するリード端子が接触して短絡を発生
したり、リード端子を所定の外部電気回路に正確、且つ
強固に電気的接続することができないという欠点を有し
ていた。
【０００５】そこで上記欠点を解消するために本願出願
人は先に、上面中央部から外周部に向かって扇状に広が
るメタライズ配線層を有する基板とリード端子とを準備
し、基板の中央に半導体素子を接着固定させ、該半導体
素子の各電極をボンディングワイヤを介して基板中央部
に位置するメタライズ配線層の一端に接続させるととも
に基板外周部に位置するメタライズ配線層の他端にリー
ド端子を取着させた半導体装置を提案した（特願平３−
３２４９２５号参照）。
【０００６】かかる半導体装置によればリード端子が扇
状に広がったメタライズ配線層に取着されることからリ
ード端子の線幅及び隣接間隔を広いものとしてリード端
子の変形を有効に防止しつつ隣接するリード端子間の電
気的絶縁を維持することが可能となる。
【０００７】しかしながら、この半導体装置においては
半導体素子の電極とメタライズ配線層とをボンディング
ワイヤを介して電気的に接続しており、半導体素子の電
極数が極めて多いことからの半導体素子の電極をメタラ
イズ配線層に接続するのに長時間を要し、半導体装置の
生産性が悪く製品としての半導体装置を高価とする欠点
を有する。
【０００８】またリード端子はその形状が略同一で、且
つ数が極めて多いことからこれを所定のメタライズ配線
層に正確に取着するには熟練を要し、誤取着を発生し易
く、リード端子を異なるメタライズ配線層に取着してし
まうと半導体素子の電極を所定の外部電気回路に正確に
電気的接続することができないという欠点も有してい
た。
【０００９】
【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は半導体素子が高密度化、高集積化し電極
数が大幅に増大したとしても該各電極を外部電気回路に
正確、且つ確実に電気的接続することができる安価な半
導体装置を提供することにある。
【００１０】
【課題を解決するための手段】本発明の半導体装置は、
透光性材料であるサファイヤから成り、上面中央部より
外周部に向かって扇状に広がって形成された、密着層と
中間金属層と主導体層との３層構造を有する複数個のメ
タライズ配線層を有する絶縁基板と、前記メタライズ配
線層の一端に半田を介して取着された、鉄−ニッケル合
金または鉄−ニッケル−コバルト合金から成るとともに
表面に半田がメッキ法により被着された複数個のリード
端子と、前記メタライズ配線層の他端にフリップチップ
接続により接続された、複数個の電極を有する半導体素
子と、前記メタライズ配線層を有する絶縁基板、半導体
素子及びリード端子の一部を被覆する樹脂部材とから成
ることを特徴とするものである。
【００１１】
【作用】本発明の半導体装置によれば、絶縁基板に設け
たメタライズ配線層に半導体素子の電極をフリップチッ
プ接続により接続することから半導体素子の電極数が多
いとしても全ての電極を一度にメタライズ配線層に電気
的接続することができ、その結果、半導体装置の生産性
が大幅に向上し、製品として半導体装置を安価となすこ
とができる。
【００１２】また本発明の半導体装置によれば、メタラ
イズ配線層を有する絶縁基板を透光性材料で形成したこ
とから、メタライズ配線層に半導体素子の電極をフリッ
プチップ接続させる際、或いはメタライズ配線層にリー
ド端子を取着させる際、メタライズ配線層と半導体素子
の電極及びメタライズ配線層とリード端子とを基板を通
して正確に位置合わせすることができ、その結果、半導
体素子の各電極及びリード端子が所定のメタライズ配線
層に正確に接続取着され、半導体素子の各電極をリード
端子を介して所定の外部電気回路に正確、且つ確実に電
気的接続することが可能となる。
【００１３】
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図１は本発明の半導体装置の一実施例を示し、1 は
電気絶縁性の透光性材料から成る基板、2 はリード端
子、３は半導体素子である。
【００１４】前記絶縁基板１は透光性材料であるサファ
イヤより成り、その上面の中央部から外周部に向かって
扇状に広がる複数個のメタライズ配線層４が被着形成さ
れている。
【００１５】
【００１６】また前記絶縁基板１の上面に被着形成され
ているメタライズ配線層４は後述する半導体素子３の各
電極をリード端子２に接続する作用を為し、メタライズ
配線層４の一端には半導体素子３の各電極がフリップチ
ップ接続により接続され、また他端側にはリード端子２
が取着される。
【００１７】前記メタライズ配線層４はチタンやニッケ
ル−クロム合金、窒化タンタル等から成る密着層と、ニ
ッケル、クロム、パラジウム、ロジウム、白金等から成
る中間金属層と、銅、金等から成る主導体層の３層構造
を有しており、絶縁基板１の上面に上記各材料を順次、
スパッタリング法や蒸着法、イオンプレーティング法に
より被着させるとともにこれをフォトリソグラフィー技
術により所定のパターンに加工することによって絶縁基
板１の上面に中央部から外周部に向かって扇状に広がる
ように被着形成される。
【００１８】前記メタライズ配線層４はその絶縁基板１
の中央部に位置する部位に半導体素子３の電極がフリッ
プチップ接続、具体的には絶縁基板１の上面に半導体素
子３を、該絶縁基板１の上面に被着させたメタライズ配
線層４と半導体素子３の各電極に予め被着させた半田バ
ンプとが相対向するようにして載置させ、しかる後、前
記半田バンプを加熱溶融させ、絶縁基板１のメタライズ
配線層４と半導体素子３の各電極とを半田接合させるこ
とによって半導体素子３は絶縁基板１の上面に各電極を
メタライズ配線層４に電気的接続させた状態で取着され
る。この場合、半導体素子３の電極はその総数が多かっ
たとしても全てを絶縁基板１の表面に被着されているメ
タライズ配線層４に半田を介して一度に、且つ強固に電
気的接続することができ、その結果、半導体素子３の各
電極とメタライズ配線層４との電気的接続を極めて短時
間として半導体装置の生産性を大きく向上させることが
できる。また絶縁基板１の上面に被着させたメタライズ
配線層４に半導体素子３の電極をフリップチップ接続に
より接続させる際、絶縁基板１が透光性材料より成るこ
とから絶縁基板１の下面側からメタライズ配線層４と半
導体素子３の電極との相対向状態を確認することがで
き、その結果、半導体素子３の各電極は所定のメタライ
ズ配線層４に簡単、且つ正確に接続することが可能とな
る。
【００１９】また前記メタライズ配線層４はその絶縁基
板１の外周部に位置する部位にリード端子２が取着され
ており、該リード端子２は半導体素子３の各電極を外部
電気回路に接続する作用を為す。
【００２０】前記メタライズ配線層４へのリード端子２
の取着はメタライズ配線層４の上部に半田を介してリー
ド端子２を載置し、しかる後、前記半田を加熱溶融させ
ることによって行なわれる。この場合、絶縁基板１が透
光性材料より成ることから絶縁基板１の下面側からメタ
ライズ配線層４とリード端子２との位置合わせを確認す
ることができ、その結果、メタライズ配線層４に所定の
リード端子２を簡単、且つ正確に取着することができ
る。
【００２１】更に前記リード端子２は該リード端子２の
取着されるメタライズ配線層４が絶縁基体１の上面中央
部より外周部に向かって扇状に広がっており、絶縁基板
１の外周部における線幅及び隣接するメタライズ配線層
４間の間隔が広いものとなっていることからその線幅を
0.25mmと広く（従来品に対し約70%広い）、且つ隣接間
隔を0.25mmと広い（従来品に対し約70%広い）ものとな
すことができ、その結果、リード端子２に外部電気回路
に接続させる際等において外力が印加されたとしても該
リード端子２は大きな変形を発生することがなく、隣接
するリード端子２間の電気的絶縁を維持しつつリード端
子２を所定の外部電気回路に正確、且つ強固に電気的接
続することが可能となる。
【００２２】尚、前記メタライズ配線層４に取着される
リード端子２は鉄−ニッケル−コバルト合金や鉄−ニッ
ケル合金の金属材料から成り、例えば、鉄−ニッケル−
コバルト合金等のインゴット（塊）を圧延加工法や打ち
抜き加工法等、従来周知の金属加工法を採用することに
よって所定の形状に形成される。
【００２３】また前記リード端子２はその表面にニッケ
ル、金等の耐蝕性に優れ、且つロウ材と濡れ性の良い金
属をメッキ法により0.1 乃至20.0μm の厚みに層着させ
ておくとリード端子２の酸化腐食を有効に防止すること
ができるとともにリード端子２とメタライズ配線層４と
の取着及びリード端子２と外部電気回路との接続を良好
となすことができる。従って、前記リード端子２はその
表面にニッケル、金等を0.1 乃至20.0μm の厚みに層着
させておくことが好ましい。
【００２４】更に、前記リード端子２はその表面に半田
をメッキ法により1.0乃至20.0μｍの厚みに被着させて
おり、リード端子２の外部電気回路への接続が容易とな
る。
【００２５】前記上面に半導体素子３及びリード端子２
が取着された絶縁基板１はリード端子２の一部を残して
エポキシ樹脂から成る樹脂部材５でモールドされ、半導
体素子３を外気から完全に遮断することによって最終製
品としての半導体装置となる。
【００２６】前記半導体素子３及びリード端子２の樹脂
部材５によるモールドは、上面に半導体素子３及びリー
ド端子２が取着された絶縁基板１を所定の治具内にセッ
トするとともに治具内にエポキシ樹脂等の液状樹脂を滴
下注入し、しかる後、注入した樹脂を180 ℃程度の温
度、100Kgf/mm 2 の圧力を加え熱硬化させることによっ
て行われる。
【００２７】かくして本発明の半導体装置はリード端子
２を外部電気回路に接続させ、内部の半導体素子３を外
部電気回路に電気的に接続することによってコンピュー
タ等の情報処理装置に搭載されることとなる。
【００２８】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。
【００２９】
【発明の効果】本発明の半導体装置によれば、絶縁基板
に扇状に広がるように設けた複数個のメタライズ配線層
に半導体素子の電極をフリップチップ接続により接続す
るとともに絶縁基板の下面側からメタライズ配線層と半
導体素子の電極との相対向状態を確認することができる
ことから、半導体素子の電極数が多いとしても全ての電
極を一度にメタライズ配線層に電気的接続することがで
き、その結果、半導体装置の生産性が大幅に向上し、製
品として半導体装置を安価となすことができる。
【００３０】また本発明の半導体装置によれば、メタラ
イズ配線層を有する絶縁基板を透光性材料で形成したこ
とから、メタライズ配線層に半導体素子の電極をフリッ
プチップ接続させる際、或いはメタライズ配線層にリー
ド端子を取着させる際、メタライズ配線層と半導体素子
の電極及びメタライズ配線層とリード端子とを基板を通
して正確に位置合わせすることができ、その結果、半導
体素子の各電極及びリード端子が所定のメタライズ配線
層に正確に接続取着され、半導体素子の各電極をリード
端子を介して所定の外部電気回路に正確、且つ確実に電
気的接続することが可能となる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounted on an information processing apparatus such as a computer, and more particularly, to a semiconductor device formed by molding a semiconductor element with a resin. Things. 2. Description of the Related Art Conventionally, as shown in FIG. 2, a semiconductor device mounted on an information processing apparatus such as a computer includes a metal plate 12 having a semiconductor element fixed to a frame 11 and a number of lead terminals 13. A joined lead frame A is prepared, and a semiconductor element 14 is bonded and fixed on the metal plate 12 with an adhesive, and then each electrode of the semiconductor element 14 is electrically connected to a lead terminal 13 via a bonding wire 15. The semiconductor device 14 is fixed to the metal plate 12 and a part of the lead terminal 13 is molded with resin to form a cover 16. [0003] Such a conventional semiconductor device includes a semiconductor element 14.
And after molding a part of the lead terminal 13 with a coating 16 made of resin, the lead terminal 13 is cut and separated from the frame 11,
Each of the lead terminals 13 is electrically independent, and each of the lead terminals 13 is connected to an external electric circuit, thereby electrically connecting the internal semiconductor element 14 to the external electric circuit. [0004] However, recently,
Semiconductor devices have rapidly increased in density and integration, and the number of electrodes has increased significantly.With this, the lead terminals connecting each electrode of the semiconductor device to an external electric circuit have a line width of 0.
It is as thin as about 15mm, and the distance between adjacent lead terminals is 0.15
mm. Therefore, in the conventional semiconductor device, when an external force is applied to the lead terminal when the lead terminal is connected to an external electric circuit, the lead terminal is easily deformed by the external force, and the adjacent lead terminals come into contact with each other to cause a short circuit or lead. There is a disadvantage that the terminals cannot be accurately and firmly electrically connected to a predetermined external electric circuit. In order to solve the above-mentioned drawbacks, the applicant of the present application first prepared a substrate having a metallized wiring layer which spread in a fan shape from the center of the upper surface to the outer periphery, and a lead terminal. And bonding each electrode of the semiconductor element to one end of a metallized wiring layer located at the center of the substrate via a bonding wire, and attaching a lead terminal to the other end of the metallized wiring layer located at the outer periphery of the substrate. Proposed a semiconductor device (Japanese Patent Application Hei 3-
324925). According to such a semiconductor device, the lead terminals are attached to the fan-shaped metallized wiring layer, so that the line widths and adjacent intervals of the lead terminals are widened to effectively prevent the deformation of the lead terminals while adjoining them. Electrical insulation between the lead terminals can be maintained. However, in this semiconductor device, the electrodes of the semiconductor element are electrically connected to the metallized wiring layers via bonding wires, and the electrodes of the semiconductor element are metallized because the number of electrodes of the semiconductor element is extremely large. It takes a long time to connect to the wiring layer, and has the disadvantage that the productivity of the semiconductor device is poor and the semiconductor device as a product is expensive. Further, since the lead terminals have substantially the same shape and a very large number, skill is required to accurately attach them to a predetermined metallized wiring layer, and erroneous attachment is likely to occur. If the terminals are attached to different metallized wiring layers, the electrodes of the semiconductor element cannot be accurately and electrically connected to a predetermined external electric circuit. SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object that even if the density of semiconductor elements is increased and the integration is increased and the number of electrodes is greatly increased, each of the electrodes is electrically connected to an external electrode. It is an object of the present invention to provide an inexpensive semiconductor device which can be accurately and reliably electrically connected to a circuit. [0010] A semiconductor device according to the present invention comprises:
A plurality of metallized wiring layers made of sapphire, which is a translucent material, and formed in a fan shape from the central portion of the upper surface toward the outer peripheral portion and having a three-layer structure of an adhesion layer, an intermediate metal layer, and a main conductor layer. An insulating substrate having a plurality of iron-nickel alloys or iron-nickel-cobalt alloys attached to one end of the metallized wiring layer via solder, and having a surface coated with solder by a plating method. A lead element, a semiconductor element having a plurality of electrodes connected to the other end of the metallized wiring layer by flip-chip connection, and an insulating substrate having the metallized wiring layer, a semiconductor element, and a part of the lead terminal are covered. And a resin member. According to the semiconductor device of the present invention, since the electrodes of the semiconductor element are connected to the metallized wiring layer provided on the insulating substrate by flip-chip connection, even if the number of electrodes of the semiconductor element is large, all the electrodes are connected. Electrical connection can be made to the metallized wiring layer at one time. As a result, the productivity of the semiconductor device is greatly improved, and the semiconductor device can be made inexpensive as a product. Further, according to the semiconductor device of the present invention, since the insulating substrate having the metallized wiring layer is formed of a translucent material, the electrode of the semiconductor element is flip-chip connected to the metallized wiring layer, or When attaching the lead terminals to the metallized wiring layer and the electrodes of the semiconductor element, and the metallized wiring layer and the lead terminals can be accurately aligned through the substrate, as a result, each electrode and the lead terminal of the semiconductor element can be fixed to a predetermined position. And the electrodes of the semiconductor element can be accurately and reliably electrically connected to predetermined external electric circuits via lead terminals. Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a semiconductor device according to the present invention, in which 1 is a substrate made of an electrically insulating translucent material, 2 is a lead terminal, and 3 is a semiconductor element. The insulating substrate 1 is made of sapphire, which is a light-transmitting material, and has a plurality of metallized wiring layers 4 spread in a fan shape from the center of the upper surface to the outer periphery. The metallized wiring layer 4 formed on the upper surface of the insulating substrate 1 serves to connect each electrode of the semiconductor element 3 described later to the lead terminal 2. Each electrode of the semiconductor element 3 is connected to one end by flip-chip connection, and a lead terminal 2 is connected to the other end.
Is attached. The metallized wiring layer 4 includes an adhesion layer made of titanium, nickel-chromium alloy, tantalum nitride, or the like, an intermediate metal layer made of nickel, chromium, palladium, rhodium, platinum, or the like, and a main conductor made of copper, gold, or the like. It has a three-layer structure, and each of the above materials is sequentially placed on the upper surface of the insulating substrate
It is applied by sputtering, vapor deposition, or ion plating, and is processed into a predetermined pattern by photolithography, so that it is applied on the upper surface of the insulating substrate 1 so as to spread in a fan shape from the center to the outer periphery. It is formed. The metallized wiring layer 4 is formed on the insulating substrate 1
The electrode of the semiconductor element 3 is flip-chip connected to a portion located at the center of the semiconductor substrate. More specifically, the semiconductor element 3 is attached to the upper surface of the insulating substrate 1, and the metallized wiring layer 4 and the semiconductor are attached to the upper surface of the insulating substrate 1. The solder bumps previously attached to the respective electrodes of the element 3 are placed so as to face each other, and then the solder bumps are heated and melted, and the metallized wiring layer 4 of the insulating substrate 1 and each of the semiconductor elements 3 are formed. The semiconductor element 3 is attached to the upper surface of the insulating substrate 1 with the electrodes electrically connected to the metallized wiring layer 4 by soldering the electrodes. In this case, even if the total number of the electrodes of the semiconductor element 3 is large, all of the electrodes can be electrically connected to the metallized wiring layer 4 attached to the surface of the insulating substrate 1 at once and firmly via solder. As a result, the electrical connection between each electrode of the semiconductor element 3 and the metallized wiring layer 4 can be made extremely short, thereby greatly improving the productivity of the semiconductor device. When the electrodes of the semiconductor element 3 are connected to the metallized wiring layer 4 attached to the upper surface of the insulating substrate 1 by flip-chip connection, the metallized surface is formed from the lower surface side of the insulating substrate 1 because the insulating substrate 1 is made of a translucent material. The opposing state between the wiring layer 4 and the electrode of the semiconductor element 3 can be confirmed. As a result, each electrode of the semiconductor element 3 can be easily and accurately connected to a predetermined metallized wiring layer 4. . A lead terminal 2 is attached to the metallized wiring layer 4 at a position located on an outer peripheral portion of the insulating substrate 1, and the lead terminal 2 connects each electrode of the semiconductor element 3 to an external electric circuit. Works. Lead terminal 2 to metallized wiring layer 4
Is mounted by placing the lead terminal 2 on the metallized wiring layer 4 via solder and then heating and melting the solder. In this case, since the insulating substrate 1 is made of a translucent material, the alignment between the metallized wiring layer 4 and the lead terminals 2 can be confirmed from the lower surface side of the insulating substrate 1, and as a result, the metallized wiring layer 4 Lead terminal 2 can be easily and accurately attached. Further, in the lead terminal 2, the metallized wiring layer 4 to which the lead terminal 2 is attached extends fanwise from the center of the upper surface of the insulating base 1 toward the outer peripheral portion. Since the width and the distance between adjacent metallized wiring layers 4 are wide, the line width is reduced.
It can be as wide as 0.25mm (approximately 70% wider than the conventional product) and the adjacent space can be wide as 0.25mm (approximately 70% wider than the conventional product). As a result, the external electric circuit Even when an external force is applied when the lead terminals 2 are connected, the lead terminals 2 do not undergo large deformation, and the lead terminals 2 are connected to a predetermined external electric circuit while maintaining electrical insulation between the adjacent lead terminals 2. It is possible to make accurate and strong electrical connection. The lead terminal 2 attached to the metallized wiring layer 4 is made of a metal material such as an iron-nickel-cobalt alloy or an iron-nickel alloy.
An ingot (lumps) of a cobalt alloy or the like is formed into a predetermined shape by employing a conventionally known metal working method such as a rolling method or a punching method. The lead terminal 2 may be formed by plating a metal having excellent corrosion resistance such as nickel and gold and having good wettability with a brazing material to a thickness of 0.1 to 20.0 μm on a surface thereof by plating. 2 can be effectively prevented, and the connection between the lead terminal 2 and the metallized wiring layer 4 and the connection between the lead terminal 2 and an external electric circuit can be improved. Therefore, it is preferable that the lead terminals 2 have nickel, gold or the like layered on the surface thereof in a thickness of 0.1 to 20.0 μm. Further, the lead terminals 2 are coated with solder to a thickness of 1.0 to 20.0 μm on a surface thereof by a plating method, so that connection of the lead terminals 2 to an external electric circuit becomes easy. The semiconductor element 3 and the lead terminal 2 are provided on the upper surface.
The insulating substrate 1 to which is attached is molded with a resin member 5 made of an epoxy resin except for a part of the lead terminal 2, and the semiconductor element 3 is completely shielded from the outside air to become a semiconductor device as a final product. The molding of the semiconductor element 3 and the lead terminal 2 by the resin member 5 sets the insulating substrate 1 on which the semiconductor element 3 and the lead terminal 2 are attached on the upper surface in a predetermined jig and sets the insulating substrate 1 in the jig. A liquid resin such as an epoxy resin is dropped and injected, and thereafter, the injected resin is thermally cured by applying a temperature of about 180 ° C and a pressure of 100 kgf / mm 2 . Thus, the semiconductor device of the present invention is mounted on an information processing apparatus such as a computer by connecting the lead terminal 2 to an external electric circuit and electrically connecting the internal semiconductor element 3 to the external electric circuit. Become. The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. According to the semiconductor device of the present invention, the electrodes of the semiconductor element are connected by flip-chip connection to a plurality of metallized wiring layers provided so as to spread in a fan shape on the insulating substrate and the lower surface of the insulating substrate. Since it is possible to check the facing state between the metallized wiring layer and the electrode of the semiconductor element from the side, even if the number of electrodes of the semiconductor element is large, all the electrodes can be electrically connected to the metallized wiring layer at once, As a result, the productivity of the semiconductor device is greatly improved, and the semiconductor device can be made inexpensive as a product. Further, according to the semiconductor device of the present invention, since the insulating substrate having the metallized wiring layer is formed of a translucent material, the electrode of the semiconductor element is flip-chip connected to the metallized wiring layer, or When attaching the lead terminals to the metallized wiring layer and the electrodes of the semiconductor element, and the metallized wiring layer and the lead terminals can be accurately aligned through the substrate, as a result, each electrode and the lead terminal of the semiconductor element can be fixed to a predetermined position. And the electrodes of the semiconductor element can be accurately and reliably electrically connected to predetermined external electric circuits via lead terminals.
【図面の簡単な説明】
【図１】本発明の半導体装置の一実施例を示す断面図で
ある。
【図２】従来の半導体装置の平面図である。
【符号の説明】
１・・・・・・絶縁基板
２・・・・・・リード端子
３・・・・・・半導体素子
４・・・・・・メタライズ配線層
５・・・・・・樹脂部材BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention. FIG. 2 is a plan view of a conventional semiconductor device. [Description of Signs] 1 ... Insulating substrate 2 ... Lead terminal 3 ... Semiconductor element 4 ... Metalized wiring layer 5 ... Resin Element
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ Ｂ２９Ｌ 31:34 Ｈ０１Ｌ 23/12 Ｋ (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 21/60 H01L 23/28 B29C 43/18 B29C 43/34 B29L 31:34 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 identification code FI B29L 31:34 H01L 23/12 K (58) Investigated field (Int.Cl. 7 , DB name) H01L 23/12 H01L 21 / 60 H01L 23/28 B29C 43/18 B29C 43/34 B29L 31:34
Claims (1)
上面中央部より外周部に向かって扇状に広がって形成さ
れた、密着層と中間金属層と主導体層との３層構造を有
する複数個のメタライズ配線層を有する絶縁基板と、前
記メタライズ配線層の一端に半田を介して取着された、
鉄−ニッケル合金または鉄−ニッケル−コバルト合金か
ら成るとともに表面に半田がメッキ法により被着された
複数個のリード端子と、前記メタライズ配線層の他端に
フリップチップ接続により接続された、複数個の電極を
有する半導体素子と、前記メタライズ配線層を有する絶
縁基板、半導体素子及びリード端子の一部を被覆する樹
脂部材とから成ることを特徴とする半導体装置。(57) [Claims 1] It is made of sapphire which is a translucent material,
An insulating substrate having a plurality of metallized wiring layers having a three-layer structure of an adhesion layer, an intermediate metal layer, and a main conductor layer, formed in a fan-like manner from a central portion of the upper surface to an outer peripheral portion; Attached to one end via solder ,
A plurality of lead terminals made of an iron-nickel alloy or an iron-nickel-cobalt alloy and having a surface coated with solder by a plating method, and connected to the other end of the metallized wiring layer by flip chip connection. A semiconductor device comprising: a semiconductor element having a plurality of electrodes; an insulating substrate having the metallized wiring layer; and a resin member covering a part of the semiconductor element and the lead terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28492894A JP3434918B2 (en) | 1994-11-18 | 1994-11-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28492894A JP3434918B2 (en) | 1994-11-18 | 1994-11-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08148527A JPH08148527A (en) | 1996-06-07 |
| JP3434918B2 true JP3434918B2 (en) | 2003-08-11 |
Family
ID=17684880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28492894A Expired - Fee Related JP3434918B2 (en) | 1994-11-18 | 1994-11-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3434918B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10355508B4 (en) | 2003-11-27 | 2006-07-06 | Infineon Technologies Ag | Ultra-thin semiconductor circuit with contact bumps and associated manufacturing method |
-
1994
- 1994-11-18 JP JP28492894A patent/JP3434918B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08148527A (en) | 1996-06-07 |
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