JP3431326B2 - Hall element and electric quantity measuring device - Google Patents

Hall element and electric quantity measuring device

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Publication number
JP3431326B2
JP3431326B2 JP01484795A JP1484795A JP3431326B2 JP 3431326 B2 JP3431326 B2 JP 3431326B2 JP 01484795 A JP01484795 A JP 01484795A JP 1484795 A JP1484795 A JP 1484795A JP 3431326 B2 JP3431326 B2 JP 3431326B2
Authority
JP
Japan
Prior art keywords
current input
pair
hall element
electrodes
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP01484795A
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Japanese (ja)
Other versions
JPH08213669A (en
Inventor
亮司 丸山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Priority to JP01484795A priority Critical patent/JP3431326B2/en
Publication of JPH08213669A publication Critical patent/JPH08213669A/en
Application granted granted Critical
Publication of JP3431326B2 publication Critical patent/JP3431326B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Hall/Mr Elements (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はホール素子の出力電圧が
入力電流あるいは磁界に比例することを利用した電流
計、磁束計、角変位計および出力電圧が入力電流と磁界
の積に比例することを利用した乗算器、電力計、位相計
などの電気量測定装置、およびこれらの電気量測定装置
に使用するホール素子の特性改善に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention utilizes an output voltage of a Hall element that is proportional to an input current or a magnetic field, an ammeter, a magnetometer, an angular displacement meter, and an output voltage which is proportional to a product of an input current and a magnetic field. The present invention relates to an electric quantity measuring device such as a multiplier, an electric power meter, and a phase meter, which uses an electric field, and a characteristic improvement of a hall element used in the electric quantity measuring device.

【0002】[0002]

【従来の技術】半導体のホール効果を利用したホール素
子が各種の電気量測定装置に広く用いられている。以
下、このようなホール素子について図5を用いて説明す
る。同図(a)は平面図、同図(b)はA−A′の縦断
面図である。ホール素子11はアクセプタ濃度が高いp
+ 基板12の上にn- 層13を成長させ、その上に電流
入力端子I1 ,I2 および電流が流れる方向に直交する
位置に電圧出力端子V1 ,V2 を設けている。Sは基板
12に接続されているサブストレート端子である。磁界
は同図(a)において紙面と直交する方向に加えられ
る。電流計として利用する場合は磁界強度を一定にして
出力電圧を測定し、磁束計として利用する場合は入力電
流を一定にして出力電圧を測定する。また、乗算器や電
力計として利用する場合は被測定系の電圧に比例した電
流と被測定系の電流に比例した磁界を加えて出力電圧を
測定する。
2. Description of the Related Art Hall elements utilizing the Hall effect of semiconductors are widely used in various electric quantity measuring devices. Hereinafter, such a Hall element will be described with reference to FIG. The figure (a) is a top view and the figure (b) is a longitudinal cross-sectional view of AA '. Hall element 11 has a high acceptor concentration p
The n layer 13 is grown on the + substrate 12, and the current input terminals I 1 and I 2 and the voltage output terminals V 1 and V 2 are provided on the + layer 13 at positions orthogonal to the current flowing direction. S is a substrate terminal connected to the substrate 12. The magnetic field is applied in the direction orthogonal to the paper surface in FIG. When used as an ammeter, the output voltage is measured with a constant magnetic field strength, and when used as a flux meter, the output voltage is measured with a constant input current. When used as a multiplier or a power meter, an output voltage is measured by adding a current proportional to the voltage of the system under test and a magnetic field proportional to the current of the system under test.

【0003】[0003]

【発明が解決しようとする課題】しかし、上述した従来
のホール素子では、基板12上のn- 層にキャリアがほ
とんど存在しない空乏層14が形成されるため、電流通
路の抵抗値が大きく変化するという問題があった。その
ため、被測定系の電圧を電流入力端子に印加したとき電
圧に比例する電流が流れず測定誤差を生じる。pn接合
における空乏層の厚さLは次式で表されるように、pn
接合面の拡散電位差Vo の平方根に比例する。
However, in the above-described conventional Hall element, since the depletion layer 14 with almost no carriers is formed in the n layer on the substrate 12, the resistance value of the current path changes greatly. There was a problem. Therefore, when the voltage of the system under measurement is applied to the current input terminal, a current proportional to the voltage does not flow and a measurement error occurs. The thickness L of the depletion layer in the pn junction is expressed by the following equation: pn
It is proportional to the square root of the diffusion potential difference V o at the junction surface.

【0004】[0004]

【数1】 ただし、εは誘電率、qは電子の電荷、NA ,ND はそ
れぞれp形領域のアクセプタ濃度、n形領域のドナー濃
度である。たとえば、図6(a)に示すように、サブス
トレート端子Sを使用電源の最低電位である−5Vに接
続し電流入力端子I1 ,I2 にそれぞれ+2Vおよび0
Vを与えると、同図(a)のように電流入力端子I1
の空乏層14が厚くなる。また、電流入力端子I1 ,I
2 にそれぞれ−2Vおよび0Vを与えると、同図(b)
のように電流入力端子I2 側の空乏層14が厚くなる。
このように電流入力端子I1 ,I2 に印加される電圧に
よって電流が流れない空乏層の厚さが変動するので、電
流入力端子I1 ,I2 間の抵抗値が変動する。
[Equation 1] Here, ε is the dielectric constant, q is the electron charge, N A and N D are the acceptor concentration in the p-type region and the donor concentration in the n-type region, respectively. For example, as shown in FIG. 6A, the substrate terminal S is connected to -5V which is the lowest potential of the power supply used, and the current input terminals I 1 and I 2 are + 2V and 0, respectively.
When V is applied, the depletion layer 14 on the side of the current input terminal I 1 becomes thicker as shown in FIG. In addition, the current input terminals I 1 , I
When -2V and 0V are applied to 2 respectively, the same figure (b)
As described above, the depletion layer 14 on the side of the current input terminal I 2 becomes thick.
Since the thickness of the depletion layer no current flows by such a current input terminal I 1, the voltage applied to the I 2 varies, the resistance value between the current input terminal I 1, I 2 varies.

【0005】また、半導体製造時のマスクパターンのず
れに伴うホール素子の特性のばらつき、および製造後の
機械的なひずみによるピエゾ効果のためのオフセットの
発生、電気抵抗のばらつきが生じるという問題があっ
た。
Further, there is a problem that variations in the characteristics of the Hall element due to the shift of the mask pattern at the time of semiconductor manufacturing, offsets due to the piezo effect due to mechanical strain after manufacturing, and variations in electrical resistance occur. It was

【0006】本発明はこのような従来の問題を解決する
ためになされたものであり、空乏層が形成されず、特性
のばらつきが少ないホール素子、および空乏層の形成に
よって生じる測定誤差ならびにホール素子の特性のばら
つきによる測定誤差を減少させることができる電気量測
定装置を提供することを目的とする。
The present invention has been made in order to solve such a conventional problem, and a Hall element in which a depletion layer is not formed and variation in characteristics is small, a measurement error caused by the formation of the depletion layer, and a Hall element. It is an object of the present invention to provide an electric quantity measuring device capable of reducing the measurement error due to the variation of the characteristics.

【0007】[0007]

【0008】[0008]

【課題を解決するための手段】上記目的を達成するた
め、請求項1記載の発明は、p 形半導体基板上に形成
されたホール効果を呈するn 層に設けられた一対の電
流入力電極と、この一対の電流入力電極間を流れる電流
と直交する位置に設けられた一対の電圧出力電極と、こ
の一対の電圧出力電極にそれぞれ接続された一対の電圧
出力端子と、前記一対の電流入力電極に隣接して形成さ
れて前記p 形半導体基板に接触する一対のサブストレ
ート電極と、前記一対の電流入力電極とそれぞれ近傍の
前記一対のサブストレート電極とが接続された一対の電
流入力端子とを備えたことを特徴とすることを要旨とす
る。
In order to solve the problem] was to achieve the above purpose
Therefore, the invention according to claim 1 is formed on a p − type semiconductor substrate.
A pair of current input electrodes provided in the n layer exhibiting the Hall effect, a pair of voltage output electrodes provided at a position orthogonal to the current flowing between the pair of current input electrodes, and a pair of voltage outputs A pair of voltage output terminals respectively connected to the electrodes, a pair of substrate electrodes formed adjacent to the pair of current input electrodes and contacting the p -type semiconductor substrate , and a pair of current input electrodes, respectively. The gist of the present invention is to have a pair of current input terminals connected to the pair of substrate electrodes in the vicinity.

【0009】また、請求項2記載の発明は、請求項1記
載のホール素子を同一の半導体基板上に、点対称の位置
に複数個形成したことを要旨とする。また、請求項3記
載の発明は、請求項1または請求項2記載のホール素子
を備えたことを要旨とする。
A second aspect of the present invention is characterized in that a plurality of Hall elements according to the first aspect are formed on the same semiconductor substrate at point-symmetrical positions. Also, claim 3
The gist of the present invention is to provide the Hall element according to claim 1 or 2 .

【0010】[0010]

【作用】請求項1記載の発明はこのような手段を講じた
ことにより、pn接合面に空乏層が形成されないので抵
抗値の変動による誤差の発生を未然に防止することがで
きる。
According to the first aspect of the present invention , since the depletion layer is not formed on the pn junction surface by taking such means, it is possible to prevent the occurrence of the error due to the variation of the resistance value.

【0011】また、請求項2記載の発明はこのような手
段を講じたことにより、半導体製造時のホール素子の幾
何学的配置に伴う誤差を減少させることができる。ま
た、請求項3記載の発明はこのような手段を講じたこと
により、電流量測定装置におけるホール素子の空乏層の
発生、および特性のばらつきに伴う誤差を減少させるこ
とができる。
Further, in the invention according to the second aspect, by taking such means, it is possible to reduce the error caused by the geometrical arrangement of the Hall elements at the time of manufacturing the semiconductor. Further, the invention according to claim 3 can reduce the error due to the generation of the depletion layer of the Hall element in the current measuring device and the variation of the characteristics by taking such means.

【0012】[0012]

【実施例】以下、本発明の実施例を図面を参照して説明
する。図1はホール素子の一実施例における構造を示す
平面図(図1(a))およびA−A′における縦断面図
(図1(b))である。同図において、1はホール素
子、2はアクセプタ濃度が低く抵抗値が大きいp形半
導体からなる基板、3は基板2上に形成されホール効果
を呈するn層である。PI1,PI2は電流入力電極で
あって接続部は抵抗値が低いn層が形成されている。
PV1,PV2は電流の流れ方向に直交する位置に設けら
れた電圧出力電極であって接続部は抵抗値が低いn
が形成されている。電流入力電極PI1,PI2および電
圧出力電極PV1,PV2はそれぞれ電流入力端子I1,
I2および電圧出力端子V1,V2に接続されている。P
S1,PS2は電流入力電極PI1,PI2の近傍に(本実
施例の場合は電流入力電極PI1 ,PI2 のそれぞれ外
側に平行して)設けられたサブストレート電極であっ
て、p 形半導体基板2に接続されている。また、それ
ぞれの電極はサブストレート端子S1,S2に接続されて
いる。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the structure of an embodiment of a Hall element.
FIG . 2 is a plan view (FIG . 1A) and a vertical sectional view taken along the line AA ′ (FIG. 1B). In the figure, 1 is a Hall element, 2 acceptor concentration is large p low resistance - substrate made of type semiconductor, it is 3 n exhibits a Hall effect are formed on the substrate 2 - a layer. PI1 and PI2 are current input electrodes, and an n + layer having a low resistance value is formed at the connection portion.
PV1 and PV2 are voltage output electrodes provided at positions orthogonal to the current flow direction, and an n + layer having a low resistance value is formed at the connection portion. The current input electrodes PI1 and PI2 and the voltage output electrodes PV1 and PV2 are the current input terminals I1 and I1, respectively.
It is connected to I2 and the voltage output terminals V1 and V2. P
S1 and PS2 are substrate electrodes provided in the vicinity of the current input electrodes PI1 and PI2 (in the present embodiment, in parallel with the outer sides of the current input electrodes PI1 and PI2, respectively), and are p − type semiconductor substrate 2 It is connected to the. Each electrode is connected to the substrate terminals S1 and S2.

【0013】次に、以上のように構成されたホール素子
の動作について電力計として使用する場合を例にとり、
図2を参照して説明する。被測定系の電流は磁界強度に
変換されて同図(a)の紙面と直交する方向に磁界が加
えられる。また、電流入力端子I1 とサブストレート端
子S1 を、電流入力端子I2 とサブストレート端子S2
をそれぞれ接続し、被測定系の電源電圧を印加する。た
とえば、同図(a)は電流入力端子I1 とサブストレー
ト端子S1 に使用電源の最低電位である0Vを接続し、
電流入力端子I2 とサブストレート端子S2 にそれぞれ
+2Vを接続した場合であり、同図(b)は電流入力端
子I1 とサブストレート端子S1 に使用電源の最低電位
である0Vを接続し、電流入力端子I2 とサブストレー
ト端子S2 にそれぞれ−2Vを接続した場合である。電
流入力電極PI1 とサブストレート電極PS1 とが接近
し、電流入力電極PI2 とサブストレート電極PS2
接近しているので、p- 形半導体からなる基板2の電位
勾配と基板2上に形成されたn- 層の電位勾配とはほと
んど一致するので、空乏層が形成されない。そのため、
電流入力端子I1 ,I2 間の抵抗値は印加される被測定
電圧の影響を受けず一定であるから、ホール素子を流れ
る電流は印加電圧に正しく比例する。したがって、以上
のような実施例の構成によれば、被測定電圧の値の如何
に関わらず電力値に正しく比例する電圧出力を得ること
ができる。
Next, taking as an example a case where the Hall element constructed as described above is used as an electric power meter,
This will be described with reference to FIG. The current of the system to be measured is converted into magnetic field strength, and the magnetic field is applied in the direction orthogonal to the paper surface of FIG. The current input terminal I 1 and the substrate terminal S 1 are connected to each other, and the current input terminal I 2 and the substrate terminal S 2 are connected to each other.
Are connected to each other and the power supply voltage of the system under measurement is applied. For example, in the same figure (a), 0V which is the lowest potential of the power supply used is connected to the current input terminal I 1 and the substrate terminal S 1 ,
This is the case where + 2V is connected to the current input terminal I 2 and the substrate terminal S 2 , respectively, and in the figure (b), 0V which is the lowest potential of the power supply used is connected to the current input terminal I 1 and the substrate terminal S 1. , -2V is respectively connected to the current input terminal I 2 and the substrate terminal S 2 . Since the current input electrode PI 1 and the substrate electrode PS 1 are close to each other and the current input electrode PI 2 and the substrate electrode PS 2 are close to each other, the potential gradient of the substrate 2 made of p − type semiconductor and the substrate 2 are The depletion layer is not formed because it almost matches the potential gradient of the formed n layer. for that reason,
Since the resistance value between the current input terminals I 1 and I 2 is constant without being influenced by the applied voltage to be measured, the current flowing through the Hall element is correctly proportional to the applied voltage. Therefore, according to the configurations of the above-described embodiments, it is possible to obtain a voltage output that is correctly proportional to the power value regardless of the value of the measured voltage.

【0014】図3は発明のホール素子の一実施例にお
ける構造を示す平面図(図3(a))およびA−A′に
おける縦断面図(図3(b))である。同図において、
1はホール素子、2はアクセプタ濃度が低く抵抗値が大
きいp形半導体からなる基板、3は基板2上に形成さ
れホール効果を呈するn層である。電流入力端子IS
1とIS2は電流入力電極PI1,PI2とそれぞれ対応す
るサブストレート電極PS1,PS2とをあらかじめ接続
済みの一対の電流入力端子であって、その動作は図1に
おける上述の説明と同一である。したがって、このよう
な実施例の構成では電流入力端子とサブストレート端子
を外部で接続する必要がない。
FIG. 3 is a plan view (FIG. 3 (a)) and a vertical sectional view taken along line AA '(FIG. 3 (b)) showing the structure of an embodiment of the Hall element of the present invention. In the figure,
1 Hall element, 2 acceptor concentration is large p low resistance - substrate made of type semiconductor, it is 3 n exhibits a Hall effect are formed on the substrate 2 - a layer. Current input terminal IS
1 and IS2 are a pair of current input terminals to which the current input electrodes PI1 and PI2 and the corresponding substrate electrodes PS1 and PS2 have been connected in advance, and the operation thereof is the same as that described above with reference to FIG. Therefore, in the structure of such an embodiment, it is not necessary to connect the current input terminal and the substrate terminal externally.

【0015】図4は請求項2記載の発明の一実施例であ
って、同一の半導体基板4上に請求項2記載の4個のホ
ール素子1−1,1−2,1−3および1−4を点対称
の位置に形成した構造を示す平面図である。ホール素子
1−i(i=1,2,3,4)の電流入力電極をPI1
i,PI2i、電圧出力電極をPV1i,PV2i、サブスト
レート電極をPS1i,PS2iとするとき、電圧出力端子
V1 には4個の電圧出力電極PV1i(i=1,2,3,
4)がすべて並列に接続され、同様に、電圧出力端子V
2 には4個の電圧出力電極PV2i(i=1,2,3,
4)がすべて並列に接続されている。また、電流入力端
子IS1 には4個の電流入力電極PI1i(i=1,2,
3,4)と4個のサブストレート電極PS1i(i=1,
2,3,4)がすべて並列に接続され、同様に、電流入
力端子IS2 には4個の電流入力電極PI2i(i=1,
2,3,4)と4個のサブストレート電極PS2i(i=
1,2,3,4)がすべて並列に接続されている。した
がって、このような実施例の構成では、半導体製造時の
マスクパターンのずれに伴うホール素子の特性のばらつ
き、および製造後の機械的なひずみによる起電力や電気
抵抗が相殺されるのでオフセットを減少させることがで
きる。電気量測定装置の構成についてはとくに図示しな
いが、本発明によるホール素子の特性改善が電気量測定
装置の精度向上に寄与することは明らかである。
FIG. 4 is an embodiment of the invention described in claim 2, and the four Hall elements 1-1, 1-2, 1-3 and 1 described in claim 2 are formed on the same semiconductor substrate 4. It is a top view which shows the structure which formed -4 in the position of point symmetry. Set the current input electrodes of Hall element 1-i (i = 1, 2, 3, 4) to PI1
i, PI2i, voltage output electrodes PV1i, PV2i, and substrate electrodes PS1i, PS2i, the voltage output terminal V1 has four voltage output electrodes PV1i (i = 1, 2, 3,
4) are all connected in parallel, and similarly, the voltage output terminal V
2 has four voltage output electrodes PV2i (i = 1, 2, 3,
4) are all connected in parallel. Further, the current input terminal IS1 has four current input electrodes PI1i (i = 1, 2,
3, 4) and four substrate electrodes PS1i (i = 1, 1
2, 3, 4) are all connected in parallel, and similarly, the four current input electrodes PI2i (i = 1, 1) are connected to the current input terminal IS2.
2, 3, 4) and four substrate electrodes PS2i (i =
1, 2, 3, 4) are all connected in parallel. Therefore, in the structure of such an embodiment, the offset is reduced because the variations in the characteristics of the Hall element due to the shift of the mask pattern during semiconductor manufacturing, and the electromotive force and electric resistance due to mechanical strain after manufacturing are offset. Can be made. Although the structure of the electric quantity measuring device is not particularly shown, it is clear that the improvement of the characteristics of the Hall element according to the present invention contributes to the improvement of the accuracy of the electric quantity measuring device.

【0016】[0016]

【発明の効果】以上説明したように請求項1記載の発明
によれば、pn接合面に空乏層を形成しないので抵抗値
の変動による誤差の発生を未然に防止することができ
る。
As described above, according to the first aspect of the present invention, since the depletion layer is not formed on the pn junction surface, it is possible to prevent the occurrence of an error due to the variation of the resistance value.

【0017】また、請求項2記載の発明によれば、ホー
ル素子の特性のばらつき、および機械的なひずみによる
起電力や電気抵抗を相殺し、オフセットが少ないホール
素子を構成することができる。また、請求項3記載の発
によれば、精度の高い電気量測定装置を構成すること
ができる。
According to the second aspect of the present invention , it is possible to construct a Hall element having a small offset by canceling out variations in characteristics of the Hall element and electromotive force and electric resistance due to mechanical strain. In addition, according to claim 3,
According to bright, it is possible to construct a highly accurate electric quantity measuring device.

【図面の簡単な説明】[Brief description of drawings]

【図1】ホール素子の一実施例における構造を示す平面
図および縦断面図である。
1A and 1B are a plan view and a vertical sectional view showing the structure of an embodiment of a Hall element.

【図2】ホール素子の動作説明図である。FIG. 2 is an operation explanatory diagram of a Hall element.

【図3】請求項1記載の発明のホール素子の一実施例に
おける構造を示す平面図および縦断面図である。
3 is a plan view and a longitudinal sectional view showing the structure of an embodiment of the Hall element of the invention of claim 1, wherein.

【図4】請求項2記載の発明のホール素子の一実施例に
おける構造を示す平面図である。
FIG. 4 is a plan view showing the structure of an embodiment of the Hall element of the present invention according to claim 2 ;

【図5】従来のホール素子の構造を示す平面図および縦
断面図である。
5A and 5B are a plan view and a vertical sectional view showing a structure of a conventional Hall element.

【図6】従来のホール素子の動作説明図である。FIG. 6 is an operation explanatory diagram of a conventional Hall element.

【符号の説明】[Explanation of symbols]

1 ホール素子 2 p- 形半導体からなるホール素子の基板 3 基板2上に形成されホール効果を呈するn- 層 4 4個のホール素子を点対称の位置に形成したホール
素子 I1,I2 電流入力端子 V1,V2 電圧出力端子 S1,S2 サブストレート端子 PI1,PI2 電流入力電極 PV1,PV2 電圧出力電極 PS1,PS2 サブストレート電極
1 Hall element 2 Substrate of Hall element made of p- type semiconductor 3 n- layer 4 formed on the substrate 2 and exhibiting the Hall effect 4 Hall elements I1 and I2 current input terminals in which four Hall elements are formed in point symmetrical positions V1, V2 voltage output terminals S1, S2 substrate terminals PI1, PI2 current input electrodes PV1, PV2 voltage output electrodes PS1, PS2 substrate electrodes

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 43/06 G01R 33/07 H01L 21/76 ─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 43/06 G01R 33/07 H01L 21/76

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 形半導体基板上に形成されたホール
効果を呈するn 層に設けられた一対の電流入力電極
と、この一対の電流入力電極間を流れる電流と直交する
位置に設けられた一対の電圧出力電極と、この一対の電
圧出力電極にそれぞれ接続された一対の電圧出力端子
と、前記一対の電流入力電極に隣接して形成されて前記
形半導体基板に接触する一対のサブストレート電極
と、前記一対の電流入力電極とそれぞれ近傍の前記一対
のサブストレート電極とが接続された一対の電流入力端
子とを備えたことを特徴とするホール素子。
1. A p - holes formed in the shape semiconductor substrate
A pair of current input electrodes provided in the n layer that exhibits the effect, a pair of voltage output electrodes provided at a position orthogonal to the current flowing between the pair of current input electrodes, and a pair of voltage output electrodes respectively. a pair of voltage output terminals connected, the formed adjacent to the pair of current input electrode
a pair of substrate electrodes in contact with the p − type semiconductor substrate; and a pair of current input terminals to which the pair of current input electrodes and the pair of substrate electrodes in the vicinity thereof are connected. Hall element.
【請求項2】請求項1記載のホール素子を同一の半導体
基板上に点対称の位置に複数個形成したことを特徴とす
るホール素子。
2. A Hall element comprising a plurality of the Hall elements according to claim 1 formed on the same semiconductor substrate at point-symmetrical positions.
【請求項3】請求項1または請求項2記載のホール素子
を備えたことを特徴とする電気量測定装置。
3. An electrical quantity measuring device comprising the hall element according to claim 1 or 2 .
JP01484795A 1995-02-01 1995-02-01 Hall element and electric quantity measuring device Expired - Fee Related JP3431326B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP01484795A JP3431326B2 (en) 1995-02-01 1995-02-01 Hall element and electric quantity measuring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01484795A JP3431326B2 (en) 1995-02-01 1995-02-01 Hall element and electric quantity measuring device

Publications (2)

Publication Number Publication Date
JPH08213669A JPH08213669A (en) 1996-08-20
JP3431326B2 true JP3431326B2 (en) 2003-07-28

Family

ID=11872438

Family Applications (1)

Application Number Title Priority Date Filing Date
JP01484795A Expired - Fee Related JP3431326B2 (en) 1995-02-01 1995-02-01 Hall element and electric quantity measuring device

Country Status (1)

Country Link
JP (1) JP3431326B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011101604B4 (en) * 2010-06-02 2016-06-09 Albert-Ludwigs-Universität Freiburg magnetic field sensor
US8901923B2 (en) 2011-06-03 2014-12-02 Micronas Gmbh Magnetic field sensor

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52139390A (en) * 1976-05-17 1977-11-21 Hitachi Ltd Semiconductor integrated circuit device
JPS58157151A (en) * 1982-03-15 1983-09-19 Mitsubishi Electric Corp Semiconductor integrated circuit device
CH668146A5 (en) * 1985-05-22 1988-11-30 Landis & Gyr Ag FURNISHING WITH A HALL ELEMENT IN INTEGRATED SEMICONDUCTOR TECHNOLOGY.
JPH0311679A (en) * 1989-06-08 1991-01-18 Mitsubishi Petrochem Co Ltd Hall device

Also Published As

Publication number Publication date
JPH08213669A (en) 1996-08-20

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