JP3426255B2 - Active matrix substrate - Google Patents

Active matrix substrate

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Publication number
JP3426255B2
JP3426255B2 JP09212191A JP9212191A JP3426255B2 JP 3426255 B2 JP3426255 B2 JP 3426255B2 JP 09212191 A JP09212191 A JP 09212191A JP 9212191 A JP9212191 A JP 9212191A JP 3426255 B2 JP3426255 B2 JP 3426255B2
Authority
JP
Japan
Prior art keywords
thin film
film transistor
silicon
hydrogen
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP09212191A
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Japanese (ja)
Other versions
JPH04323876A (en
Inventor
英幸 赤沼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
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Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は液晶表示体に用いられる
薄膜トランジスタの構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a thin film transistor used in a liquid crystal display.

【0002】[0002]

【従来の技術】従来の薄膜トランジスタは、例えば「1
989年InternationalElectron
Device Meeting (IEDM)Tec
h−nical Digest,p.p.157−16
0,H.Ohshimaet.al.」にあるように、
基本的には図1のような構造をしており、絶縁基板10
1あるいは絶縁膜上にドレイン電極102、ソース電極
103、チャネル領域104からなるシリコン薄膜10
5とシリコン薄膜105を覆うゲート絶縁膜106、ゲ
ート絶縁膜106を介してチャネル領域104と対向す
るゲート電極107、これらを覆う層間絶縁膜108、
そしてゲート絶縁膜106と層間絶縁膜108に開けた
コンタクトホールでシリコン薄膜105のドレイン電極
102とソース電極103にそれぞれつながるドレイン
電極配線109とソース電極配線110からなる。
2. Description of the Related Art A conventional thin film transistor is, for example, "1".
989 International Electron
Device Meeting (IEDM) Tec
h-nical Digest, p. p. 157-16
0, H. Ohshimaet. al. , ”
Basically, the structure is as shown in FIG.
1 or a silicon thin film 10 including a drain electrode 102, a source electrode 103, and a channel region 104 on an insulating film
5, a gate insulating film 106 covering the silicon thin film 105, a gate electrode 107 facing the channel region 104 through the gate insulating film 106, an interlayer insulating film 108 covering these.
Then, a drain electrode wiring 109 and a source electrode wiring 110 which are respectively connected to the drain electrode 102 and the source electrode 103 of the silicon thin film 105 through contact holes formed in the gate insulating film 106 and the interlayer insulating film 108 are formed.

【0003】このような薄膜トランジスタは、シリコン
薄膜105がアモルファスシリコンのものと多結晶シリ
コンのものに大別されるが、キャリアの易動度などその
性能の面では多結晶シリコンがよい。
In such a thin film transistor, the silicon thin film 105 is roughly classified into amorphous silicon and polycrystalline silicon, and polycrystalline silicon is preferable in terms of performance such as carrier mobility.

【0004】多結晶シリコン薄膜トランジスタの高性能
化、即ち半導体シリコン中のキャリアの易動度向上によ
るON電流の増加のために幾つかの技術が使われる。例
えばシリコン薄膜に高エネルギーのレーザー光を照射す
ることでシリコンの結晶化を促進したり、溶融再結晶化
させてキャリアトラップの低減を図ることで、レーザー
光照射の無い場合に比べて易動度が非常に大きく高性能
な薄膜トランジスタが得られる。また、水素プラズマ技
術によるシリコン中のトラップの不動態化や、長時間の
加熱処理を施すいわゆる固相成長法も薄膜トランジスタ
の高易動度化に有効である。
Several techniques are used to improve the performance of polycrystalline silicon thin film transistors, that is, increase the ON current by increasing the mobility of carriers in semiconductor silicon. For example, by irradiating a silicon thin film with high-energy laser light to promote crystallization of silicon, or by melting and recrystallizing it to reduce carrier traps, mobility can be improved compared to the case without laser light irradiation. A very large and high-performance thin film transistor can be obtained. In addition, passivation of traps in silicon by hydrogen plasma technology and so-called solid phase growth method in which heat treatment is performed for a long time are also effective for increasing mobility of thin film transistors.

【0005】[0005]

【発明が解決しようとする課題】上述のような方法によ
る薄膜トランジスタの高性能化によって、薄膜トランジ
スタにより大きな電流(ON電流)を流せるようになっ
た。しかし、それにともない、薄膜トランジスタを流れ
る電流による薄膜トランジスタ自身の劣化が問題にな
る。その問題の1つはいわゆるホットエレクトロンのゲ
ート絶縁膜への注入などによる劣化であり、もう1つは
薄膜トランジスタ自身の発熱による劣化である。前者に
ついては薄膜トランジスタのドレインのゲート電極に近
い部分の不純物濃度を小さくするいわゆるLDD構造と
することで改善が図られている。
By improving the performance of the thin film transistor by the above method, a larger current (ON current) can be passed through the thin film transistor. However, along with this, deterioration of the thin film transistor itself due to a current flowing through the thin film transistor becomes a problem. One of the problems is deterioration due to injection of so-called hot electrons into the gate insulating film, and the other is deterioration due to heat generation of the thin film transistor itself. The former has been improved by adopting a so-called LDD structure in which the impurity concentration in the portion of the drain of the thin film transistor near the gate electrode is reduced.

【0006】シリコン基板上に形成されたトランジスタ
では、シリコン基板の熱伝導率が比較的大きいためトラ
ンジスタ個々の熱はすぐに基板中に拡散してしまう。こ
れに対し、アクティブマトリクス型の液晶表示体などに
用いられる薄膜トランジスタでは、ガラスなどの熱伝導
率の小さい基板上に薄膜トランジスタが形成されるた
め、薄膜トランジスタ個々の発熱は拡散されにくい。そ
のような場合に、上記のように薄膜トランジスタに流れ
る電流が大きくなり発熱が大きくなると、その熱のため
に薄膜トランジスタを構成するシリコン薄膜の結晶状態
が変化して新たな欠陥が生じたり、水素プラズマ技術に
よって導入したシリコン薄膜中の水素の再脱離によって
キャリアトラップが増加し、薄膜トランジスタの特性が
変化して、設計通りの初期特性を長時間維持できないな
ど信頼性を欠く。
In a transistor formed on a silicon substrate, the heat conductivity of the silicon substrate is relatively large, and the heat of each transistor is immediately diffused into the substrate. On the other hand, in a thin film transistor used for an active matrix type liquid crystal display or the like, since the thin film transistor is formed on a substrate having a low thermal conductivity such as glass, the heat generated by each thin film transistor is difficult to diffuse. In such a case, when the current flowing through the thin film transistor increases and the heat generation increases as described above, the crystal state of the silicon thin film forming the thin film transistor changes due to the heat and a new defect occurs, or the hydrogen plasma technology Due to the re-desorption of hydrogen in the silicon thin film introduced by the method, carrier traps increase, the characteristics of the thin film transistor change, and the initial characteristics as designed cannot be maintained for a long time, resulting in lack of reliability.

【0007】[0007]

【課題を解決するための手段】本発明のアクティブマト
リクス基板は、絶縁基板上に形成され前記絶縁基板より
も熱伝導率が大きく、配線層を兼ねた金属でなる熱伝導
層と、前記熱伝導層上に絶縁膜を介して形成され、水素
プラズマ処理でシリコン中に水素が注入されたLDD構
造の薄膜トランジスタとを備えることを特徴とする。ま
た、本発明のアクティブマトリクス基板は、絶縁基板上
に形成された絶縁膜上に形成され、前記絶縁膜よりも熱
伝導率が大きく、配線層を兼ねた金属でなる熱伝導層
と、前記熱伝導層上に絶縁膜を介して形成され、水素プ
ラズマ処理でシリコン中に水素が注入されたLDD構造
の薄膜トランジスタとを備えることを特徴とする。ま
た、熱伝導層は約2000オングストロームのクロム層
を形成していることを特徴とする。
An active matrix substrate of the present invention is formed on an insulating substrate, has a thermal conductivity higher than that of the insulating substrate, and is made of a metal serving as a wiring layer. And a thin film transistor having an LDD structure in which hydrogen is injected into silicon by hydrogen plasma treatment. Further, the active matrix substrate of the present invention is formed on an insulating film formed on an insulating substrate, has a thermal conductivity higher than that of the insulating film, and is made of a metal that also serves as a wiring layer. A thin film transistor having an LDD structure, which is formed on a conductive layer via an insulating film and in which hydrogen is injected into silicon by hydrogen plasma treatment, is provided. Further, the heat conducting layer is characterized by forming a chromium layer having a thickness of about 2000 angstroms.

【0008】[0008]

【実施例】本発明の薄膜トランジスタの1例を図2によ
り、以下に工程を追いながら具体的に説明する。
EXAMPLE An example of the thin film transistor of the present invention will be specifically described with reference to FIG.

【0009】ガラス基板201はガラスそのままであっ
てもよいが、ガラスの表面にSiO2 などの絶縁膜を形
成してから用いることもある。ここではガラスそのまま
で用いている。このガラス基板201の上に熱伝導層2
02としてスパッタリング法でCr薄膜を約2000Å
の膜厚で堆積し、その上に絶縁膜203としてSiO2
薄膜を約2000Åの膜厚で化学気相成長法(CVD
法)により堆積した。
The glass substrate 201 may be the glass as it is, but it may be used after forming an insulating film such as SiO 2 on the surface of the glass. Here, the glass is used as it is. The heat conductive layer 2 is formed on the glass substrate 201.
As a No. 02, a Cr thin film of about 2000 Å is formed by the sputtering method.
Of SiO 2 and SiO 2 as an insulating film 203 thereon.
A thin film with a thickness of about 2000Å is prepared by chemical vapor deposition (CVD
Method).

【0010】この上に多結晶シリコンからなるシリコン
薄膜204を減圧CVD法により形成し、これにレーザ
ー光の照射を行ってからフォトリソグラフィ技術により
パターニングしたうえで、ゲート絶縁膜205としてS
iO2薄膜を全面にECRプラズマCVD法によって形
成した。シリコン薄膜へのレーザー光の照射はシリコン
薄膜204のパターニング後に行う事もある。また、シ
リコン薄膜204としてプラズマCVD法でアモルファ
スシリコンを堆積した後、レーザー光照射によって結晶
化することもある。ゲート絶縁膜205は、シリコン薄
膜204の熱酸化によっても形成できる。
A silicon thin film 204 made of polycrystalline silicon is formed on this by a low pressure CVD method, and a laser beam is applied to this, followed by patterning by a photolithography technique.
An iO 2 thin film was formed on the entire surface by the ECR plasma CVD method. Irradiation of the laser beam to the silicon thin film may be performed after the patterning of the silicon thin film 204. Further, amorphous silicon may be deposited as the silicon thin film 204 by a plasma CVD method and then crystallized by laser light irradiation. The gate insulating film 205 can also be formed by thermal oxidation of the silicon thin film 204.

【0011】そして、さらにシリコン薄膜を堆積した
後、パターニングしゲート電極206を形成した。シリ
コン薄膜204のパターニングの際のマスクであるフォ
トレジスト207は、この薄膜トランジスタをドレイン
電極のゲート電極に近い部分の不純物濃度が小さい、い
わゆるLDD構造(Lightly DopedDra
in構造)にするため、後の工程で必要になるので残し
ておく。次にゲート電極206とフォトレジスト207
をマスクにしてシリコン薄膜204中に不純物として燐
イオンあるいはホウ素イオンを第1のイオンシャワー2
08により高濃度で打ち込み、自己整合的にソース電極
209とドレイン電極210を形成した。
After further depositing a silicon thin film, patterning was performed to form a gate electrode 206. The photoresist 207, which is a mask when patterning the silicon thin film 204, has a so-called LDD structure (Lightly Doped Dra) in which the thin film transistor has a low impurity concentration in the portion near the gate electrode of the drain electrode.
In structure), it will be necessary in a later step, so it is left. Next, the gate electrode 206 and the photoresist 207
With the mask as a mask, phosphorus ions or boron ions as impurities are introduced into the silicon thin film 204 as the first ion shower 2
No. 08, the source electrode 209 and the drain electrode 210 were formed in a high concentration by self-alignment.

【0012】この後、プラズマエッチング法によりゲー
ト電極206をさらにエッチングする。前の工程でフォ
トレジスト207を残してあるので、ゲート電極206
は両端のみがエッチングされ細くなる。ここでフォトレ
ジスト207を取り除き、第2のイオンシャワー211
で第1のイオンシャワー208と同じイオンを第1のイ
オンシャワー208より低濃度で打ち込んだ。この低濃
度のイオンを打ち込んだ部分がLDD部分212であ
り、ゲート電極206の下のイオンの打ち込まれなかっ
た部分がチャネル領域213である。ソース電極209
側にもイオンを低濃度で打ち込んだ領域が存在するが、
これもLDD部分212と呼ぶ。この後、加熱あるいは
レーザー光照射によって打ち込んだイオンの活性化を行
った。
After that, the gate electrode 206 is further etched by the plasma etching method. Since the photoresist 207 was left in the previous step, the gate electrode 206
Is thinned by etching only both ends. Here, the photoresist 207 is removed, and the second ion shower 211 is removed.
Then, the same ions as in the first ion shower 208 were implanted at a lower concentration than in the first ion shower 208. The LDD portion 212 is the portion where the ions of low concentration are implanted, and the channel region 213 is the portion under the gate electrode 206 where the ions are not implanted. Source electrode 209
There is also a region where ions are implanted at a low concentration on the side,
This is also called the LDD portion 212. After that, the ions implanted by heating or laser light irradiation were activated.

【0013】この上に層間絶縁膜214としてSiO2
を約5000ÅCVD法で堆積し、ソース電極209と
ドレイン電極210の上のゲート絶縁膜205と層間絶
縁膜214にコンタクト穴を開け、ソース電極配線21
5及びドレイン電極配線216を形成し、さらに水素プ
ラズマ中に暴露してシリコン薄膜204中のキャリアト
ラップの不動態化処理を施し薄膜トランジスタを完成し
た。
On top of this, an SiO 2 film is formed as an interlayer insulating film 214.
Is deposited by a CVD method of about 5000 Å, contact holes are formed in the gate insulating film 205 and the interlayer insulating film 214 on the source electrode 209 and the drain electrode 210, and the source electrode wiring 21 is formed.
5 and the drain electrode wiring 216 were formed, and further exposed to hydrogen plasma to passivate the carrier trap in the silicon thin film 204 to complete the thin film transistor.

【0014】本実施例においては、薄膜トランジスタと
絶縁基板あるいは絶縁膜の間の熱伝導層に金属のクロム
(Cr)を用い、これが絶縁膜を介して薄膜トランジス
タのシリコン薄膜に発した熱を放散する構造になってい
るが、熱伝導層に用いる金属は後の工程における熱に耐
えるものであればCrでなくても良い。また、この熱伝
導層が金属である場合には、例えば本発明の薄膜トラン
ジスタをアクティブマトリクス基板に応用した場合な
ど、何らかの配線層をこの熱伝導層が兼ねるか、少なく
とも同層に形成することができる。
In the present embodiment, metal chromium (Cr) is used for the heat conducting layer between the thin film transistor and the insulating substrate or the insulating film, and this dissipates the heat emitted to the silicon thin film of the thin film transistor through the insulating film. However, the metal used for the heat conductive layer may not be Cr as long as it can withstand the heat in the subsequent steps. When the heat conducting layer is a metal, for example, when the thin film transistor of the present invention is applied to an active matrix substrate, the heat conducting layer also serves as some wiring layer or can be formed at least in the same layer. .

【0015】また、熱伝導層に絶縁物を用いれば、金属
を用いた場合のように薄膜トランジスタとの間に絶縁膜
を介する必要がないので、より有効に熱を放散でき、ま
た、工程を簡略化できる。熱伝導層に用いることのでき
る絶縁物あるいは絶縁物に近い材料としては、例えばセ
ラミクス薄膜やダイアモンド薄膜等が考えられる。特に
ダイアモンド薄膜は透明であり、本発明の薄膜トランジ
スタを液晶表示体などに応用する場合、パターニング等
の加工を施す必要がなく、従来の薄膜トランジスタと比
べても工程が大きく増えることはない。
Further, when an insulator is used for the heat conducting layer, it is not necessary to interpose an insulating film between the thin film transistor and the thin film transistor as in the case of using a metal, so that heat can be more effectively dissipated and the process is simplified. Can be converted. As the insulator or a material close to the insulator that can be used for the heat conduction layer, for example, a ceramic thin film or a diamond thin film can be considered. In particular, the diamond thin film is transparent, and when the thin film transistor of the present invention is applied to a liquid crystal display or the like, it is not necessary to perform processing such as patterning, and the number of steps is not significantly increased compared with the conventional thin film transistor.

【0016】〔従来の技術〕及び〔発明が解決しようと
する課題〕の項で述べたような薄膜トランジスタの劣化
の1例を、熱伝導層の無い従来の薄膜トランジスタ(図
1の薄膜トランジスタ)について図3に示す。チャネル
幅10μm、チャネル長5μmの薄膜トランジスタにお
いて、数分の直流通電の後、ゲートソース間電圧(Vg
s)−ドレインソース間電流(Ids)のグラフに、電
流の立ち上がり電位の変化、電流値の全体的低下がみら
れた。特に水素プラズマ技術によりシリコン中のキャリ
アトラップを不動態化した薄膜トランジスタでは、温度
が約400℃以上になると水素プラズマでシリコン中に
注入した水素が脱離しはじめて、薄膜トランジスタの特
性が劣化する。そして温度が高いほど劣化が激しい。ま
た、薄膜トランジスタのドレイン電極あるいはソース電
極に不純物として注入した燐イオンやホウ素イオンの、
チャネル領域での発熱によるチャネル領域への拡散も特
性変化の原因と考えられる。このような事情からも考え
られるように、上述のような工程を経て作られた本発明
の薄膜トランジスタは、ガラスのような熱伝導率の小さ
い基板上に直接あるいはSiO2膜を介しただけで形成
した従来の薄膜トランジスタに比べ、自己の発熱に対す
る放熱の能力が高いことからその特性の劣化は小さい。
更に熱伝導層の効果として考えられるのは、ガラス基板
などからの有害な不純物の熱による拡散の抑制効果であ
る。SiO2 薄膜などによっても不純物拡散の抑制は可
能であるが、不純物の拡散が高温ほど速いことを考えれ
ば熱伝導層を設けることで不純物の拡散を更に遅くで
き、長期に渡る薄膜トランジスタの信頼性の確保に効果
がある。
One example of the deterioration of the thin film transistor as described in the [Prior Art] and [Problems to be Solved by the Invention] is shown in FIG. Shown in. In a thin film transistor having a channel width of 10 μm and a channel length of 5 μm, a gate-source voltage (Vg
In the graph of (s) -drain source current (Ids), changes in the rising potential of the current and an overall decrease in the current value were observed. Particularly in a thin film transistor in which a carrier trap in silicon is passivated by hydrogen plasma technology, when the temperature rises to about 400 ° C. or more, hydrogen injected into silicon starts to be desorbed by hydrogen plasma, and the characteristics of the thin film transistor deteriorate. And the higher the temperature, the more severe the deterioration. In addition, phosphorus ions or boron ions implanted as impurities into the drain electrode or the source electrode of the thin film transistor,
Diffusion into the channel region due to heat generation in the channel region is also considered to be the cause of the characteristic change. As is conceivable from such circumstances, the thin film transistor of the present invention manufactured through the above-described steps is formed directly on a substrate having a small thermal conductivity such as glass or only through a SiO 2 film. Compared with the conventional thin film transistor described above, since the ability to dissipate heat generated by the thin film transistor is high, deterioration of the characteristics is small.
Further conceivable as the effect of the heat conduction layer is the effect of suppressing the diffusion of harmful impurities from the glass substrate or the like due to heat. Although the diffusion of impurities can be suppressed by using a SiO 2 thin film, etc., considering that the diffusion of impurities is faster at higher temperatures, the diffusion of impurities can be further delayed by providing a heat conduction layer, and the reliability of the thin film transistor for a long time can be improved. It is effective in securing.

【0017】[0017]

【発明の効果】以上述べたように、本発明の液晶表示体
用薄膜トランジスタは、従来の薄膜トランジスタに比べ
て自己の発熱に対する放熱能力が大きく、高性能化が進
み大電流を流せるようになった液晶表示体用薄膜トラン
ジスタにおいて特に信頼性の向上に寄与する。
As described above, the thin film transistor for a liquid crystal display according to the present invention has a large heat dissipation ability against its own heat generation as compared with the conventional thin film transistor, and has improved performance so that a large current can flow. In particular, it contributes to the improvement of reliability in the thin film transistor for display.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の薄膜トランジスタの構造を示す説明図。FIG. 1 is an explanatory diagram showing a structure of a conventional thin film transistor.

【図2】本発明の薄膜トランジスタの工程と構造を示す
説明図。
FIG. 2 is an explanatory view showing a process and a structure of a thin film transistor of the invention.

【図3】従来の薄膜トランジスタの特性の劣化を示すゲ
ートソース間電位(Vgs)−ドレインソース間電流
(Ids)のグラフ。
FIG. 3 is a graph of gate-source potential (Vgs) -drain-source current (Ids) showing deterioration of characteristics of a conventional thin film transistor.

【符号の説明】[Explanation of symbols]

101 絶縁基板 102 210 ドレイン電極 103 209 ソース電極 104 チャネル領域 105 204 シリコン薄膜 106 205 ゲート絶縁膜 107 206 ゲート電極 108 層間絶縁膜 109 216 ドレイン電極配線 110 215 ソース電極配線 201 ガラス基板 202 熱伝導層 203 絶縁膜 207 フォトレジスト 208 第1のイオンシャワー 211 第2のイオンシャワー 212 LDD部分 213 チャネル領域 214 層間絶縁膜 101 insulating substrate 102 210 drain electrode 103 209 Source electrode 104 channel region 105 204 Silicon thin film 106 205 gate insulating film 107 206 Gate electrode 108 Interlayer insulating film 109 216 Drain electrode wiring 110 215 Source electrode wiring 201 glass substrate 202 heat conductive layer 203 insulating film 207 photoresist 208 First Ion Shower 211 Second ion shower 212 LDD part 213 channel region 214 Interlayer insulation film

フロントページの続き (56)参考文献 特開 昭56−126956(JP,A) 特開 昭62−254459(JP,A) 特開 昭63−142851(JP,A) 特開 昭62−16509(JP,A) 特開 昭63−10516(JP,A) 特開 昭58−142566(JP,A) 特開 昭58−204570(JP,A) 特開 昭59−204275(JP,A) 特開 昭64−61062(JP,A) 特開 平3−4214(JP,A) 特開 昭61−51973(JP,A)Continued front page       (56) References JP-A-56-126956 (JP, A)                 JP 62-254459 (JP, A)                 JP 63-142851 (JP, A)                 JP 62-16509 (JP, A)                 JP-A-63-10516 (JP, A)                 JP-A-58-142566 (JP, A)                 JP-A-58-204570 (JP, A)                 JP-A-59-204275 (JP, A)                 JP 64-61062 (JP, A)                 Japanese Patent Laid-Open No. 3-4214 (JP, A)                 JP 61-51973 (JP, A)

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 絶縁基板上に形成され前記絶縁基板より
も熱伝導率が大きく、配線層を兼ねた金属でなる熱伝導
層と、前記熱伝導層上に絶縁膜を介して形成され、水素
プラズマ処理でシリコン中に水素が注入されたLDD構
造の薄膜トランジスタとを備えることを特徴とするアク
ティブマトリクス基板。
1. A hydrogen conductive layer formed on an insulating substrate, having a thermal conductivity higher than that of the insulating substrate, and made of a metal which also serves as a wiring layer, and a hydrogen formed on the thermal conductive layer via an insulating film. An active matrix substrate, comprising: a thin film transistor having an LDD structure in which hydrogen is injected into silicon by plasma treatment.
【請求項2】 絶縁基板上に形成された絶縁膜上に形成
され、前記絶縁膜よりも熱伝導率が大きく、配線層を兼
ねた金属でなる熱伝導層と、前記熱伝導層上に絶縁膜を
介して形成され、水素プラズマ処理でシリコン中に水素
が注入されたLDD構造の薄膜トランジスタとを備える
ことを特徴とするアクティブマトリクス基板。
2. A heat conductive layer formed on an insulating film formed on an insulating substrate, having a thermal conductivity higher than that of the insulating film, and made of a metal also serving as a wiring layer, and insulating on the heat conductive layer. An active matrix substrate comprising: a thin film transistor having an LDD structure, which is formed through a film and in which hydrogen is injected into silicon by hydrogen plasma treatment.
【請求項3】 前記熱伝導層は約2000オングストロ
ームのクロム層を形成していることを特徴とする請求項
1または請求項2記載のアクティブマトリクス基板。
3. The active matrix substrate according to claim 1, wherein the heat conducting layer forms a chromium layer having a thickness of about 2000 angstroms.
JP09212191A 1991-04-23 1991-04-23 Active matrix substrate Expired - Lifetime JP3426255B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09212191A JP3426255B2 (en) 1991-04-23 1991-04-23 Active matrix substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09212191A JP3426255B2 (en) 1991-04-23 1991-04-23 Active matrix substrate

Publications (2)

Publication Number Publication Date
JPH04323876A JPH04323876A (en) 1992-11-13
JP3426255B2 true JP3426255B2 (en) 2003-07-14

Family

ID=14045604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP09212191A Expired - Lifetime JP3426255B2 (en) 1991-04-23 1991-04-23 Active matrix substrate

Country Status (1)

Country Link
JP (1) JP3426255B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331722B1 (en) 1997-01-18 2001-12-18 Semiconductor Energy Laboratory Co., Ltd. Hybrid circuit and electronic device using same

Also Published As

Publication number Publication date
JPH04323876A (en) 1992-11-13

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