JP3413683B2 - Horizontal deflection frequency generation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal deflection frequency generating circuit for generating a required horizontal deflection frequency in a television receiver, a monitor device or the like.

[0002]

2. Description of the Related Art As a horizontal deflection frequency generating circuit provided in a television receiver, a monitor device, etc., for example, FIG.
Those shown in are known. In this figure, 1 is a horizontal synchronizing signal HD and a vertical synchronizing signal V from the input video signal.
This is a sync separation circuit that extracts and outputs D, and in this case, the horizontal sync signal HD of frequency f _D is input to the phase comparator 2 as a reference signal. Reference numeral 2 is a phase comparator for comparing the phase difference between the reference signal and the comparison signal, 3 is a low pass filter (hereinafter referred to as LPF) for filtering the phase comparison output of the phase comparator 2 to form an error signal, and 4 is a low pass filter. 3 is a voltage controlled oscillator (hereinafter referred to as VCO) whose oscillation frequency is controlled according to the voltage value of the error signal input from the circuit 3.
Reference numeral 4a connected to the VCO 4 via the resistor R represents a piezoelectric vibrator. Reference numeral 5 denotes a horizontal driver unit that amplifies and outputs the oscillation frequency signal output from the VCO 4, and 6 denotes a horizontal output circuit that is driven by the horizontal driver unit 5 and outputs a horizontal deflection current to a deflection yoke (not shown). is there. A pulse signal obtained from a flyback transformer, for example, is input from the horizontal output circuit 6 to the phase comparator 2 as a comparison signal.

In the case of such a horizontal deflection frequency generating circuit composed of the PLL circuit, the phase comparator 2 compares the horizontal synchronizing signal HD of the frequency f _D with the frequency f _C input from the horizontal output circuit 6 side. The phases of the signals are compared, and an error signal corresponding to this phase difference is passed through the LPF 3 to the VCO 4
Is supplied to. Then, in the VCO 4, the oscillation frequency f _C is the frequency f _{D of the} horizontal synchronizing signal HD based on the error signal.
Control to match with. In this case, the frequency of the horizontal deflection current output from the horizontal driver unit 5 via the horizontal output circuit 6 is also f _C based on the oscillation frequency f _C of the VCO 4.
However, due to the feedback circuit as described above, P
When the LL circuit is locked, the oscillation frequency f _C of the VCO 4 is controlled so as to match the frequency f _D of the input horizontal synchronizing signal HD. Therefore, the frequency f _C of the horizontal deflection current output from the horizontal output circuit 6 is also output at the same frequency as the frequency f _D of the horizontal synchronizing signal HD.
That is, it is possible to obtain a deflection output having an appropriate horizontal deflection frequency corresponding to the input video signal.

[0004]

By the way, in recent years, not only television systems such as the standard NTSC system and the PAL system but also, for example, an EDT for displaying the current NTSC image by line double speed processing and non-interlaced display.
There is also known a V (Extended Definition TV) system and a double speed system such as so-called flicker-free, which performs field double speed processing in order to eliminate flicker in the PAL system. In addition, MUSE (Multiple Sub-Nyquist Samp
ling Encoding) has also started broadcasting. From such a background, television receivers and the like compatible with both the MUSE system and the NTSC system have been known. However, in such a device, it is transmitted to the NTSC system because of the deflection circuit. Video signal is standard system and ED
Displaying by a double speed processing method regardless of the TV method is also considered.

The horizontal deflection frequency in each of the above-mentioned systems is different, and is 15.734 KHz in the standard NTSC system and 15.625 K in the PAL system.
It becomes Hz. In addition, in the double speed system by the line double speed or field double speed based on NTSC and PAL including EDTV system and flicker-free system, each standard N
Since a horizontal deflection frequency twice that of the TSC and PAL systems is required, for example, the double speed system (EDT) based on the NTSC system is used.
(Including the V system), the horizontal deflection frequency is 15.734 × 2 = 31.468 KHz, which is double the standard NTSC system, and the double speed system based on the PAL system such as the flicker-free system has the standard PAL system.
The horizontal deflection frequency is 15.625 × 2 = 31.25 KHz, which is twice that of the system. Furthermore, in the MUSE method, 3
It is set to 3.75 KHz.

As described above, when various television systems have come to exist, it is advantageous in terms of cost if the horizontal deflection frequency generator is used in common regardless of the horizontal deflection frequency which is different for each system. However, in general, the PLL circuit has a range in which the range locked with the input frequency is VC.
It is limited by the sensitivity of O4, and becomes unstable when designed to have a wide lock range. Further, although a VCO using a crystal oscillator or the like as an oscillating element has high stability, a lock range is narrowed and a horizontal deflection frequency generation circuit capable of supporting all of the horizontal deflection frequencies of various television systems as described above should be formed. Becomes difficult.
Therefore, for example, the configuration of the horizontal deflection frequency generation circuit shown in FIG. 3 can basically support only one type of horizontal deflection frequency. For example, the VCO 4 can be freed depending on the horizontal deflection frequency for each television system. It is difficult to standardize the horizontal deflection frequency generation circuit because it is necessary to prepare a changed run frequency setting.

Further, in the case of a television receiver which is compatible with both the above-mentioned MUSE system and NTSC system,
In the mode for displaying the NTSC image, as described above, the horizontal deflection frequency of 31.468 KHz, which is double the standard, is
At least a horizontal deflection frequency of 33.75 KHz is required in the mode for displaying the E system image. However, since the horizontal deflection frequency between the NTSC double-speed system and the MUSE system is relatively large, in the case of the horizontal deflection frequency generation circuit having the configuration shown in FIG. If the loop of the PLL circuit is set to lock, the horizontal deflection frequency of the other method cannot be locked outside the pull-in range for the reason described above. Therefore, by changing the free-run frequency of the VCO 4 shown in FIG. 3 according to the switching of the MUSE and NTSC modes, the horizontal deflection frequency corresponding to both methods can be obtained by one horizontal deflection frequency generating circuit. I was doing.

However, as the switching of the free-run frequency of the VCO 4, specifically, for example, the time constant of an adjusting component such as a capacitor and a resistor that can be adjusted from the outside is adjusted and set. Therefore, a considerable number of man-hours are required to adjust the constants of the adjustment parts, and the absolute value accuracy of the adjustment parts, the temperature characteristics, and the variation over time must be taken into consideration, and its design is difficult. This was a factor of lowering manufacturing efficiency and high cost.

[0009]

In view of the above-mentioned problems, the present invention considers at least the horizontal deflection frequencies of the standard system (NTSC and PAL), the EDTV system, the double speed system such as flicker-free, and the MUSE system. It is an object of the present invention to obtain a horizontal deflection frequency generating circuit that can generate the signal without adjusting the CR time constant. For this reason,
The free-run frequency f ₀ is: f ₀ = 86n × fH ₀ (n is a positive integer, fH ₀ is the standard NTSC system and the standard P
A voltage-controlled oscillator set to an intermediate frequency of each horizontal deflection frequency of the AL system), and at least 1 / 86n, 1
Frequency division ratios of / 43n and 1 / 40n can be switched,
A variable frequency divider that divides the oscillation output of the voltage controlled oscillator and outputs it, and a phase comparator that compares the phase difference between the horizontal synchronizing signal as a reference signal extracted from the video signal and the frequency division output of the variable frequency divider. And the voltage controller is controlled by the output of the phase comparator, and the oscillation frequency is varied so that the frequency of the divided output substantially matches the frequency of the horizontal synchronizing signal.

When the input video signal is the NTSC system or the PAL system, the frequency division ratio of the variable frequency divider is set to 1 / 86n, and in the case of the double speed display in the NTSC system or the PAL system, the frequency division ratio is 1. / 43n, MUS
In the case of the E method, the frequency division ratio of the variable frequency divider is set to 1 / 40n.

[0011]

According to the above construction, the horizontal deflection frequency of the standard NTSC system and the PAL system, the double-speed processed NTSC system and the PAL system, and the MUSE system can be set to one by simply variably setting the frequency division ratio of the variable frequency divider. It can be obtained with a horizontal deflection frequency generation circuit.

[0012]

1 is a block diagram showing an embodiment of a horizontal deflection frequency generating circuit according to the present invention. The same parts as those in FIG. In this embodiment, the VCO
A frequency divider 7 is provided in a stage subsequent to 4, and divides the oscillation output of the VCO 4 and supplies it to the phase comparator 2 as a comparison signal. A variable frequency divider 7 is provided. The variable frequency divider 7 can variably set the frequency division ratio by an external control signal, which will be described later. Reference numeral 8 denotes a controller. In this case, a control signal S _C is supplied to the variable frequency divider 7 based on an input command signal of a remote controller or the like or preset data set in advance to control the switching of the frequency division ratio. It can be performed. In this case, as shown by the broken line, the PLL circuit 9 is formed by the loop of the VCO 4, the variable frequency divider 7, the phase comparator 2 and the LPF 3. In this embodiment, the frequency-divided output of the variable frequency divider 7 supplied to the phase comparator 2 is branched as a horizontal deflection frequency signal and supplied to the horizontal driver unit 5, and the horizontal deflection is performed via the horizontal output circuit 6. The output is designed to be obtained.
According to the connection configuration of FIG. 3, in this embodiment, the horizontal driver section 5 and the horizontal output circuit 6 are inserted between the variable frequency divider 7 and the phase comparator 2 to form a PLL loop circuit. It is also possible to do so.

Next, the basic concept of this embodiment will be described with reference to FIG. In the present embodiment, as shown in this figure, with respect to the free-run frequency f ₀ of the VCO 4,
Standard NTSC horizontal deflection frequency (15.734
z) and the standard PAL horizontal deflection frequency (15.62).
5 KHz) intermediate frequency, for example, 15.68 KHz
The When _{fH O, f 0 = 86n ×} fH O ( where, n = positive integer) is set to be. The coefficient 86 set forth above formula, for example, the frequency fH of the horizontal deflection frequency intermediate NTSC and PAL format of the standard _O = 15.68KH
It is calculated based on z and a value approximate to the least common multiple of the MUSE horizontal deflection frequency of 33.75 KHz. Further, in the present embodiment, a ceramic oscillator having a relatively low Q is used for the piezoelectric vibrator 4a, so that horizontal deflection frequencies of both the NTSC system and the PAL system, which are based on the free-run frequency f ₀ , are drawn in, as described later. It has been made possible.

Then, in the variable frequency divider 7 of this embodiment, which divides the oscillation output of the VCO 4 and outputs it, 1/86
The frequency division ratios of n, 1 / 43n, and 1 / 40n are set to enable switching (note that n is a positive integer variable). In this variable frequency divider 7, the frequency division ratio is 1 / 86n.
If the frequency is set to, the frequency of the frequency division output (hereinafter referred to as the center frequency) fH ₁ obtained by the oscillation output of the VCO 4 corresponding to the free-run frequency f ₀ is: fH ₁ = f ₀ / 86n = 86n × fH _O / 86n = fH
_O words, fH ₁ = fH _O = 15.68KHz, and the center frequency fH ₁ Standard NTSC or PA
Since it is a frequency substantially in the middle of each horizontal deflection frequency of the L system, the PLL circuit 9 of the present embodiment has a horizontal deflection frequency related to the normal display of the NTSC and PAL systems by this frequency division ratio.
Can be locked.

Next, the center frequency fH ₂ which is the frequency division output when the frequency division ratio is switched to 1 / 43n is: fH ₂ = f ₀ / 43n = 86n × fH _O / 43n = 2f
H _O That is, fH ₂ = 2fH _O = 31.36 KHz, and the center frequency fH ₂ when the frequency division ratio is 1 / 43n
Is an intermediate frequency of each horizontal deflection frequency in the EDTV system (31.468 KHz) and the flicker-free system (31.25 KHz) that uses double speed frequencies of the NTSC system and the PAL system, and is used for displaying these systems. It can be locked to the horizontal deflection frequency.

Then, the horizontal deflection frequency of the MUSE method 3
When obtaining 3.75 KHz, (1 / 43n) × 1.08≈1 / 40n is set as the division ratio corresponding to this MUSE method. Specifically, if the frequency is divided by a frequency division ratio of 1 / 40n with respect to the free-run frequency f ₀ of the VCO 4, the frequency division output (center frequency) fH ₃ is fH ₃ = f ₀ / 40n = 86n × fH _O / 40n = 86
/ A 40fH _O. That is, a _{fH 3 = 86 / 40fH O =} 33.712KHz, a horizontal deflection frequency of the MUSE system 33.7
It is possible to obtain a center frequency close to 5 KHz, and it is possible to lock the center frequency on the MUSE horizontal synchronizing signal.

In this embodiment, as shown in FIG. 1, for example, the free running frequency f of the VCO 4 is specifically
₀ is set to n = 2 for the above variable n, that is, f ₀ = 86n × fH _O = 86 × 2 × 15.68≈2.7.
Set to MHz. The setting of the variable n may be determined according to, for example, the characteristics of the piezoelectric vibrator that is actually used. Along with this, the frequency division ratios 1 / 86n, 1 / 43n, and 1 / 40n in the variable frequency divider 7 are 1 / 86n = 1/86 × 2 = 1/172, respectively, as shown in the figure. It is set so that 1 / 43n = 1/43 × 2 = 1/86 1 / 40n = 1/40 × 2 = 1/80.

For example, in a television receiver equipped with the horizontal deflection frequency generating circuit shown in FIG. 1, when the mode for displaying a standard NTSC system or PAL system image is selected, the controller 8 is standard. Based on information such as a command signal indicating the mode of the system, control is performed so that the variable frequency divider 7 selects a frequency division ratio of 1/172 corresponding to the mode of the standard system. From the frequency division output with fH ₁ = 15.68 KHz as the center frequency. When the horizontal synchronizing signal (frequency 15.734 KHz) separated from the NTSC video signal is input to the phase comparator 2 as the reference signal, the PLL circuit 9 of the present embodiment shown in the broken line in the figure operates. By doing so, the oscillation frequency of the VCO 4 is controlled, and the variable frequency divider 7
The frequency of the signal output from is controlled to match the NTSC horizontal sync signal of 15.734 KHz. As a result, the horizontal output current is output from the horizontal output circuit 6 via the horizontal driver unit 5 in a cycle that properly corresponds to the NTSC video signal.

The phase comparator 2 uses PA as a reference signal.
Horizontal sync signal of L video signal (frequency 15.625KH
z) is input, 1/17 as above
Since the frequency division ratio of 2 is selected, the PLL circuit operates so that the output of the variable frequency divider 7 matches the center frequency of 15.68 KHz with the horizontal deflection frequency frequency of 15.625 KHz of the PAL system. Become.

As described above, in the present embodiment, the free-run frequency f ₀ is set on the basis of the frequency 15.68 KHz, which is approximately halfway between the horizontal deflection frequencies of the standard NTSC system and the PAL system. Both the horizontal deflection frequency of the PAL system and that of the PAL system are set within the pull-in range of the VCO 4, and the horizontal deflection frequency of both the standard NTSC and PAL systems can be generated by the division ratio of 1/172 as described above. it can. Therefore, in this embodiment, V
A ceramic oscillator having a relatively low Q in CO4 is used for the piezoelectric vibrator 4a. For example,
When such a ceramic oscillator is adopted, for example,
The PLL circuit 9 can be set within the pull-in range of ± 700 Hz with respect to the center frequency fH ₁ = 15.68 KHz of the variable frequency divider 7.

Also, the television receiver is NTSC / P
If the mode is the double speed display of AL (including EDTV system and flicker-free system), the controller 8
Thus, the variable frequency divider 7 selects a frequency division ratio of 1/86, and its center frequency fH ₂ = 31.36 KHz. When displaying a video signal that has been double-speed processed based on the NTSC system, the phase comparator 2 outputs the frequency 3
Since the horizontal synchronizing signal of 1.468 KHz is input as the reference signal, the PLL circuit 9 uses the above 31.468 KHz.
The oscillation frequency of the VCO 4 is controlled so that the signal of the frequency locked to is generated as the divided output.
Alternatively, in the mode in which the video signal subjected to the double speed processing based on the PAL system is displayed, the reference signal of the phase comparator 2 is a horizontal synchronization signal having a frequency of 31.25 KHz.
The PLL circuit 9 operates so that the frequency signal locked at 31.25 KHz can be obtained from the variable frequency divider 7. As described above, in this embodiment, regardless of whether the video signal of the NTSC double-speed system or the PAL double-speed system is supplied, the horizontal deflection frequency of both systems is changed by switching to the division ratio of 1/86. It can be generated without adjustment.

Next, when the television receiver is set to a mode for displaying a video signal of the MUSE system, the controller 8 switches the frequency division ratio of the variable frequency divider 7 to 1/80 and the variable frequency divider 7 The center frequency output from fH ₃ = 33.
It is set to be 712 KHz. Then, in the PLL circuit 9 of the present embodiment, the phase comparator 2 compares the horizontal deflection frequency (33.75 KHz) of the video signal of the MUSE system with the frequency division output of the variable frequency divider 7 to generate an error via the LPF 3. The signal is supplied to the VCO 4 as a signal, and the frequency division output of the variable frequency divider 7, that is, the horizontal deflection frequency signal supplied to the horizontal driver unit 5 is adjusted to VC at 33.75 KHz.
O4 controls the oscillation frequency.

As described above, in the present embodiment, one horizontal deflection frequency generation circuit is used, and the horizontal deflection frequency of the standard NTSC and PAL systems and the NTSC and PAL by the double speed processing are used.
It is possible to generate the horizontal deflection frequency of the video signal of the standard system and the horizontal deflection frequency of the MUSE system, and moreover, it is only necessary to switch the frequency division ratio of the variable frequency divider 7 under the control of the controller 8, and no particular adjustment is required. Absent.

The present invention is not limited to the configuration shown in FIG. 1, for example, and may be modified within the scope of the invention. For example, the output from the controller 8 automatically determines the characteristics of the display video signal. The control output may be supplied to the VCO 4 and the control output may be supplied. Further, in the case where another television system is developed in the future, the VCO 4 free-run frequency and This can be dealt with by setting the frequency division ratio of the variable frequency divider 7.

[0025]

As described above, the horizontal deflection frequency generation circuit of the present invention uses the standard NTSC and PAL systems and the double speed processing NTS while using one piezoelectric vibrator for the VCO.
Different horizontal deflection frequencies of the C and PAL systems and the MUSE system can be generated without adjustment only by controlling the switching of the frequency division ratio of the variable frequency divider.

As a result, for example, MUSE system and NTS
When the present invention is applied to a multi-system compatible television receiver that is compatible with both C-systems, CR (condenser, capacitor,
Since it is not necessary to change the free-run frequency itself by adjusting the time constant such as resistance, it is possible to improve the manufacturing efficiency and reduce the cost. Further, the horizontal deflection frequency generation circuit of the present invention can be commonly used for various models having different television systems if, for example, the frequency division ratio is switched to a required division ratio in advance and provided for a set. As a result, product management is facilitated, and manufacturing efficiency and cost reduction are similarly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a horizontal deflection frequency generation circuit as an embodiment of the present invention.

FIG. 2 is a diagram showing a basic concept of the embodiment.

FIG. 3 is a block diagram showing a configuration of a horizontal deflection frequency generation circuit as a conventional example.

[Explanation of symbols]

1 Sync separation circuit 2 Phase comparator 3 LPF 4 VCO 4a Piezoelectric vibrator (oscillator) 5 Horizontal driver section 6 Horizontal output circuit 7 Variable frequency divider 8 controller

Continuation of front page (56) Reference JP-A-5-183772 (JP, A) JP-A-4-233586 (JP, A) JP-A-6-311379 (JP, A) JP-A-6-35409 (JP , A) JP 6-70326 (JP, A) JP 4-328980 (JP, A) JP 6-232741 (JP, A) JP 6-77823 (JP, A) JP 6-78172 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 3/00-7/00

Claims (2)

(57) [Claims] 1. A free-run frequency f ₀ is f ₀ = 86n × fH ₀ (n is a positive integer, fH ₀ is a standard NTSC system and a standard P
The voltage-controlled oscillation means is set to a frequency substantially in the middle of each horizontal deflection frequency of the AL method, and at least 1 / 86n, 1 / 43n, and 1 / 40n frequency division ratios are switchable, and the voltage-controlled oscillation is performed. Variable dividing means for dividing and outputting the oscillating output of the means, phase comparison means for comparing the phase difference between the horizontal synchronizing signal as the reference signal extracted from the video signal and the divided output of the variable dividing means. And controlling the voltage control means by the output of the phase comparison means to vary the oscillation frequency so that the frequency of the divided output is substantially equal to the frequency of the horizontal synchronizing signal. Horizontal deflection frequency generation circuit. 2. In the NTSC system or the PAL system, the frequency division ratio of the variable frequency dividing means is set to 1 / 86n, and in the case of the double speed display in the NTSC system or the PAL system, the frequency division ratio of the variable frequency dividing means. Is 1 / 43n, and in the case of the MUSE system, the frequency division ratio of the variable frequency dividing means is 1 / n.
The horizontal deflection frequency generation circuit according to claim 1, wherein the horizontal deflection frequency generation circuit is 40 n.