JP3410922B2 - Clock control circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for controlling the timing of an external clock generated by a CPU and the timing of an internal clock used inside a memory (IC) using a delay array.

[0002]

2. Description of the Related Art In recent years, an increasing number of memories achieve high-speed data transfer by transferring data in synchronization with a clock. For example, synchronous DRAM
For clock-synchronous DRAMs such as
Data is exchanged with blocks such as a CPU in synchronization with the clocks of MHz and 250 MHz.

In a system for exchanging data between blocks in synchronism with such a clock, an external clock applied to a memory from a block such as a CPU and an internal clock generated inside the memory. There is a problem that a slight timing shift, that is, a skew occurs.

For example, when an external clock of 100 MHz is used, one cycle is 10 nsec (nanosecond). Therefore, when a deviation of 1 nsec occurs between the external clock and the internal clock, this deviation is 1 cycle time.
This corresponds to 0%, which hinders high-speed synchronous control.

In particular, when transferring data from the memory to another block, the skew of the external clock and the internal clock directly affects the data output time of the memory, and
Slow down the transfer time.

FIG. 48 shows an example of a system for performing synchronous control using a high speed clock. Also, FIG.
Shows the relationship between the external clock and the internal clock in the system of FIG.

An external clock CK generated by the CPU 12, for example, is input to a memory (clock synchronous DRAM such as a synchronous DRAM) 11. The external clock CK is supplied to the internal clock CL by the buffer 13.
K is converted to K, and the internal clock CLK is input to the input circuit 14,
It is supplied to the output circuit 15, the writing / reading circuit 16, etc., and controls the input / output operation of data.

The internal clock CLK is the external clock CK.
Since it is generated by the buffer 13 using as a trigger, there is necessarily a skew between the external clock CK and the internal clock CLK.

The internal clock CLK controls the internal operation of the memory 11. Therefore, when data is exchanged between the memory 11 and another block (such as the CPU 12), an external clock CK is used. It is necessary to set the timing in consideration of the skew between the internal clocks CLK.

However, as described above, the timing setting that allows for the skew delays the data transfer rate.

Therefore, recently, a technique for eliminating this skew has been developed. Two examples of this technology at the present time will be described below.

The first is a technique using a PLL (phase lock loop). In this technique, the width of the skew is detected by the PLL and the skew is set to zero. In addition, this technology uses a clock for the internal clock.
Since the feedback is applied, it is effective when the external clock given to the memory has a constant frequency and is not interrupted.

The second is a technique for forming a circuit for generating a corrected internal clock that matches the external clock based on a predetermined principle. This technology is very promising, as it can immediately respond to changes in the frequency of the external clock, even if the external clock is interrupted, and make them match. There is.

Therefore, the latter technique will be described in detail below.

First, the principle of this technique will be described with reference to FIG.

The skew width (delay amount) of the external clock CK and the internal clock CLK is D1, and the external clock CK
And the cycle of the internal clock CLK is T.

Here, the delay imitation pulse FCL is generated at the time when the time A has elapsed from the time when the first pulse of the internal clock CLK was generated (at the time of rising). In this case, the time from when the delay imitation pulse FCL is generated to when the second pulse of the internal clock CLK is generated is Δ.

Further, this time Δ is copied so that the delay imitation pulse RCL is generated at the time (2 × Δ) after the time when the delay imitation pulse FCL is generated. Then, the time when the time A has elapsed from the time when the delay imitation pulse RCL is generated coincides with the time when the third pulse of the internal clock CLK is generated.

However, (A + W) <T. W is the width of the delay imitation pulses FCL and RCL.

If the time from the time when the delay imitation pulse RCL is generated to the time when the third pulse of the external clock CK is generated is D2, the delay imitation pulse RCL
By delaying time D2, a corrected internal clock CK 'that matches the timing of the external clock CK can be obtained.

That is, a delay circuit for generating the delay amounts A, (2 × Δ) and D2 is formed, and the internal clock CLK is set to the time.
By delaying by A + (2 × Δ) + D2, the corrected internal clock CK ′ that matches the timing of the external clock CK can be obtained.

As is apparent from FIG. 50, A = D
Since the relationship of 1 + D2 exists, the delay amount D2 is A
And D1.

Since the period T of the external clock CK and the internal clock CLK is not constant, the time Δ does not have a constant value either. Therefore, the time (2
The delay circuit that generates xΔ) must be configured to be able to accurately generate time (2 × Δ) according to the cycle T of the external clock CK and the internal clock CLK.

According to such a principle, the external clock C
The first pulse of the correction internal clock is always applied to the external clock CK regardless of the K and the cycle T of the internal clock CLK.
The third pulse can be matched. Also, after the third pulse of the external clock CK, the timing of the external clock CK and the timing of the corrected internal clock CLK are the same, so even if the external clock CK is interrupted, it is immediately Correspondingly, it becomes possible to match the external clock with the internal clock.

Next, a circuit configuration for matching the timings of the external clock and the internal clock based on the above principle will be examined.

FIG. 51 shows an example of the circuit configuration.

The external clock CK is input to the input buffer 22 via the input terminal 21. Internal clock CL
K is output from the input buffer 22. Here, since the input buffer 22 has the delay amount D1, the delay amount D1 is provided between the external clock CK and the internal clock CLK.
Minute skew occurs.

The internal clock CLK is input to the forward delay array 24 via the delay circuit 23 having the delay amount A. The forward delay array 24 is composed of a plurality of delay circuits 25-1, 25-2 to 25-n having a delay amount d.

The mirror control circuit 26 includes a delay circuit 25-
It has control elements 27-1, 27-2, to 27-n corresponding in number to 1,25-2 to 25-n. The mirror control circuit 26 has a function of determining the delay amount Δf in the forward delay array 24 and making the delay amount Δb in the backward delay array 28 equal to the delay amount Δf.

The backward delay array 28 is the forward delay array 2
4, the plurality of delay circuits 29- each having the delay amount d
1, 29-2 to 29-n.

The clock output from the backward delay array 28 passes through the delay circuit 30 having the delay amount D2 to become the corrected internal clock CK 'having the timing that matches the timing of the external clock CK.

In the circuit having the above configuration, the forward delay array 24
And the configuration of the backward delay array 28 are the same, and the forward pulse delay amount Δf is copied as it is to obtain the backward pulse delay amount Δb, which is 2Δ (Δf = Δb = Δ).

However, in the circuit having the above configuration, it is difficult to completely match the forward pulse delay amount Δf and the backward pulse delay amount Δb due to the forward pulse having a constant pulse width. There are drawbacks.

This drawback will be described.

FIG. 52 shows the circuit state of FIG. 51 at the time t in FIG. 50 (that is, the time when the delay amounts Δf and Δb are determined).

Here, the state in which the forward pulse is input to the delay circuit of the forward delay array is in the active state (shown by diagonal lines).
Then, the state in which the forward pulse is not input to the delay circuit of the forward delay array is deactivated. In this case, for example, when the forward pulse is input to the delay circuit 25-k, the delay circuit 25-k becomes active and the other delay circuits become inactive.

When a pulse of the internal clock CLK is generated after the forward pulse is input to the delay circuit 25-k, the delay circuit 29-k of the backward delay array is activated and the delay circuit 29-k outputs the backward pulse. Occur.

That is, since the forward pulse and the pulse of the internal clock CLK are input to the k-th control element 27-k from the head of the delay array, the control element 27-k is the delay circuit 29- of the backward delay array. The k is activated and the backward pulse is generated from the delay circuit 29-k.

However, in this case, the position from the beginning of the delay circuit 29-k to which the forward pulse is input is the same as the position from the beginning of the delay circuit 29-k that generates the backward pulse.

Therefore, the forward pulse front F1 that determines the delay amount Δf and the backward pulse front F2 that determines the delay amount Δb inevitably have a delay amount corresponding to one stage of the delay circuit (for example, the forward pulse pulse). Only the width W) will be different. That is, in the circuit having the configuration of FIG. 51, the maximum delay amount Δb is shorter than the delay amount Δf by the delay amount of one stage of the delay circuit.

[0041]

As described above, the prior art is as follows.
In the technique of forming a circuit that generates a corrected internal clock that matches an external clock based on a predetermined principle, it was not possible to configure a circuit that accurately copies a predetermined delay amount. It was difficult to match the clock exactly.

The present invention has been made to solve the above-mentioned drawbacks, and an object thereof is to provide a predetermined delay in a technique for forming a circuit for generating a corrected internal clock that matches an external clock based on a predetermined principle. To construct a circuit that can copy the quantity accurately so that the corrected internal clock is exactly matched to the external clock.

Another object of the present invention is to have a fixed phase relationship with an external clock based on a predetermined principle.
That is, it is to provide a circuit for generating a corrected internal clock whose phase is delayed by a predetermined amount with respect to the external clock.

[0044]

In order to achieve the above object, the delay array of the present invention comprises a plurality of delay units connected in series, each delay unit transmitting a forward pulse by a predetermined delay amount. A forward pulse delay circuit that delays and transmits the delayed pulse to the subsequent delay unit, a backward pulse delay circuit that delays the backward pulse by the certain delay amount and transmits to the preceding delay unit, and a pulse of the internal clock to the plurality of delay units. Set to the set state when the forward pulse is input when not input, and to the reset state when the reverse pulse is input when the internal clock pulse is input to the plurality of delay units The forward pulse is input to the delay unit at the first stage, and the front edge of the backward pulse is When the pulse of the internal clock is input to the plurality of delay units, the state holding unit is formed of a delay unit closest to the first-stage delay unit among the delay units in the reset state, and the backward pulse is the first-stage delay unit. Output from the unit.

The edges other than the front edge of the backward pulse are the first-stage delay units among the delay units whose state holding section is in the reset state when the internal clock pulse is no longer input to the plurality of delay units. Is formed by a delay unit close to.

The clock control circuit of the present invention comprises the delay array, a buffer having the delay amount D1 and generating an internal clock based on an external clock, and a pulse of the internal clock delayed by the delay amount A to advance the forward pulse. And a first delay circuit for supplying the delay unit at the first stage of the delay array, and a second delay circuit for delaying the backward pulse output from the delay unit at the first stage by a delay amount D2 and outputting the corrected internal clock. , The delay amount D1, the delay amount D2, and the delay amount A have a relationship of A = D1 + D2.

Further, in the clock control circuit of the present invention, within the period from the input of the pulse of the internal clock to the plurality of delay units of the delay array to the supply of the forward pulse to the delay unit of the first stage. , A control pulse generation circuit for generating a control pulse for initializing the forward pulse delay circuits of the plurality of delay units.

In the clock control circuit of the present invention, when the forward pulse is output from the delay unit at the final stage of the delay array, the reverse pulse output from the delay unit at the first stage is blocked, and the reverse pulse is output. There is provided means for controlling so that the pulse of the internal clock is output from the second delay circuit instead of the pulse.

The means outputs the second pulse based on a backward pulse output from the delay unit at the first stage after the pulse of the internal clock is output from the second delay circuit.
Initialize the delay circuit.

The delay array is arranged between the position where the buffer is arranged and the position where the second delay circuit is arranged. The pattern of the first delay circuit is similar to that of the buffer and the wiring from the buffer to the delay array, and the pattern of the second delay circuit and the delay array to the second delay circuit. Wiring pattern up to
Is laid out so as to be configured by a combination with a similar pattern.

The memory circuit of the present invention includes a memory cell array, a write / read circuit for writing or reading data to or from the memory cell array, and an input circuit for inputting the data from a bus. And an output circuit for outputting the data to the bus, and the clock control circuit. The operation of the write / read circuit is controlled by an internal clock output from the buffer of the clock control circuit. The operation of the input circuit or the output circuit is controlled by at least the corrected internal clock output from the second delay circuit of the clock control circuit.

The clock control system of the present invention has a bus, a control block for transmitting and receiving data to and from the bus and generating an external clock, and the memory circuit. And a memory block that receives and transmits the external clock.

The delay array of the present invention comprises a plurality of first and second delay units connected in series. Each of the first delay units delays the forward pulse by a fixed delay amount and transmits it to the subsequent delay unit, and a first backward pulse delay circuit that delays the forward pulse by the fixed delay amount and transmits it to the preceding delay unit. A first backward pulse delay circuit, and when the forward pulse is input when the internal clock pulse is not input to the plurality of first delay units, the internal clock pulse is set to the first state. When the first backward pulse is input to the plurality of first delay units, the state holding unit is set to the second state. Each second delay unit is composed of a second backward pulse delay circuit that delays the second backward pulse by the predetermined delay amount and transmits it to the preceding delay unit. The forward pulse is input to the first delay unit at the first stage, and the front edge of the first reverse pulse is stored in the second state when the pulse of the internal clock is input to the plurality of first delay units. First of
The delay unit is formed of a first delay unit closest to the first delay unit of the first stage, and the first backward pulse is output from the first delay unit of the first stage. The front edge of the second backward pulse is formed by a second delay unit corresponding to the first delay unit forming the front edge of the first backward pulse, and the second backward pulse is output from the second delay unit of the first stage. Is output. The first
The delay amount of the backward pulse delay circuit and the delay amount of the second backward pulse delay circuit are the same.

An edge other than the front edge of the first backward pulse is the most one of the first delay units whose state holding unit is in the second state when the pulse of the internal clock is no longer input to the plurality of first delay units. First of the first stage
It is formed by a first delay unit close to the delay unit.

The number of the first delay units and the number of the second delay units are different from each other. It is effective that the number of the second delay units is smaller than the number of the first delay units.

Of the plurality of first delay units, j first delay units that are continuous form one first block, and the continuous k of the plurality of second delay units is used.
A second block corresponding to the first block is composed of the second delay units, and the second delay unit is based on control pulses for controlling k operations of the j first delay units of the first block. To control the operation of the k second delay units of the second block. However, j and k are natural numbers that are relatively prime and j> k.

The first delay unit constitutes r (r is a natural number) blocks, the total number of the first delay units is n (= r × j), and the second delay unit is also The total number of the second delay units that constitute r blocks is m (= r × j), and the delay of the second backward pulse is when the delay amount of the first backward pulse is Δ. The quantity is (m / n) × Δ.

The clock control circuit of the present invention has the delay array described above, the delay amount D1, the buffer for generating the internal clock based on the external clock, and the pulse of the internal clock delayed by the delay amount A. A first delay circuit that supplies the first delay unit at the first stage as the forward pulse and the first backward pulse output from the first delay unit at the first stage are delayed by a delay amount (j−1) × D1 + j × D2. And a second delay circuit that outputs the second backward pulse output from the second delay unit of the first stage by a delay amount (k-1) × D1 + k × D.
And a third delay circuit which delays by 2 and outputs as a second corrected internal clock. However, j and k are natural numbers that are relatively prime and j> k.

The delay amount D1, the delay amount D2, and the delay amount A have a relation of A = j × (D1 + D2).

A clock control circuit according to the present invention has the above-mentioned delay array, a delay amount k × D1, a buffer for generating the internal clock based on an external clock, and a pulse of the internal clock for the delay amount A. A first delay circuit that delays the forward pulse and supplies it to the first delay unit of the first stage, and the first backward pulse output from the first delay unit of the first stage is a delay amount (j−k) × D1 + j × D.
A second delay circuit which delays by 2 and outputs as the first corrected internal clock, and the second backward pulse output from the first-stage second delay unit is delayed by the delay amount k × D2 and output as the second corrected internal clock. And a third delay circuit that operates. However, j and k are natural numbers that are relatively prime, and
j> k.

The delay amount D1, the delay amount D2 and the delay amount A have a relationship of A = j × (D1 + D2).

In the clock control circuit of the present invention, within the period from when the pulse of the internal clock is input to the plurality of first delay units to when the forward pulse is supplied to the first delay unit of the first stage, A control pulse generation circuit for generating a control pulse for initializing the forward pulse delay circuits of the plurality of first delay units is further provided.

The number of the first delay units and the number of the second delay units are different from each other. It is effective that the number of the second delay units is smaller than the number of the first delay units.

Of the plurality of first delay units, j consecutive first delay units form one first block, and the consecutive k of the plurality of second delay units are formed.
A second block corresponding to the first block is composed of the second delay units, and the second delay unit is based on control pulses for controlling k operations of the j first delay units of the first block. To control the operation of the k second delay units of the second block.

The first delay unit constitutes r (r is a natural number) blocks, the total number of the first delay units is n (= r × j), and the second delay unit is also The total number of the second delay units that make up the r blocks is m (= r × j).

The second backward pulse delay circuit includes the first backward pulse delay circuit.
The delay amount generated by the backward pulse delay circuit is m / n (= k /
j) Generate the delay amount.

The j is 2, the k is 1, and the second backward pulse delay circuit of the second delay unit has a delay amount generated by the first backward pulse delay circuit of the first delay unit. Produces half the delay amount of.

The k is 1, and the second backward pulse delay circuit of the second delay unit delays by 1 / j of the delay amount generated by the first backward pulse delay circuit of the first delay unit. Produce a quantity.

The memory system of the present invention is the same as the input capacity of the plurality of memories with respect to the plurality of memories, the controller controlling the plurality of memories, and the external clock output from the controller. A dummy memory having an input capacity and a delay time of the external clock from the controller to the plurality of memories are arranged to be equal to a delay time of the external clock from the controller to the dummy memory. A first wiring, a data bus for guiding data from one of the plurality of memories to the controller based on an internal clock having a constant phase relationship with the external clock; Second wiring for returning the external clock given to the dummy memory to the controller as a return clock.

The delay time of the data from one of the plurality of memories to the controller and the delay time of the return clock from the dummy memory to the controller are equal. And, the controller takes in the data based on the return clock.

The clock control circuit of the present invention receives the internal clock delayed by D1 from the external clock, and outputs the forward pulse after the delay time A has elapsed from the input of the internal clock. And a second delay circuit that delays the forward pulse by 2 × Δ and outputs a backward pulse, and the backward pulse is input, and a delay time (j−1) × D1 + j after the backward pulse is input.
And a third delay circuit that outputs a corrected internal clock whose phase matches that of the external clock after the passage of × D2. Here, j is a natural number, Δ is the time from the occurrence of the forward pulse to the first occurrence of the internal clock pulse, and A is j × (D1 + D2).

The clock control circuit of the present invention receives the internal clock delayed by m × D1 from the external clock,
A first delay circuit that outputs a forward pulse after a delay time A has elapsed from the input of the internal clock; and a second delay circuit that delays the forward pulse by 2 × Δ and then outputs a backward pulse. , The backward pulse is input, and the delay time (j−k) × D1 + after the backward pulse is input.
a third delay circuit that outputs a corrected internal clock whose phase matches the external clock after j × D2 has elapsed. However, j and k are natural numbers that are relatively prime, and j
≧ k, Δ is the time from the occurrence of the forward pulse to the first occurrence of the internal clock pulse, and A is j
X (D1 + D2).

In the clock control circuit of the present invention, the internal clock delayed by D1 from the external clock is input, and the first delay circuit which outputs the forward pulse after the delay time A has elapsed after the internal clock was input. And a second delay circuit that delays the forward pulse by Δ + (k / j) × Δ and then outputs a backward pulse, the backward pulse is input, and a delay time (k −
1) × D1 + k × D2, and a third delay circuit for outputting a corrected internal clock whose phase is delayed by (k / j) × T with respect to the external clock. However,
j and k are mutually prime natural numbers, j ≧ k and Δ are the times from the occurrence of the forward pulse to the first occurrence of the internal clock pulse, A is j × (D1 + D2), T
Is the period of the external clock.

The clock control circuit of the present invention receives the internal clock delayed by k × D1 from the external clock,
After a delay time A has elapsed since the internal clock was input, a first delay circuit that outputs a forward pulse and a forward pulse that outputs the backward pulse after delaying the forward pulse by Δ + (k / j) × Δ A second delay circuit, the backward pulse is input, and the delay time k × D after the backward pulse is input.
After 2 has passed, the phase is (k
/J).times.T, and a third delay circuit for outputting a corrected internal clock. However, j and k are natural numbers that are relatively prime, and j ≧ k and Δ are, after the forward pulse is generated,
First, A is j × (D1 + D2), and T is the period of the external clock until the pulse of the internal clock is generated.

[0075]

BEST MODE FOR CARRYING OUT THE INVENTION The clock control circuit of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows an example of a synchronous control system including a memory block having a clock control circuit of the present invention.

An external clock CK generated by the CPU 12, for example, is input to the memory (clock synchronous DRAM such as synchronous DRAM) 11. The external clock CK is supplied to the internal clock CL by the buffer 13.
Converted to K. The internal clock CLK is supplied to the writing / reading circuit 16 and controls the data writing / reading operation.

The internal clock CLK is the external clock CK.
Since it is generated by the buffer 13 using as a trigger, there is necessarily a skew between the external clock CK and the internal clock CLK.

The clock control circuit 31 uses the internal clock C.
Based on LK, a corrected internal clock CK 'that matches the timing of the external clock is generated. The corrected internal clock CK ′ is supplied to the input circuit 14 and the output circuit 15,
It controls the input / output operation of data.

FIG. 2 shows the configuration of the clock control circuit 31 in the memory 11 of FIG.

The external clock CK is applied to the input terminal 3 of the memory.
Given to 0. The external clock CK is input to the input buffer 13 having the delay amount D1. Input buffer 13
Outputs an internal clock CLK having a skew of D1 with respect to the external clock CK. Internal clock CLK
Is input to the delay circuit 32 having the delay amount A, and the delay circuit 32 receives the forward pulse FCL1 (delay imitation pulse CL).
Is output.

Internal clock CLK and internal clock C
The inverted internal clock / CLK obtained by inverting LK by the inverter 35 has n delay units 33-1 and 3-3, respectively.
3-2, ..., 33-n.

The n delay units 33-1, 33-2,
33-n are connected to each other in series. The forward pulse FCL1 is input to the delay unit 33-1 in the first stage, and the backward pulse RCL1 is output from the delay unit 33-1 in the first stage.

The backward pulse RCL1 becomes the corrected internal clock CK 'by passing through the delay circuit 34 having the delay amount D2.

FIG. 3 shows the configuration of the delay unit of FIG. 2 in detail.

The delay unit 33-i is composed of three parts, a forward pulse delay circuit, a state holding circuit and a backward pulse delay circuit.

The forward pulse delay circuit is composed of three inverters 41-43. Inverters 41, 42
Are connected in series, the output signal FCLi of the preceding delay unit is input to the inverter 41, and the inverter 42 is connected.
Outputs the output signal FCLi + 1 to the delay unit in the subsequent stage. The operation of the inverter (clocked inverter) 41 is controlled by the control pulse / P. For example, when the control pulse / P is "1", the inverter 41 is activated.

The output terminal of the inverter 43 is connected to the input terminal of the inverter 42, and a potential of "0" (for example, ground potential) is always applied to the input terminal of the inverter 43. ing. The operation of the inverter (clocked inverter) 43 is controlled by the control pulse P. For example, when the control pulse P is "1", the inverter 43 is activated.

The backward pulse delay circuit is composed of three inverters 44 to 46. Inverters 44, 45
Are connected in series, and the inverter 44 outputs the output signal RCLi + 1 or the internal clock CLK of the delay unit in the subsequent stage.
Is input, the inverter 45 outputs the output signal RCLi to the delay unit at the previous stage. The operation of the inverter (clocked inverter) 44 is controlled by the control pulse Q. For example, the inverter 44 is activated only when the control pulse Q is "1".

The output terminal of the inverter 46 is connected to the input terminal of the inverter 45, and the internal clock CLK is always input to the input terminal of the inverter 46. The operation of the inverter (clocked inverter) 46 is controlled by the control pulse / Q. For example, when the control pulse / Q is "1", the inverter 46 is activated.

The state holding circuit includes a state holding unit 47 and NA.
It is composed of ND circuits 48 and 49. The output signal FCLi of the delay unit at the previous stage and the inverted internal clock / CLK are input to the NAND circuit 48, and the NAND circuit 4
9, the output signal of the inverter 45 and the internal clock C
LK is input.

The output signal of the NAND circuit 48 becomes the set input / S of the state holding unit 47, and the output signal of the NAND circuit 49 becomes the reset input / R of the state holding unit 47. Therefore, when the output signal (set input) / S of the NAND circuit 48 becomes “0”, the state holding unit 47 enters the set state, and the output signal (reset input) / R of the NAND circuit 49 becomes “0”. Then, the state holding unit 47 is in the reset state.

The state holding unit 47 is also configured to output the control pulses Q and / Q. The control pulse Q becomes "1" when the state holding unit 47 is in the set state, and the control pulse / Q becomes "1" when the state holding unit 47 is in the reset state.

FIG. 4 shows an example of the configuration of the state holding unit shown in FIG.

The P-channel MOS transistor 51 and the N-channel MOS transistors 53 and 54 are connected in series with each other, and the high potential VDD and the low potential VSS are applied to both ends thereof, respectively.

Similarly, the P-channel type MOS transistor 52 and the N-channel type MOS transistors 55 and 56 are provided.
Are connected in series with each other, and a high potential VD
D and low potential VSS are applied respectively.

The set input / S is the MOS transistor 5
Input to the gates 1, 54, reset input / R is M
It is input to the gates of the OS transistors 52 and 56.

The gate of the MOS transistor 53 is MO
It is connected to the drain of the S transistor 52, and the gate of the MOS transistor 55 is connected to the drain of the MOS transistor 51.

The control pulse Q is applied to the MOS transistor 51.
And the control pulse / Q is output from the drain of the MOS transistor 52.

FIG. 5 shows an example of the structure of the control pulse P, / P generating circuit.

The internal clock CLK is input to one input end of the NOR circuit 58 via the delay circuit 57 having the delay amount A ', and the inverted internal clock / CLK is input to the other input end of the NOR circuit 58. To be done. NOR circuit 58
Outputs a control pulse P. The control pulse P is
The control pulse becomes / P by passing through the inverter 59.

The pulse widths of the control pulses P and / P are determined by the delay amount A'of the delay circuit 57. However, this delay amount A ′ is set to be smaller than the delay amount A of the delay circuit 32 that outputs the delay imitation pulse. This is because it is necessary to initialize the forward delay circuits of all the delay units before the forward pulse is input to the delay unit at the first stage.

Next, the principle of the present invention will be confirmed with reference to FIG.

The width (delay amount) of the skew between the external clock CK and the internal clock CLK is set to D1, and the external clock CK
And the cycle of the internal clock CLK is T.

The delay imitation pulse FCL1 is generated when the time A elapses from the time when the first pulse of the internal clock CLK is generated (the time when it rises). In this case, the time from the generation of the delay imitation pulse FCL1 to the generation of the second pulse of the internal clock CLK is Δf.

Further, when the time 2 × Δ (however, Δf = Δb = Δ) elapses from the time when the delayed imitation pulse FCL1 is generated by copying this time Δf to produce Δb, the delayed imitation pulse RCL1 is generated. To occur. Then, the time when the time A elapses from the time when the delay imitation pulse RCL1 is generated coincides with the time when the third pulse of the internal clock CLK is generated. However, (A + W) <
Let T. W is the width of the delay imitation pulses FCL and RCL.

If the time from the time when the delay imitation pulse RCL1 is generated to the time when the third pulse of the external clock CK is generated is D2, if the delay imitation pulse RCL1 is delayed by the time D2, the external clock CK is delayed. A corrected internal clock CK 'that matches the timing is obtained.

That is, a delay circuit for generating the delay amounts A, (2 × Δ), and D2 is formed, and the internal clock CLK is timed.
By delaying by A + (2 × Δ) + D2, the corrected internal clock CK ′ that matches the timing of the external clock CK can be obtained.

Since the relationship of A = D1 + D2 exists, the delay amount D2 can be obtained from A and D1. The control pulse P is for initializing the forward delay circuits of all the delay units before the forward pulse is input to the delay unit at the first stage.

Next, the operation of the clock control circuit shown in FIGS. 2 to 5 will be described.

1. State of the timing chart of FIG. 7 at the time point “a” As shown in FIG. 8, the internal clock CLK becomes “1” (rises). Therefore, the output signal of the control pulse generation circuit 60 becomes P = “1”, / P = “0”, and the delay amount A
Control pulse P having a pulse width determined by
P is generated, and each delay unit 33-1, 33-2, ...
33-n.

Each delay unit 33-1, 33-2, ... 3
In 3-n, since P = “1” and / P = “0”, the inverter 43 is activated and the inverter 41 is activated.
Becomes inactive. Therefore, all delay units 33
The input / output signals FCL1 to FCLn of the forward pulse delay circuits -1, 33-2, to 33-n are all "0", and the line for transmitting the forward pulse is initialized.

After this, each delay unit 33-1 and 33-
In 2 to 33-n, when P = "0" and / P = "1", the inverter 41 becomes active and the inverter 43
Becomes inactive. That is, each delay unit 33-1
The forward pulse delay circuits 33-2 to 33-n are electrically connected to each other, and the input terminal of the forward pulse delay circuit of the delay unit 33-1 is electrically connected to the delay circuit 32 to forward the forward pulse. Ready for transmission.

The pulse width of control pulses P and / P (P
It is an essential condition that the period of "1" and / P of "0") is shorter than the period determined by the delay amount A of the delay circuit 32. Before the forward pulse (delay imitation pulse) FCL1 is input to the delay unit 33-1, it is necessary to initialize the forward pulse transmission lines of all the delay units 33-1, 33-2, to 33-n. Because there is.

2. As shown in FIG. 9 of the state of the timing chart of FIG. 7 at time point b, the internal clock CLK becomes "0" and the inverted internal clock / CLK becomes "1". Since the internal clock CLK and the inverted internal clock / CLK are common to all the delay units 33-1, 33-2, to 33-n, all the delay units 33-1 and 33-.
One input of the NAND circuits 48 of 2, to 33-n becomes "1".

On the other hand, each of the delay units 33-1 and 33-
The state holding units 47 of 2 to 33-n are in the reset state R, and the control pulse output from the state holding unit 47 is Q = “0” and / Q = “1”.

Therefore, each of the delay units 33-1 and 33-
The inverters 2 to 33-n are activated and the inverter 44 is deactivated to input / output the backward pulse delay circuits of all the delay units 33-1, 33-2, 33-n. The signals RCL1 to RCLn are all "0".

3. As shown in FIG. 10 of the state at the time point c of the timing chart of FIG. 7, the forward pulse (delay imitation pulse) FCL1 is output from the delay circuit (delay amount A) 32 and input to the delay unit 33-1. It is necessary to set the sum of the pulse width of the forward pulse (the period of “1”) and the period determined by the delay amount A to be shorter than the cycle T of the internal clock CLK.

When the forward pulse FCL1 (= "1") is input to the delay unit 33-1, the delay unit 33-1
The other input of the NAND circuit 48 becomes "1", and NA
The output (set input / S) of the ND circuit 48 becomes “0”. Therefore, the state of the state holding unit 47 changes to the set state S.

In the delay unit 33-1 in which the state holding unit 47 is in the set state S, the control pulse output from the state holding unit 47 is Q = “1”, / Q = “0”. -44 becomes active and the inverter 46
Becomes inactive.

4. D and e of the timing chart of FIG.
State of Time As shown in FIG. 11, the forward pulse is transmitted to the delay unit 33.
Proceed while sequentially passing through -1, 33-2, to 33-n.

Delay unit 33 that the forward pulse has passed
At -1, the other input of the NAND circuit 48 is again "0".
Therefore, the output of the NAND circuit 48 (set input / S) becomes “1”, but the state of the state holding unit 47 is maintained in the set state S.

Similarly, the forward pulse is delayed by the delay unit 33-
2 is input, the state holding unit 47 of the delay unit 33-2 changes to the set state S. Even if the forward pulse passes through the delay unit 33-2, the state holding unit 47 of the delay unit 33-2 maintains the set state S.

The internal clock CLK becomes "1" again,
When the inverted internal clock / CLK becomes "0", the internal clock CLK and the inverted internal clock / CLK are input to each of the delay units 33-1, 33-2, to 33-n.

Therefore, all delay units 33-1 and 3-3
One input of the NAND circuits 48 of 3-2 to 33-n becomes "0", and one input of the NAND circuit 49 becomes "1".

In the delay units 33-1 and 33-2 in which the state holding unit 47 is in the set state S, Q = "1" and the inverter 44 is in the active state. Therefore, the output of the backward pulse delay circuit is output. The signals RCL1 and RCL2 maintain the state of "0", but in the delay units 33-3 to 33-n in which the state holding unit 47 is in the reset state R, / Q = "1" and the inverter 46 operates. Since it is in the active state, the output signals RCL3 to RCLn of the backward pulse delay circuit become "1".

As a result, the front edge F2 of the backward pulse is formed.

Here, the front edge F2 of the backward pulse
When the internal clock CLK becomes “1”, the delay unit 33-3 to 33 in which the state holding unit is in the reset state R is
It is formed by the delay unit 33-3 located on the side of the delay unit 33-1 in the first stage of -n.

At this time, the front edge F1 of the forward pulse
Is considered to be located immediately before the delay unit 33-3, the front edge F1 of the forward pulse and the front edge F2 of the backward pulse coincide with each other.

Therefore, the forward pulse (delay imitation pulse) F
The time Δf from when CL1 is generated to when the pulse of the internal clock CLK is generated, and the internal clock CLK
After the pulse of (after the backward pulse)
The time Δb until the reverse pulse RCL1 is output and input to the delay circuit 34 becomes equal.

Thereafter, as shown in FIG. 12, the output signal of the control pulse generating circuit 60 is P = “1”, / P = “0”.
Therefore, control pulses P and / P having a pulse width determined by the delay amount A'are generated, and each delay unit 33-
1, 33-2, to 33-n.

Each delay unit 33-1, 33-2, to 3
In 3-n, since P = “1” and / P = “0”, the inverter 43 is activated and the inverter 41 is activated.
Becomes inactive. Therefore, all delay units 33
The input / output signals FCL1 to FCLn of the forward pulse delay circuits -1, 33-2 to 33-n all become "0", the forward pulse disappears, and the line for transmitting the forward pulse is initialized.

On the other hand, when the front of the backward pulse (= "1") is input to the delay unit 33-1, in the delay unit 33-2, the two inputs of the NAND circuit 49 are both "1". The output (reset input / R) of the NAND circuit 49 becomes “0”, and the state holding unit 47 changes to the reset state R (initialized).

Initialization (setting to the reset state R) of the state holding unit 47 of each delay unit is performed by the internal clock CLK.
Is performed only during the period of "1". That is, the internal clock C
This is because when the backward pulse (= “1”) is input when LK is “1”, both two inputs of the NAND circuit 49 become “1”.

Since the state holding unit 47 of each delay unit is initialized only during the period when the internal clock CLK is "1", the state holding units 47 of all the delay units are initialized, that is, reset state R is set. You may not be able to do this, but there is no particular problem. This is because it is clear that the next forward pulse will pass through the uninitialized delay unit 33-1.

5. The state of the timing chart of FIG. 7 at the time point f As shown in FIG. 13, the internal clock CLK becomes "0" and the inverted internal clock / CLK becomes "1". The internal clock CLK and the inverted internal clock / CLK are input to all the delay units 33-1, 33-2, to 33-n.

In addition, each delay unit 33-1 and 33-
In 2 to 33-n, since P = "0" and / P = "1", the inverter 41 becomes active and the inverter 4
3 becomes inactive. That is, each delay unit 33-
The forward pulse delay circuits 1, 33-2, to 33-n are electrically connected to each other, and the input end of the forward pulse delay circuit of the delay unit 33-1 is electrically connected to the delay circuit 32. The pulse is ready for transmission.

On the other hand, in the delay units 33-2 to 33-n whose state holding unit 47 is in the reset state R, / Q = "1" and the inverter 46 is in the active state. Therefore, when the internal clock CLK becomes "0", the state holding unit 47 sets the output signals RCL2 to RCLn of the delay units 33-2 to 33-n in the reset state R to "0" and forms the back edge of the backward pulse. To be done.

Therefore, the pulse width of the backward pulse is equal to or shorter than the period corresponding to the delay amount for one stage of the delay unit (the delay amount for two stages of the inverter).

If it is desired to make the pulse width of the backward pulse longer than the delay amount of one stage of the delay unit, as shown in FIG. 17, the other input of the NAND circuit 49 of the delay circuit 33-n is changed to the preceding stage. Output R of the delay circuit 33- (n-1) of
CLn-1 may be used. In this case, the maximum pulse width of the backward pulse is the delay amount (inverter) of two delay units.
This is a period corresponding to the delay amount of four steps).

In the delay unit 33-1 in which the state holding unit 47 is in the set state S, Q = “1”, and
Data 44 is active. Therefore, preparation for guiding the backward pulse to the delay circuit 34 via the delay unit 33-1 is completed.

6. As shown in FIG. 14 of the state of the timing chart of FIG. 7 at the time point g, the forward pulse (delay imitation pulse) FCL1 is output from the delay circuit (delay amount A) 32 and input to the delay unit 33-1. Forward pulse FCL1
When (= “1”) is input to the delay unit 33-1,
The other input of the NAND circuit 48 of the delay unit 33-1 becomes "1", and the output (set input / S) of the NAND circuit 48 becomes "0".

Therefore, when the state holding unit 47 of the delay unit 33-1 is in the set state, the state holding unit 47 maintains the set state S, and when the state holding unit 47 is in the reset state R, the state holding unit 47 holds the state. The part 47 changes to the set state S.

In the delay unit 33-1 in which the state holding unit 47 is in the set state S, the control pulse output from the state holding unit 47 is Q = “1”, / Q = “0”, so -44 becomes active and the inverter 46
Becomes inactive.

On the other hand, the reverse pulse is input to the delay unit 33-1 in the first stage, delayed by two stages of the inverter, and output from the delay unit 33-1 in the first stage.

7. The state of the timing chart of FIG. 7 at the time point “h” As shown in FIG.
Proceed while sequentially passing through -1, 33-2, to 33-n.

Delay unit 33 that the forward pulse has passed
At -1, the other input of the NAND circuit 48 is again "0".
Therefore, the output of the NAND circuit 48 (set input / S) becomes “1”, but the state of the state holding unit 47 is maintained in the set state S.

Similarly, the forward pulse is delayed by the delay unit 33-
2 is input, the state holding unit 47 of the delay unit 33-2 changes to the set state S. Even if the forward pulse passes through the delay unit 33-2, the state holding unit 47 of the delay unit 33-2 maintains the set state S.

On the other hand, the backward pulse is input to the delay circuit 34. The delay circuit 34 delays the backward pulse by the delay amount D2 to generate the pulse of the corrected internal clock CK '. The timing of the pulse of the corrected internal clock CK 'matches the timing of the pulse of the external clock CK.

8. The state at the time point i of the timing chart in FIG. 7 As shown in FIG.
And the inverted internal clock / CLK becomes "0",
Each delay unit 33-1, 33-2, to 33-n includes
The internal clock CLK and the inverted internal clock / CLK are input.

Therefore, all delay units 33-1 and 3-3
One input of the NAND circuits 48 of 3-2 to 33-n becomes "0", and one input of the NAND circuit 49 becomes "1".

In the delay units 33-1 and 33-2 in which the state holding unit 47 is in the set state S, Q = “1” and the inverter 44 is in the active state. Therefore, the output of the backward pulse delay circuit is output. The signals RCL1 and RCL2 maintain the state of "0", but in the delay units 33-3 to 33-n in which the state holding unit 47 is in the reset state R, / Q = "1" and the inverter 46 operates. Since it is in the active state, the output signals RCL3 to RCLn of the backward pulse delay circuit become "1".

As a result, the front F1 of the backward pulse is formed.

After that, the operations shown in FIGS. 12 to 16 are repeated.

According to the clock control circuit having the above-mentioned configuration, since each delay unit has the state holding unit, the time Δf from the generation of the delay imitation pulse (forward pulse) FCL1 to the generation of the pulse of the internal clock CLK is increased. Can be accurately copied to form Δb, and the backward pulse RCL1 can be input to the delay circuit 34 having the delay amount D2 after a time Δb (= Δf) from the generation of the pulse of the internal clock CLK.

Therefore, it becomes possible to generate the corrected internal clock CK 'which is accurately synchronized with CK to the external clock, and the data transfer using the high speed clock can be achieved. Further, the present invention is effective for a memory, such as a synchronous DRAM, in which an internal clock is temporarily interrupted and data is transferred in synchronization with a high-speed clock whose frequency changes.

FIG. 18 shows a modification of the clock control circuit of FIG.

This clock control circuit is different from the circuit of FIG. 2 in that a predetermined function is added to the delay circuit 34, and the other structure is the same as that of the circuit of FIG.

That is, in this embodiment, the external clock C
If K or the cycle T of the internal clock CLK is longer than a predetermined value, the process of adjusting the timing of the internal clock CLK to the timing of the external clock CK is not performed,
The input / output circuit of the memory is controlled by the internal clock CLK having a certain skew.

This is because when the frequency of the external clock CK is relatively low (long cycle), the skew itself does not cause much problem. This is also because the number of delay units forming the clock control circuit is not so large in relation to the occupied area on the memory chip.

The configuration of the circuit of this embodiment will be briefly described below.

The external clock CK is applied to the input terminal 3 of the memory.
Given to 0. The external clock CK is input to the input buffer 13 having the delay amount D1. Input buffer 13
Outputs an internal clock CLK having a skew of D1 with respect to the external clock CK. Internal clock CLK
Is input to the delay circuit 32 having the delay amount A, and the delay circuit 32 receives the forward pulse FCL1 (delay imitation pulse CL).
Is output.

Internal clock CLK and internal clock C
The inverted internal clock / CLK obtained by inverting LK by the inverter 35 has n delay units 33-1 and 3-3, respectively.
3-2, ..., 33-n.

The n delay units 33-1, 33-2,
33-n are connected to each other in series. The forward pulse FCL1 is input to the delay unit 33-1 in the first stage, and the backward pulse RCL1 is output from the delay unit 33-1 in the first stage.

When the period T of the external clock CK is less than the predetermined value (high speed clock), the backward pulse RCL1 is
The corrected internal clock CK ′ is obtained by passing through the delay circuit 34 having the delay amount D2. The timing of this corrected internal clock CK 'matches the timing of the external clock CK.

When the period T of the external clock CK is equal to or greater than the predetermined value, the backward pulse RCL1 is input to the delay circuit 34 having the delay amount D2, but is not output from the delay circuit 34. Instead, the internal clock CLK is output from the delay circuit 34. In this case, of course, the internal clock CLK has a certain skew with respect to the external clock CK, but this skew corresponds to the external clock C.
The amount is such that it does not matter much for the K cycle.

The control pulse generation circuit 61 outputs the output LST of the forward pulse delay circuit of the delay unit 33-n at the final stage.
And the control pulse L, / L is output based on the output RCL1 of the backward pulse delay circuit of the delay unit 33-1 in the first stage. Control pulses L and / L are corrected internal clock CK '
Is output or the internal clock CLK is output.

FIG. 19 shows the structure of the delay circuit 34 of FIG. 18 in detail.

The output RCL1 of the delay unit 33-1 is
It is input to one input terminal of the NAND circuit 64 via the delay circuit 62 and the inverter 63, and is directly input to the NA.
It is input to the other input terminal of the ND circuit 64. NAN
The output signals of the D circuit 64 are three inverters 65-67.
Then, the corrected internal clock CK 'is obtained.

The inverter 66 is a clocked inverter which becomes active when the control clock / L is "1". That is, when the control clock / L is "1",
Correct the internal pulse C by delaying the backward pulse by a fixed time.
When K'is generated and the control clock / L is "0", the backward pulse is cut off.

The internal clock CLK is input to the inverter 67 of the delay circuit 34 via the inverter 68. The inverter 68 is a clocked inverter that is activated when the control clock L is "1".
That is, when the control clock L is "1", the internal clock C
LK is led to the inverter 67, and the control clock L is "0".
At this time, the internal clock CLK is shut off.

FIG. 20 shows the control pulse generation circuit 6 of FIG.
1 shows the configuration of 1.

The output LST of the forward pulse delay circuit of the delay unit 33-n at the final stage is input to one input end of the NOR circuit 69, and the NOR circuit 72 is input to the other input end.
The output of is input. The output of the NOR circuit 69 is input to one input end of the NOR circuit 72, and the output of the NOR circuit 71 is input to the other input end.

The NOR circuit 71 has an output LST of the forward pulse delay circuit of the final delay unit 33-n and an output R of the backward pulse delay circuit of the initial delay unit 33-1.
Each of CL1 inverted by the inverter 70 is input.

Furthermore, the output of the NOR circuit 69 and the output obtained by delaying this output by the delay amount D3 by the delay circuit 74 are input to the NAND circuit 73, respectively.
The output of the NAND circuit 73 becomes the control clock L, and the control clock L inverted by the inverter 75 becomes the control clock / L.

The NAND circuit 73 and the delay circuit 74 have N
The rise of the control clock L is not delayed with respect to the output of the OR circuit 69, and only the fall of the control clock L is delayed by the delay amount D.
It is for delaying by 3 to surely extinguish the backward pulse in the delay circuit 34 and for initialization.

Next, the principle of the clock control circuit of FIGS. 18 to 20 will be briefly described with reference to FIG.

In FIG. 21, one cycle (cycle time) of the external clock CK becomes relatively long, and the maximum delay amount maxΔ by all the delay units is the time when the pulse of the internal clock CLK is generated from the time when the delay imitation pulse is generated. The timing chart is shown when the time becomes shorter than the time Δf.

The skew width (delay amount) of the external clock CK and the internal clock CLK is set to D1, and the external clock CK
Let T be the cycle of.

The delay imitation pulse FCL1 is generated when the time A elapses from the time when the first pulse of the internal clock CLK is generated (the time when it rises). In this case, the time from the generation of the delay imitation pulse FCL1 to the generation of the second pulse of the internal clock CLK is Δf.

However, the maximum delay amount that can be formed by all the delay units is maxΔ (<Δf). That is, since the maximum value of the delay amount that can be copied by the clock control circuit of the present invention is maxΔ, the delay imitation pulse RCL1 is generated when the time maxΔ has elapsed from the time when the second pulse of the internal clock CLK is generated. Therefore, the delay amount Δf cannot be copied accurately.

Therefore, even if the correction internal clock CK ′ is generated at the time when the time D2 has elapsed from the time when the delay imitation pulse RCL1 was generated, the timing of the correction internal clock CK ′ is deviated from the timing of the external clock CK. There is. Moreover, this gap is a skew that originally existed.
However, the performance of the memory is deteriorated.

The present embodiment is conceived to avoid such a phenomenon. In the embodiment of FIG. 2, when the time from the generation of the pulse of the internal clock CLK to the generation of the delay imitation pulse is A, and the maximum delay amount of all the delay units is maxΔ, A +
It is necessary to satisfy maxΔ ≦ T, but in the present embodiment, such a condition is not required.

Next, the operation of the clock control circuit of FIGS. 18 to 20 will be described with reference to the timing chart of FIG.

Since the operation when A + maxΔ ≦ T is satisfied is the same as the timing chart shown in FIG. 7, only the operation when A + maxΔ> T will be described below.

When the internal clock CLK becomes "1", P
= “1”, / P = “0”, and all delay units 3
All the input / output signals FCL1 to FCLn of the forward pulse delay circuits 3-1 to 33-2 to 33-n become "0", and the line for transmitting the forward pulse is initialized.

After that, when P = "0" and / P = "1", the forward pulse delay circuits of the delay units 33-1, 33-2, to 33-n are electrically connected to each other. The input end of the forward pulse delay circuit of the delay unit 33-1 is electrically connected to the delay circuit 32, and the preparation for transmission of the forward pulse is completed.

After the internal clock CLK becomes "0" and the inverted internal clock / CLK becomes "1", the forward pulse (delay imitative pulse) F is output from the delay circuit (delay amount A) 32.
CL1 is output and input to the delay unit 33-1.

When the forward pulse FCL1 (= "1") is input to the delay unit 33-1, the delay unit 33-1
The state of the state holding unit 47 is the set state S. Further, the forward pulse is transmitted to the delay units 33-1, 33-2,
~ 33-n is sequentially progressed. In the delay unit that has passed the forward pulse, the state of the state holding unit 47 is maintained in the set state S.

After that, the forward pulse passes through all the delay units 33-1, 33-2, to 33-n and is output from the delay unit 33-n as an output pulse LST (= "1").

The output pulse LST is input to the control pulse generation circuit 61. As a result, the control pulse generation circuit 61 generates a path switching signal of L = “1”, / L = “0”. That is, when the output pulse LST is output, L = “1” and / L = “0”, the delay circuit 34 is deactivated, and the delay circuit 34 outputs the correction internal signal that matches the timing of the internal clock CLK. The clock CK 'is output.

When the time maxΔ has elapsed after the internal clock CLK became "1" again, the delay unit 33-1 outputs the backward pulse RCL1. When the reverse pulse RCL1 is input to the control pulse generation circuit 61, the control pulse generation circuit 61 causes the reverse pulse RC
After the timing when L1 is output from the delay circuit 34, that is, after the backward pulse RCL1 disappears, L = “0”, /
A path switching signal of L = "1" is generated.

That is, the delay circuit 34 is initialized (activated).
Then, the delay circuit 34 changes to a state in which it can output the output signal RCL1 of the delay unit 33-1.

The delay circuit 62, the inverter 63 and the NAND circuit 64 determine the pulse width of the backward pulse output from the delay unit 33-1. That is, when the internal clock CLK is used for input / output control of the memory, after the backward pulse disappears in the delay circuit 34, L = “0”, /
The configuration is such that L = “1” and the delay circuit 34 is initialized (activated).

However, the delay amounts of the delay circuits 34, 62 and 74 are set so as to have the relationship of D3> D2 + D2 '.

According to the clock control circuit having the above configuration, the corrected internal clock C which is accurately synchronized with CK with the external clock is used.
It becomes possible to generate K ', and data transfer using a high speed clock can be achieved.

Further, in this embodiment, the external clock C
Depending on the frequency of K, it is possible to decide whether to use the internal clock CK as it is or to use the corrected internal clock CK ′ synchronized with the external clock CK.

That is, when data is transmitted / received in synchronization with a high speed clock in which the skew between the external clock CK and the internal clock CLK becomes a problem, the external clock C
The corrected internal clock CK 'synchronized with K is used, and the data is synchronized with the clock such that the skew does not cause a problem.
When sending and receiving data, the internal clock C
It is configured to use K.

Whether to use the internal clock or the corrected internal clock is determined by the number of delay units.

Therefore, when the period (cycle time) of the external clock CK is long, the situation in which the deviation between the external clock CK and the corrected internal clock CK 'becomes large does not occur.

FIG. 23 shows a layout when the clock control circuit of the present invention is arranged on a chip.

When the clock control circuit of the present invention is actually incorporated in the system as an IC, it is necessary to consider the delay caused by the wiring capacitance (wiring delay).

Therefore, first, an array of delay units (hereinafter, STBD, Synchronous Traced) is used.
Backwards Delay 80 is a distance (or wiring delay amount) from the input buffer 13 and a distance (or wiring delay amount) to the output buffer (delay circuit) 34.
Place them so that they are the same.

Next, the input buffer 13 and the STBD 80 are connected by a wire having a wire length L. Here, the actual skew D1 is the sum of the delay amount due to the input buffer 13 and the delay amount due to the wiring having the wiring length L.

Next, the delay circuit 32 having the delay amount A will be examined. The delay amount A is D1 + D2 as described above.
(See, for example, FIG. 6). The actual delay amount D2 of the delay circuit (output buffer) 34 is the sum of the delay amount of the output buffer 34 and the delay amount of the wiring having the wiring length L.

Therefore, the delay circuit having the delay amount A includes a pattern 82 whose left and right sides are reversed with respect to the pattern 81 forming the skew D1 and a pattern 8 forming the delay amount D2.
The same pattern 84 as that of No. 3 is used.

With such a layout, the delay amounts A, D1 and D2 can be determined in consideration of the wiring delay, so that the correction internal clock CK can be more accurately determined.
It is possible to synchronize ′ with the external clock CK.

As described above, the clock control circuit of the present invention has the following effects.

Since each delay unit has a state holding section, the time Δf from the generation of the delay imitation pulse (forward pulse) FCL1 to the generation of the pulse of the internal clock CLK is accurately copied to form Δb. However, time Δb (= Δf) has elapsed after the pulse of the internal clock CLK is generated.
The backward pulse RCL1 can be input to the delay circuit having the delay amount D2 later.

This state is schematically shown in FIGS.

That is, in the initial state, as shown in FIG. 24, the forward pulse delay circuit and the backward pulse delay circuit of the delay units 33-1 to 33-n are all in the state of outputting "0". There is.

Further, as shown in FIG. 25, the forward pulse is input to the delay unit 33-4, and the delay unit 33-
When the pulse of the internal clock CLK is generated after the state holding unit of No. 4 enters the set state S, the delay units 33-5 to 33-n whose state holding unit is in the reset state R output "1".

That is, the front pulse F1 of the forward pulse and the front F2 of the backward pulse coincide with each other, so that the delay amount Δf and the delay amount Δb are the same.

Thereafter, as shown in FIGS. 26 and 27,
The delay unit 33-4 is initialized to the reset state R,
Further, a backward pulse is formed, and the backward pulse passes through the delay units 33-3 and 33-2 and is delayed by the delay unit 33.
It is output from -1.

By such an operation, C is applied to the external clock.
It is possible to generate a corrected internal clock CK 'that is accurately synchronized with K, and it is possible to achieve data transfer using a high speed clock.

By monitoring the signal output from the final stage of the delay unit, the internal clock CK may be used as it is, depending on the frequency of the external clock CK.
Or corrected internal clock CK synchronized with external clock CK
It is possible to decide whether to use '.

In other words, when data is transmitted / received in synchronization with a high-speed clock in which the skew between the external clock CK and the internal clock CLK becomes a problem, the external clock C
The corrected internal clock CK 'synchronized with K is used, and the data is synchronized with the clock such that the skew does not cause a problem.
When sending and receiving data, the internal clock C
It is configured to use K.

Whether the internal clock or the corrected internal clock is used is determined by the number of delay units.

Therefore, when the cycle (cycle time) of the external clock CK is long, the situation in which the deviation between the external clock CK and the corrected internal clock CK 'does not become large will occur.

Further, paying attention to the point that the delay amount A is represented by (D1 + D2), and taking the wiring delay into consideration, the pattern of the delay amount A is used as the pattern forming the delay amounts D1 and D2. They are formed by the same pattern.

Therefore, the corrected internal clock CK 'can be accurately stored in the memory chip by the simplified layout.
It is possible to configure a system that synchronizes with the external clock CK.

The present invention is effective for a memory, such as a synchronous DRAM, in which an internal clock is temporarily interrupted and data is transferred in synchronization with a high-speed clock whose frequency changes. Is.

FIG. 28 shows the clock control circuit of FIG. 2 in a simplified form.

D1 is a delay circuit having a delay amount D1, D
2 is a delay circuit having a delay amount D2, A is a delay amount D1
Delay circuit with + D2, STBD (Synchronous Trac)
ed Backward Delay) is an array of delay units. STBD has FD (Forward Delay) and BD (Back
ward Delay).

According to the clock control circuit having such a configuration, as described above, the phase of the external clock CK and the phase of the internal clock CK 'completely match (skew is eliminated). Therefore, the clock control circuit having the above configuration is effective in the case of outputting data at the rising of the external clock CK (at the time of transition from "L" to "H").

On the other hand, in recent years, when the cycle of the external clock CK is set to T, in addition to the internal clock CK 'with no skew, the internal clock lagging the external clock CK by (k / j) × T It is required to accurately generate the clock CKD (k and j are natural numbers that are coprime and j> k).

For example, when outputting data at the rising and falling edges of the external clock CK, the internal clock CK 'whose phase matches the external clock CK and the phase of the external clock CK Is T
It is necessary to generate the internal clock CKD delayed by / 2 (= π).

In such a case, the internal clock CK
The phase of D is exactly T / 2 with respect to the phase of the external clock.
If it is not delayed by (= π), the data window at the time of data output (the period during which the data is fixed) becomes short, and there is a possibility that erroneous data will be output.

Therefore, in the following, the internal clock CK whose phase is delayed by (k / j) × T from the external clock CK will be described below.
A clock control circuit capable of accurately generating D will be described.

FIG. 29 shows a first example of the configuration of the clock control circuit of the present invention.

This clock control circuit uses the external clock C
With the internal clock CK 'whose phase matches K,
An internal clock CKD whose phase is delayed by T / 2 (= π) with respect to the external clock CK is generated (T is a cycle of the external clock).

The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 is
The internal clock CLK having the skew of D1 is output with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A, and the delay circuit 32
Outputs the delay imitation pulse CL (forward pulse FCL1).

The delay imitation pulse CL is equivalent to STBD (Synchr
FD (Forward Dela) of onous Traced Backward Delay
y) is entered. In the FD, after the delay imitation pulse CL advances by the delay amount Δ, BD (Backward Delay)
And a backward pulse is generated in HBD (Half Backward Delay).

The backward pulse RCL in the BD is output backward from the BD after being accurately advanced by the delay amount Δ. Also, H
The backward pulse HCL during BD travels exactly backward by the delay amount Δ / 2 and is then output from the HBD.

The internal clock CLK is input to BD and HBD, and determines the timing of generation of the backward pulse.
The inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 is input to the FD and controls the period (delay amount) in which the forward pulse advances.

The reverse pulse RCL has a delay amount D1 + (D2
When passing through the delay circuit 34 having x2), the corrected internal clock CK 'that matches the phase of the external clock CK is obtained. When the backward pulse HCL passes through the delay circuit 36 having the delay amount D2, the internal clock CK whose phase is delayed by T / 2 (= 180 °) with respect to the external clock CK.
It becomes D.

Here, the delay amount A of the delay circuit 32 is 2 ×
It is set to (D1 + D2).

FIG. 30 shows a second example of the configuration of the clock control circuit of the present invention.

This clock control circuit uses the external clock C
With the internal clock CK 'whose phase matches K,
Phase is T / j (= 2π / j) with respect to external clock CK
The internal clock CKD delayed by a certain amount is generated (T is the period of the external clock and j is a natural number).

The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 is
The internal clock CLK having the skew of D1 is output with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A, and the delay circuit 32
Outputs the delay imitation pulse CL (forward pulse FCL1).

The delay imitation pulse CL is STBD (Synchr
FD (Forward Dela) of onous Traced Backward Delay
y) is entered. In the FD, after the delay imitation pulse CL advances by the delay amount Δ, BD (Backward Delay)
And a backward pulse is generated at 1 / jBD (Backward Delay).

The backward pulse RCL in the BD is output backward from the BD after being correctly advanced by the delay amount Δ. Also, 1
The backward pulse 1 / jCL in / jBD is exactly the delay amount Δ
After moving backward by / j, it is output from 1 / jBD.

The internal clock CLK is BD and 1 / jB
It is input to D and determines the timing of generation of the backward pulse. The inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 is input to the FD and controls the period (delay amount) in which the forward pulse advances.

The backward pulse RCL has a delay amount (j-1) ×
When passing through the delay circuit 34 having D1 + j × D2, the corrected internal clock CK that matches the phase of the external clock CK
It becomes ´. Further, the backward pulse 1 / jCL is the delay amount D2.
Through the delay circuit 36 having
, The internal clock CKD is delayed in phase by T / j (= 360 ° / n).

Here, the delay amount A of the delay circuit 32 is j ×
It is set to (D1 + D2).

FIG. 31 shows a third example of the configuration of the clock control circuit of the present invention.

This clock control circuit uses the external clock C
With the internal clock CK 'whose phase matches K,
The phase is (k / j) × T (= 2) with respect to the external clock CK.
The internal clock CKD delayed by (π × k / j) is generated (T is the period of the external clock, k and j are coprime natural numbers, and j> k).

The external clock CK is input to the input buffer 13 having the delay amount k × D1. Input buffer 13
Outputs an internal clock CLK having a skew of k × D1 with respect to the external clock CK. Internal clock CL
K is input to the delay circuit 32 having the delay amount A, and the delay circuit 32 receives the delay imitation pulse CL (forward pulse FCL
1) is output.

The delay imitation pulse CL is STBD (Synchr
FD (Forward Dela) of onous Traced Backward Delay
y) is entered. In the FD, after the delay imitation pulse CL advances by the delay amount Δ, BD (Backward Delay)
And backward pulses are generated at k / jBD (Backward Delay).

The backward pulse RCL in the BD is output backward from the BD after being accurately advanced by the delay amount Δ. Also, k
The backward pulse k / jCL in / jBD is exactly the delay amount Δ
After moving backward by x (k / j), the data is output from k / j BD.

The internal clock CLK is BD and k / jB.
It is input to D and determines the timing of generation of the backward pulse. The inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 is input to the FD and controls the period (delay amount) in which the forward pulse advances.

The backward pulse RCL has a delay amount (j−k) ×
When passing through the delay circuit 34 having D1 + j × D2, the corrected internal clock CK that matches the phase of the external clock CK
It becomes ´. Further, the backward pulse k / jCL has a delay amount k ×
When passing through the delay circuit 36 having D2, the phase is T × (k / j) (= 360 ° × k /) with respect to the external clock CK.
The internal clock CKD is delayed by j).

Here, the delay amount A of the delay circuit 32 is j ×
It is set to (D1 + D2).

FIG. 32 shows a fourth example of the configuration of the clock control circuit of the present invention.

This clock control circuit uses the external clock C
With the internal clock CK 'whose phase matches K,
The phase is T × (k / j) (= 2 with respect to the external clock CK).
The internal clock CKD delayed by (π × k / j) is generated (T is the period of the external clock, k and j are coprime natural numbers, and j> k).

The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 is
The internal clock CLK having the skew of D1 is output with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A, and the delay circuit 32
Outputs the delay imitation pulse CL (forward pulse FCL1).

Delay imitation pulse CL is STBD (Synchr
FD (Forward Dela) of onous Traced Backward Delay
y) is entered. In the FD, after the delay imitation pulse CL advances by the delay amount Δ, BD (Backward Delay)
And backward pulses are generated at k / jBD (Backward Delay).

The backward pulse RCL in the BD is output backward from the BD after being accurately advanced by the delay amount Δ. Also, k
The backward pulse k / jCL in / jBD is exactly the delay amount Δ
After moving backward by x (k / j), the data is output from k / j BD.

The internal clock CLK is BD and k / jB.
It is input to D and determines the timing of generation of the backward pulse. The inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 is input to the FD and controls the period (delay amount) in which the forward pulse advances.

The backward pulse RCL has a delay amount (j-1) ×
When passing through the delay circuit 34 having D1 + j × D2, the corrected internal clock CK that matches the phase of the external clock CK
It becomes ´. The backward pulse k / jCL is a delay amount (k
−1) × D1 + k × D2 through the delay circuit 36, the phase is T × (k / j) with respect to the external clock CK.
Internal clock CKD delayed by (= 360 ° × k / j)
Becomes

Here, the delay amount A of the delay circuit 32 is j ×
It is set to (D1 + D2).

FIG. 33 shows a fifth example of the configuration of the clock control circuit of the present invention.

This clock control circuit uses the external clock C
With the internal clock CK 'whose phase matches K,
The phase is T / 4 (= 90 °) with respect to the external clock CK,
The internal clocks CKQ, CKH, and CK3Q delayed by T / 2 (= 180 °) and 3T / 4 (= 270 °) are respectively generated.

The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 is
The internal clock CLK having the skew of D1 is output with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A, and the delay circuit 32
Outputs the delay imitation pulse CL (forward pulse FCL1).

The delay imitation pulse CL is SAD (Synchron
FD (Forward Delay) of ous adjustable delay). For SAD, STBD (Synchronous Traced
Backward Delay), etc. are included.

In the FD, after the delay imitation pulse CL advances by the delay amount Δ, BD (Backward Delay), QB
D (Quarter Backward Delay), HBD (Half Backw
ardDelay) and 3QBD (3 Quarters Backward Delay)
), A backward pulse is generated respectively.

The backward pulse RCL in the BD is output from the BD after being moved backward by the delay amount Δ (X delay elements). Further, the backward pulse QCL in QBD is delayed by Δ /
After moving backward by 4 minutes (for X / 4 delay elements), the backward pulse HCL output from the QBD is the delay amount Δ.
/ 2 minutes (delay elements X / 2 pieces) move backward, then HBD
The reverse pulse 3QCL output from the 3QBD is output from the 3QBD after being advanced by a delay amount of 3Δ / 4 (3X / 4 delay elements).

The internal clock CLK is BD, QBD, H
It is input to BD and 3QBD, respectively, and determines the timing of generation of the backward pulse. The inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 is
The period (delay amount) in which the forward pulse is advanced in the FD.
To control.

The backward pulse RCL has a delay amount (D1 × 3 +
After passing through the delay circuit 34 having D2 × 4), the corrected internal clock CK ′ that matches the phase of the external clock CK is obtained.

When the backward pulse QCL passes through the delay circuit 36a having the delay amount D2, the external clock CK
The internal clock CKQ has a phase delayed by T / 4 (= 90 °) with respect to.

The reverse pulse HCL is delayed by the delay amount (D1
After passing through the delay circuit 36b having + D2 × 2), the internal clock CKH has a phase delayed by T / 2 (= 180 °) from the external clock CK.

Further, the backward pulse 3QCL passes through the delay circuit 36c having the delay amount (D1 × 2 + D2 × 3) and has a phase of 3T / 4 (= with respect to the external clock CK.
The internal clock CKD is delayed by 270 °).

Here, the delay amount A of the delay circuit 32 is 4 ×
It is set to (D1 + D2).

FIG. 34 shows the structure of the clock control circuit of FIG. 32 in detail.

The external clock CK is applied to the input terminal 3 of the memory.
Given to 0. The external clock CK is input to the input buffer 13 having the delay amount D1. Input buffer 13
Outputs an internal clock CLK having a skew of D1 with respect to the external clock CK. Internal clock CLK
Is input to the delay circuit 32 having the delay amount A, and the delay circuit 32 receives the forward pulse FCL1 (delay imitation pulse CL).
Is output.

Internal clock CLK and internal clock C
The inverted internal clock / CLK obtained by inverting LK by the inverter 35 is input to n (n is a natural number) delay units 33-1, 33-2, ... 33-n.

N delay units 33-1, 33-2,
33-n are connected to each other in series. The forward pulse FCL1 is input to the delay unit 33-1 in the first stage, and the backward pulse RCL1 is output from the delay unit 33-1 in the first stage.

N delay units 33-1, 33-2,
The control pulses P and / P output from the control pulse generation circuit 60 are input to 33-n. Also, the delay unit 3
3-i (i is 1 to n) outputs control pulses Qi and / Qi. The control pulse Qi, / Qi is k / jBD37
Entered in.

The backward pulse RCL1 has a delay amount (j-1).
The corrected internal clock CK ′ is obtained by passing through the delay circuit 34 having × D1 + j × D2.

The backward pulse k / jCL is the delay amount (k-
1) By passing through the delay circuit 36 having D1 + k × D2, the phase is T × (k
/ J) (= 360 ° × k / j), which is the internal clock CKD delayed.

FIG. 35 shows the first example of the configuration of the delay unit shown in FIG. 34 in detail.

The delay unit Ui (i = 1 to n) is composed of three parts of a forward pulse delay circuit, a state holding circuit and a backward pulse delay circuit.

The forward pulse delay circuit is composed of three inverters 41-43. Inverters 41, 42
Are connected in series, the output signal FCLi of the preceding delay unit is input to the inverter 41, and the inverter 42 is connected.
Outputs the output signal FCLi + 1 to the delay unit in the subsequent stage. The operation of the inverter (clocked inverter) 41 is controlled by the control pulse / P. For example, when the control pulse / P is "1", the inverter 41 is activated.

The output end of the inverter 43 is connected to the input end of the inverter 42, and the input end of the inverter 43 is always applied with a potential of "0" (for example, ground potential). ing. The operation of the inverter (clocked inverter) 43 is controlled by the control pulse P. For example, when the control pulse P is "1", the inverter 43 is activated.

The backward pulse delay circuit is composed of three inverters 44 to 46. Inverters 44, 45
Are connected in series, and the inverter 44 outputs the output signal RCLi + 1 or the internal clock CLK of the delay unit in the subsequent stage.
Is input, the inverter 45 outputs the output signal RCLi to the delay unit at the previous stage. The operation of the inverter (clocked inverter) 44 is controlled by the control pulse Qi. For example, the inverter 44 is activated only when the control pulse Qi is "1".

The output terminal of the inverter 46 is connected to the input terminal of the inverter 45, and the internal clock CLK is always input to the input terminal of the inverter 46. The operation of the inverter (clocked inverter) 46 is controlled by the control pulse / Qi, for example, the control pulse / Q.
When i is "1", the inverter 46 is activated.

The state holding circuit includes the state holding unit 47 and NA.
It is composed of ND circuits 48 and 49. The output signal FCLi of the delay unit at the previous stage and the inverted internal clock / CLK are input to the NAND circuit 48, and the NAND circuit 4
9, the output signal of the inverter 45 and the internal clock C
LK is input.

The output signal of the NAND circuit 48 becomes the set input / S of the state holding unit 47, and the output signal of the NAND circuit 49 becomes the reset input / R of the state holding unit 47. Therefore, when the output signal (set input) / S of the NAND circuit 48 becomes “0”, the state holding unit 47 enters the set state, and the output signal (reset input) / R of the NAND circuit 49 becomes “0”. Then, the state holding unit 47 is in the reset state.

The state holding unit 47 is also configured to output the control pulses Q and / Q. The control pulse Q becomes "1" when the state holding unit 47 is in the set state, and the control pulse / Q becomes "1" when the state holding unit 47 is in the reset state.

As the state holding unit 47, for example, the one having the configuration shown in FIG. 4 can be used.

In the delay unit Ui through which the forward pulse has passed, the control pulse Qi becomes "H" and / Qi becomes "L". On the other hand, in the delay unit Ui through which the backward pulse has passed, the control pulse Qi becomes "L" and / Qi becomes "H".

FIG. 36 shows the second example of the configuration of the delay unit shown in FIG. 34 in detail.

The delay unit Ui (i = 1 to n) is composed of three parts of a forward pulse delay circuit fdi, a state holding circuit sri and a backward pulse delay circuit bdi.

The forward pulse delay circuit fdi is composed of five inverters 91 to 95. Inverter 91
To 93 are connected in series, the output signal FCLi of the delay unit at the preceding stage is input to the inverter 91, and the inverter 91 is connected.
The output signal FCLi + 1 to the delay unit in the subsequent stage.
Is output. Inverter (Clocked Inverter) 91
Is controlled by the control pulse / P. For example, when the control pulse / P is "1", the inverter 91 is activated.

The output end of the inverter 94 is connected to the output end of the inverter 91, and the inverters 92,
The input terminal of the inverter 95 is connected to the input terminal of the inverter 94, and the input terminal of the inverter 94 is always applied with a potential of "0" (eg, ground potential). The operation of the inverter (clocked inverter) 94 is controlled by the control pulse P. For example, when the control pulse P is "1", the inverter 94 is activated.

The backward pulse delay circuit bdi is composed of five inverters 96-100. Inverter 9
6 to 98 are connected in series, the output signal RCLi + 1 of the delay unit in the subsequent stage or the internal clock CLK is input to the inverter 96, and the inverter 97 outputs the output signal RCLi to the delay unit in the previous stage. The operation of the inverter (clocked inverter) 96 is controlled by the control pulse Qi. For example, the inverter 96 is activated only when the control pulse Qi is "1".

The output terminal of the inverter 99 is connected to the output terminal of the inverter 96 and the inverters 97,
The internal clock CLK is always input to the input terminal of the inverter 99. The operation of the inverter (clocked inverter) 99 is controlled by the control pulse / Qi, for example, the control pulse / Qi.
When is "1", the inverter 99 is activated.

The state holding circuit sri is a P channel MOS.
It is composed of transistors 101 and 102, N-channel MOS transistors 103 and 104, and an inverter 105.

P-channel MOS transistors 101, 1
02 is connected in series between the power supply terminal and the node Z, and the N-channel MOS transistors 103 and 104 are connected in series between the ground terminal and the node Z.

The gates of the MOS transistors 101 and 104
The clock signal / CLK obtained by inverting the internal clock CLK is input to the gate of the MOS transistor 102.
Output signal of delay unit Ui-3 / RCLi-
3 is input, and the output signal FFCLi of the delay unit Ui-1 is input to the gate of the MOS transistor 103.

The input end of the inverter 105 is connected to the node Z, and the control pulse Qi-2 is output from the output end of the inverter 105. From node Z, control pulse /
Qi-2 is output.

FIGS. 37 and 38 show k / jBD of FIG.
An example of the configuration of is shown.

In this example, when k is 1 and j is 2, that is,
A case where the phase is delayed by T / 2 with respect to the external clock will be described. In this case, k / jBD is HBD (Half
Backward Delay).

The HBD is composed of m (m is a natural number) delay units bdi (i = 1 to m) connected in series. The configuration of each delay unit bdi is SAD (Sy
(nchronous Adjustable Delay) delay unit Ui has the same configuration as the backward pulse delay circuit bdi.

Therefore, the ratio of the delay amount of the backward pulse in BD to the delay amount of the backward pulse in HBD is the ratio of the number of delay units in BD to the number of delay units in HBD, more precisely, the delay of BD in one block. It is equal to the ratio of the number of units to the number of delay units of HBD.

Specifically, in this example, n delay units Ui (i = 1 to n) and m delay units bdi (i
= 1 to m) are equally divided into r (r is a natural number) blocks B (1), B (2), ... B (r).

For example, the block B (1) is composed of two delay units U1 and U2 and one delay unit bd1, and the control pulse Q1, / for controlling the delay unit U1.
Control pulses Q2 for controlling Q1 and the delay unit U2
Either one of / Q2 is given to the delay unit bd1.

Similarly, the block B (r) is composed of two delay units Un-1, Un and one delay unit bdm, and control pulses Qn-1, / Qn- for controlling the delay unit Un-1. 1 or one of the control pulses Qn and / Qn for controlling the delay unit Un is given to the delay unit bdm.

That is, in this example, one delay unit of HBD is provided for two delay units of SAD. Therefore, in BD, the backward pulse is delayed by Δ, whereas in HBD, the backward pulse is delayed by Δ.
It will be delayed by / 2.

In the case of this example, r and m are equal and m
= N / 2. Further, the natural numbers j and k that are relatively prime in the above description are often j = 2 (1
Equal to the number of SAD delay units in one block), k = 1 (equal to the number of HBD delay units in one block).

The total number n of SAD delay units is
j (2 in this example) × r, and the total number m of HBD delay units is k (1 in this example) × r.

Also, the delay units bd1 to bd of the HBD
It is preferable that m is evenly arranged with respect to the delay units U1 to Un of the SAD. That is, if one delay unit of the HBD is associated with two adjacent delay units of the SAD, the delay of Δ / 2 can be accurately generated.

FIG. 39 shows the delay unit b in the HBD.
An example of the configuration of di is shown.

In this example, the delay unit Ui shown in FIG. 35 is used. That is, since the backward pulse delay circuit of the delay unit Ui is composed of the three inverters 44 to 46, the delay unit bdi in the HBD is also
It is composed of three inverters 44'-46 '.

The inverters 44 'and 45' are connected in series, and the output signal HCLi + 1 of the delay unit in the subsequent stage or the internal clock CLK is input to the inverter 44 '.
The inverter 45 'outputs the output signal H to the delay unit in the preceding stage.
Output CLi. Inverter (Clocked Inverter
44 'is controlled by the control pulse Qi,
For example, only when the control pulse Qi is "1"
Switch 44 'is activated.

The output end of the inverter 46 'is connected to the input end of the inverter 45', and the internal clock CLK is always input to the input end of the inverter 46 '. The operation of the inverter (clocked inverter) 46 'is controlled by the control pulse / Qi. For example, when the control pulse / Qi is "1", the inverter 46' is activated.

FIG. 40 shows the delay unit bdi of FIG. 39 symbolically. Therefore, the circuit of FIG. 39 and the circuit of FIG. 40 show the same thing.

FIG. 41 shows an example of the structure of the k / j BD of FIG.

In this example, when j is 3 and k is 1, that is,
A case where the phase is delayed by T / 3 with respect to the external clock will be described.

The 1 / 3BD is composed of m delay units bdi (i = 1 to m) connected in series. The configuration of each delay unit bdi is SAD (Synchronous Ad
This is the same as the configuration of the backward pulse delay circuit bdi of the delay unit Ui of justable delay).

Therefore, the ratio of the delay amount of the backward pulse in BD to the delay amount of the backward pulse in 1/3 BD is BD
Is equal to the ratio of the number of delay units in 1/3 BD to the number of delay units in 1/3 BD, to be precise, the ratio of the number of BD delay units to the number of 1/3 BD delay units in one block.

Specifically, in this example, n delay units Ui (i = 1 to n) and m delay units bdi (i
= 1 to m), r blocks B (1), B (2), ...
It is evenly divided into B (r).

For example, the block B (1) is composed of three delay units U1 to U3 and one delay unit bd1, and the control pulse Q1, / for controlling the delay unit U1.
Q1 is given to the delay unit bd1. However, the control pulse for controlling the delay unit U2 or the delay unit U3 is replaced with the delay unit bd instead of the control pulse Q1, / Q1.
May be given to 1.

That is, in this example, one delay unit of 1 / 3BD is provided for three delay units of SAD. Therefore, in BD, the backward pulse is delayed by Δ, whereas in 1/3 BD, the backward pulse is delayed by Δ / 3.

In this example, r and m are equal and m
= N / 3. Further, the natural numbers j and k that are relatively prime in the above description are often j = 3 (1
Equal to the number of SAD delay units in one block), k = 1 (equal to the number of HBD delay units in one block).

Further, the total number n of SAD delay units is
j (3 in this example) × r, and the total number m of delay units of the HBD is k (1 in this example) × r.

Further, the delay units bd1 to 1/3 BD
The bdms should be evenly arranged with respect to the delay units U1 to Un of the SAD. That is, if one delay unit of 1/3 BD is associated with three adjacent delay units of SAD, a delay of Δ / 3 can be accurately generated.

FIG. 42 shows an example of the structure of the k / j BD of FIG.

In this example, when k is 2 and j is 3, that is,
A case where the phase is delayed by 2T / 3 with respect to the external clock will be described.

The 2 / 3BD is composed of m delay units bdi (i = 1 to m) connected in series. The configuration of each delay unit bdi is SAD (Synchronous Ad
This is the same as the configuration of the backward pulse delay circuit bdi of the delay unit Ui of justable delay).

Therefore, the ratio of the delay amount of the backward pulse in BD to the delay amount of the backward pulse in 2/3 BD is BD
Ratio between the number of delay units in the block and the number of delay units in the 2/3 BD, to be exact, the BD
The number of delay units is equal to the number of delay units of 2/3 BD.

Specifically, in this example, n delay units Ui (i = 1 to n) and m delay units bdi (i
= 1 to m), r blocks B (1), B (2), ...
It is evenly divided into B (r).

For example, the block B (1) is composed of three delay units U1 to U3 and two delay units bd1 and bd.
The control pulse Q1, / Q1 for controlling the delay unit U1 is applied to the delay unit bd1, and the control pulses Q3, / Q3 for controlling the delay unit U3 are applied to the delay unit bd2.

However, control pulses Q1, / Q1, Q3, /
Instead of Q3, control pulses Q1, / Q1, Q2, / Q2
May be applied to the delay units bd1 and bd2, or the control pulses Q2, / Q2, Q3 and / Q3 may be applied to the delay units bd1 and bd2.

That is, in this example, two delay units of 2 / 3BD are provided for the three delay units of SAD. Therefore, in BD, the backward pulse is delayed by Δ, whereas in 2/3 BD, the backward pulse is delayed by 2Δ / 3.

In the case of this example, there is a relation of m = 2n / 3. Further, the coprime natural numbers j and k that often appear in the above description are j = 3 (equal to the number of delay units of SAD in one block) and k = 2 (HBD delay in one block, respectively). Equal to the number of units).

Further, the total number n of SAD delay units is
j (3 in this example) × r, and the total number m of delay units of the HBD is k (2 in this example) × r. Also, m / n
= K × r / j × r, there is a relationship of m / n = k / j.

Also, 2/3 BD delay units bd1 to bd1
The bdms should be evenly arranged with respect to the delay units U1 to Un of the SAD. That is, if two delay units of 2 / 3BD are associated with three adjacent delay units of SAD, it is possible to accurately generate a delay of 2Δ / 3.

FIG. 43 generally shows the structure of the k / j BD of FIG. FIG. 44 shows the configuration of k / jBD in one block B (i) of FIG. 43.

SAD is composed of r blocks B (1) to B
(R). In SAD, each block contains j delay units. Similarly, k /
The jBD is composed of r blocks B (1) to B (r). In k / jBD, each block contains k delay units.

J and k are natural numbers that are relatively prime, and j
It is common to set> k. Since there are r blocks, the total number n of delay units of SAD is r × j
And the total number m of k / j BD delay units is r
× k.

The number of SAD blocks and the number of k / jBD blocks are equal. For example, the block B (1) of SAD is
The block (1) of k / jBD corresponds, the block B (2) of SAD corresponds to the block (2) of k / jBD,
The block B (r) of SAD corresponds to the block (r) of k / jBD.

For example, the block (1) of the SAD has j sets of control pulses Q1, / Q1, Q2, / Q2, ... Q.
j, / Qj. Therefore, only k (<j) sets of these j sets of control pulses are selected, and these k sets of control pulses are supplied to the block (1) of k / jBD.

The k sets of control pulses are the j sets of control pulses Q.
1, / Q1, Q2, / Q2, ... Qj, / Qj are regularly and evenly selected.

Also, the selected k sets of control pulses are k
/ JBD is regularly given to the corresponding k delay units. For example, control pulses Q1, / Q1, Q2, / Q
When 2 is selected, the control pulses Q1, / Q1 are set to k
/ JBD delay unit bd1 (not applied to bd2) and control pulses Q2 and / Q2 applied to k / jBD delay unit bd2 (not applied to bd1).

With such a configuration, the ratio of the number of delay units of SAD to the number of delay units of k / jBD is always k / j = m regardless of the position of the delay unit where the forward pulse of SAD arrives. / N is satisfied. Therefore, the delay amount of k / jΔ can be accurately generated in k / jBD regardless of the position of the delay unit reached by the forward pulse.

Next, the principle of the present invention (in the case of the example of FIG. 31) will be described with reference to FIG.

The skew width (delay amount) of the external clock CK and the internal clock CLK is k × D1, and the cycle of the external clock CK and the internal clock CLK is T.

The delay imitation pulse CL is generated at the time when the time A has elapsed from the time when the first pulse of the internal clock CLK was generated (at the time of rising). In this case, from the time when the delay imitation pulse CL is generated, the internal clock C
The time until the second pulse of LK is generated is Δ
f.

Further, this time Δf is copied to produce Δb, and time 2 × is obtained from the time when the delayed imitation pulse CL is generated.
The delay imitation pulse RCL is generated when Δ (however, Δf = Δb = Δ) has elapsed. Then, the time when the time A has elapsed from the time when the delay imitation pulse RCL is generated coincides with the time when the third pulse of the internal clock CLK is generated. However, (A + W) <T. W is the width of the delay imitation pulses CL and RCL.

When the time from the time when the delay imitation pulse RCL is generated to the time when the third pulse of the external clock CK is generated is (j−k) × D1 + j × D2, the delay imitation pulse RCL is time (j−k). ) × D1 + j × D2, a corrected internal clock CK ′ that matches the timing of the external clock CK can be obtained.

That is, the delay amount A, (2 × Δ), (j-
k) × D1 + j × D2 to form a delay circuit, and the internal clock CLK is time A + (2 × Δ) + {(j−
k) × D1 + j × D2}, the corrected internal clock CK ′ that matches the timing of the external clock CK can be obtained.

The delay amount (2 × Δ) is generated by SAD, and the delay amount (j−k) × D1 + j × D2 is generated by the delay element. The delay amount A is determined as follows.

From the relationship of FIG. 45,   k × D1 + A + Δ = T + k × D1 (1)   k × D1 + A + 2Δ + (j−k) × D1 + j × D2                             = 2T (2) Can lead.

From equation (1), T = A + Δ (3)
Can be derived, and from the formula (2), A + 2Δ + j (D1 + D2)
= 2T (4) can be derived.

From equations (3) and (4),   A + 2Δ + j (D1 + D2) = 2 (A + Δ)   A = j (D1 + D2) (5) Becomes

Further, with respect to the external clock CK, (k /
j) The principle that the internal clock CKD delayed by T is generated is as follows.

Time (k / j) × Δ (Δ = Δf = Δb) is created, and the time Δ from the time when the delayed imitation pulse CL is generated.
When + (k / j) × Δ has elapsed, the delayed pulse k / jC
Let L occur. Also, the delay pulse k / jCL
The internal clock CKD is generated at the time point when time k × D2 has elapsed from the time point at which the clock pulse occurred.

At this time, as apparent from FIG. 45, the internal clock CKD is delayed from the external clock CK by k × D1 + (k / j) × Δ + k × D2 (6).

Transforming equation (6),   (K / j) × (j × D1 + Δ + j × D2)       = (K / j) × {j (D1 + D2) + Δ} (7) Becomes

From the above equations (3) and (5), equation (7) is   (K / j) × T (8) Becomes

In other words, the internal clock CKD is delayed in phase from the external clock CK by (k / j) × T.

Therefore, the delay amount A, Δ + (k / j) × Δ,
The internal clock C is formed by forming a delay circuit for generating k × D2.
If LK is delayed by time A + {Δ + (k / j) × Δ} + k × D2, the phase is (k /
j) An internal clock CKD delayed by T will be obtained.

The delay amount Δ is generated by the FD of SAD, and the delay amount k × D2 is generated by the delay element. The delay amount A is set to j (D1 + D2) by the above method as shown in the equation (5).

Next, the principle of the present invention (in the case of the example of FIG. 32) will be described with reference to FIG.

The width (delay amount) of the skew between the external clock CK and the internal clock CLK is set to D1, and the external clock CK
And the cycle of the internal clock CLK is T.

The delay imitation pulse CL is generated when the time A has elapsed from the time when the first pulse of the internal clock CLK was generated (the time when it rises). In this case, from the time when the delay imitation pulse CL is generated, the internal clock C
The time until the second pulse of LK is generated is Δ
f.

Further, this time Δf is copied to create Δb, and time 2 × is generated from the time when the delayed imitation pulse CL is generated.
The delay imitation pulse RCL is generated when Δ (however, Δf = Δb = Δ) has elapsed. Then, the time when the time A has elapsed from the time when the delay imitation pulse RCL is generated coincides with the time when the third pulse of the internal clock CLK is generated. However, (A + W) <T. W is the width of the delay imitation pulses CL and RCL.

When the time from the time when the delay imitation pulse RCL is generated to the time when the third pulse of the external clock CK is generated is (j−1) × D1 + j × D2, the delay imitation pulse RCL is time (j−1). ) × D1 + j × D2, a corrected internal clock CK ′ that matches the timing of the external clock CK can be obtained.

That is, the delay amount A, (2 × Δ), (j-
1) A delay circuit for generating × D1 + j × D2 is formed, and an internal clock CLK is generated at time A + (2 × Δ) + {(j−
1) × D1 + j × D2}, the corrected internal clock CK ′ that matches the timing of the external clock CK can be obtained.

The delay amount (2 × Δ) is generated by SAD, and the delay amount (j−1) × D1 + j × D2 is generated by the delay element. The delay amount A is determined as follows.

From the relationship of FIG. 46,   D1 + A + Δ = T + D1 (9)   D1 + A + 2Δ + (j-1) × D1 + j × D2                             = 2T (10) Can lead.

From equation (9), T = A + Δ (1
1) is derived, and from the equation (10), A + 2Δ + j (D1 + D
2) = 2T (12) can be derived.

From equations (11) and (12),   A + 2Δ + j (D1 + D2) = 2 (A + Δ)   A = j (D1 + D2) (13) Becomes

Further, with respect to the external clock CK, (k /
j) The principle that the internal clock CKD delayed by T is generated is as follows.

Time (k / j) × Δ (Δ = Δf = Δb) is created, and the time Δ from the time when the delayed imitation pulse CL is generated.
When + (k / j) × Δ has elapsed, the delayed pulse k / jC
Let L occur. Also, the delay pulse k / jCL
The internal clock CKD is generated when a time (k−1) × D2 + k × D2 elapses from the time when is generated.

At this time, as is clear from FIG. 46, the internal clock CKD is delayed by D1 + (k / j) × Δ + (k−1) × D1 + k × D2 (14) with respect to the external clock CK. Will be there.

Transforming equation (14),   (K / j) × (j × D1 + Δ + j × D2)       = (K / j) × {j (D1 + D2) + Δ} (15) Becomes

Equation (15) becomes (k / j) × T (16) from the above equations (11) and (12).

That is, the internal clock CKD is delayed in phase from the external clock CK by (k / j) × T.

Therefore, the delay amount A, Δ + (k / j) × Δ,
The internal clock C is formed by forming a delay circuit for generating k × D2.
If LK is delayed by time A + {Δ + (k / j) × Δ} + k × D2, the phase is (k /
j) An internal clock CKD delayed by T will be obtained.

The delay amount Δ is generated by the FD of SAD, and the delay amount k × D2 is generated by the delay element. The delay amount A is set to j (D1 + D2) by the above-described method, as shown in Expression (13).

FIG. 47 shows the connection relationship between a controller which generates an external clock and receives data, and a memory which outputs data based on the internal clock generated from the external clock.

In the above-mentioned example, the technique of clearly determining the phase relationship between the external clock and the internal clock and outputting the correct data from the memory has been described. In this example, a technique in which the controller can accurately receive accurate data read from such a memory will be described.

Generally, the memory system includes a controller (CPU) and a plurality of memories (IC).
In addition, the external clock CK is transferred from the controller to the memory 1,
It takes a certain amount of time to reach 2. Therefore,
First, the wiring lengths of external clocks from the controller to the memories 1 and 2 are made equal.

Further, the memory 1 or memory 2 outputs data based on the internal clock having a fixed phase relationship with the external clock CK. The data is led to the controller via the data bus.

The controller receives the data from the memory 1 or the memory 2, but the data is output from the memory 1 or the memory 2 depending on the wiring length and the wiring capacity of the data bus, and the data is sent to the controller. It takes a certain amount of time to enter.

That is, since the controller fetches accurate data, it is necessary to fetch the data at a timing in consideration of the propagation time of the data on the data bus.

Therefore, a dummy memory (IC) having an external clock input capacity equal to that of the memories 1 and 2 is prepared.
The wiring length of the external clock from the controller to the dummy memory is made equal to the wiring length of the external clock from the controller to each of the memories 1 and 2.

The external clock CK input to the dummy IC is further returned to the controller and used as the return clock.

The return clock determines the timing at which the controller receives the output data of the memory 1 or memory 2. Therefore, the wiring length of the return clock from the dummy memory to the controller is made equal to the data bus length from the memory 1 or memory 2 to the controller.

As described above, the controller receives the data from the memory 1 or the memory 2 based on the return clock. Therefore, erroneous data will not be input to the controller.

[0393]

As described above, the clock control circuit of the present invention has the following effects.

It is possible to stably generate an internal clock that always has a constant phase relationship with the external clock, and even if the cycle of the external clock changes, the external clock does not change to the external clock at several cycles of the external clock. On the other hand, the internal clock always has a constant phase relationship.

Therefore, the present invention is most suitable for controlling the data input / output circuit of a clock synchronous DRAM such as a so-called synchronous memory.

The clock cycle is divided and the
In the case of outputting a plurality of data in one clock cycle by controlling to output the data, a plurality of internal clocks whose phases are exactly shifted by a predetermined amount with respect to the external clock are required. According to the present invention, such a plurality of internal clocks can be easily generated without using a complicated system such as a PLL.

[Brief description of drawings]

FIG. 1 is a diagram showing a main part of a system including a memory including a circuit of the present invention.

FIG. 2 is a diagram showing a configuration of a clock control circuit in the memory of FIG.

3 is a circuit diagram showing in detail a delay unit in the circuit of FIG.

4 is a circuit diagram showing in detail a state holding unit in the delay unit of FIG.

5 is a diagram showing the control pulse generating circuit in the circuit of FIG. 2 in detail.

FIG. 6 is a diagram showing the principle of the present invention.

FIG. 7 is a timing diagram showing the operation of the circuits of FIGS.

FIG. 8 is a diagram showing a state of “a” in the timing chart of FIG. 7.

9 is a diagram showing the state of b of the timing chart of FIG. 7. FIG.

10 is a diagram showing a state of c in the timing chart of FIG. 7. FIG.

11 is a diagram showing a state of d in the timing chart of FIG. 7. FIG.

FIG. 12 is a diagram showing a state of “e” in the timing chart of FIG. 7.

13 is a diagram showing a state of f in the timing chart of FIG. 7. FIG.

14 is a diagram showing a state of g in the timing chart of FIG. 7. FIG.

15 is a diagram showing a state of h in the timing chart of FIG. 7. FIG.

16 is a diagram showing a state of i in the timing chart of FIG. 7. FIG.

FIG. 17 is a diagram showing a modification of the circuit of FIG.

FIG. 18 is a diagram showing a modification of the circuit of FIG. 2;

19 is a diagram showing in detail the delay circuit in the circuit of FIG.

20 is a control pulse generation delay circuit 61 in the circuit of FIG.
The figure showing in detail,

FIG. 21 is a diagram showing a problem in the operation of the circuit of FIG.

FIG. 22 is a timing diagram showing the operation of the circuits of FIGS.

FIG. 23 is a diagram showing a layout when the circuit of the present invention is incorporated in a chip.

FIG. 24 is a diagram showing the operation of the circuits of FIGS. 2 and 18;

FIG. 25 is a diagram showing the operation of the circuits of FIGS. 2 and 18.

FIG. 26 is a diagram showing the operation of the circuits of FIGS. 2 and 18;

FIG. 27 is a diagram showing the operation of the circuits of FIGS. 2 and 18.

FIG. 28 is a diagram showing a schematic configuration of the clock control circuit of FIG. 2.

FIG. 29 is a diagram showing a first example of a clock control circuit of the present invention.

FIG. 30 is a diagram showing a second example of the clock control circuit of the present invention.

FIG. 31 is a diagram showing a third example of the clock control circuit of the present invention.

FIG. 32 is a diagram showing a fourth example of the clock control circuit of the present invention.

FIG. 33 is a diagram showing a fifth example of the clock control circuit of the present invention.

34 is a diagram showing the configuration of the clock control circuit of FIG. 1 in detail.

35 is a diagram showing in detail the configuration of the delay unit Ui in the circuit of FIG. 34.

FIG. 36 is a diagram showing in detail the configuration of the delay unit Ui in the circuit of FIG. 34.

FIG. 37 is a diagram showing a first example of a configuration of an HBD.

FIG. 38 is a diagram showing a second example of an HBD configuration.

39 is a diagram showing the configuration of the delay unit bdi of FIG. 37 or FIG. 38.

FIG. 40 is a diagram showing the circuit of FIG. 39 as a symbol.

FIG. 41 is a diagram showing a first example of a 1/3 BD configuration.

FIG. 42 is a diagram showing a second example of a 1/3 BD configuration.

FIG. 43 is a diagram showing a structure of an m / n BD.

FIG. 44 is a diagram showing the configuration of block B (i) in FIG. 43.

FIG. 45 is a diagram showing the principle of the present invention.

FIG. 46 is a diagram showing the principle of the present invention.

FIG. 47 is a diagram showing a configuration of a memory system of the present invention.

FIG. 48 is a diagram showing a main part of a conventional system.

FIG. 49 is a circuit diagram showing a skew of an external clock and an internal clock of the system of FIG. 48.

FIG. 50 is a diagram showing the principle of a synchronization system which is the basis of the present invention.

51 is a diagram showing an example of a circuit for achieving the principle of FIG. 50. FIG.

52 is a diagram showing how delay amounts Δf and Δb are determined in the circuit of FIG. 51.

[Explanation of symbols]

11: memory, 12: CPU, 13: buffer, 14: input circuit, 15: output circuit, 16: write / read circuit, 17: memory cell array, 18: data bus, 21: input terminal, 22: input buffer, 23, 25-1 to 25-n, 29-1 to 29-n, 30
: Delay circuit, 24: forward delay array, 26: mirror control circuit, 27-1 to 27-n: control element, 28: backward delay array, 31: clock synchronous delay control circuit, 32, 33-1 to 33-33. n, 34, 57, 62: delay circuit, 41 to 46, 59, 63, 66 to 68, 70: inverter, 47: state holding unit, 48, 49, 64: NAND circuit, 51, 52: P channel Type MOS transistors, 53 to 56: N-channel type MOS transistors, 58, 69, 71, 72: NOR circuit, 60, 61: control pulse generating circuit, 73: NAND circuit, 74: delay circuit, 75: inverter, 81-84: Circuit pattern.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ identification code FI H03L 7/00 G11C 11/34 354C 362S (56) References JP-A-9-238058 (JP, A) JP-A-8-237091 (JP, A) JP 9-186584 (JP, A) JP 10-126254 (JP, A) JP 10-145347 (JP, A) JP 10-254580 (JP, A) Kaihei 11-110062 (JP, A) JP 2000-194440 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 1/10 G06F 13/42 350 G11C 11/407 G11C 19/00 H03K 5/13 H03L 7/00

Claims (30)

(57) [Claims] 1. A forward pulse delay circuit comprising a plurality of delay units connected in series, each delay unit delaying a forward pulse by a certain delay amount and transmitting the forward pulse to a delay unit at a subsequent stage, and a backward pulse. A backward pulse delay circuit that delays the signal by a certain amount of delay and transmits it to the preceding delay unit, and a first state when the forward pulse is input when the internal clock pulse is not input to the plurality of delay units. And a state holding unit that is set to a second state when the backward pulse is input when the pulse of the internal clock is input to the plurality of delay units. is inputted to the delay unit, the front edge of the reverse pulse, the reverse pulse in pulse said plurality of delay units of said internal clock Late
The state holding unit is formed by a delay unit closest to the first-stage delay unit among the delay units in the second state when input to all the delay circuits, and the backward pulse is output from the first-stage delay unit. Delay array characterized by. 2. The delay array according to claim 1, wherein an edge other than a front edge of the backward pulse has a state holding unit in a second state when a pulse of the internal clock is no longer input to the plurality of delay units. A delay array formed of a delay unit closest to the first-stage delay unit among the delay units. 3. A delay array according to claim 1, and a delay amount D.
1 for generating an internal clock based on an external clock, and a pulse of the internal clock for delay amount A
And a second delay circuit that delays the forward pulse as a forward pulse to the delay unit at the first stage of the delay array and delays the backward pulse output from the delay unit at the first stage by a delay amount D2 and outputs the corrected internal clock. And a delay amount D1, the delay amount D2, and the delay amount A have a relationship of A = D1 + D2. 4. The plurality of delay units within the delay array according to claim 1, wherein the pulses of the internal clock are input to the plurality of delay units before the forward pulse is supplied to the first-stage delay unit. 4. The clock control circuit according to claim 3, further comprising a control pulse generating circuit for generating a control pulse for initializing the forward pulse delay circuit of the delay unit. 5. When the forward pulse is output from the delay unit at the final stage of the delay array according to claim 1, the backward pulse output from the delay unit at the first stage is cut off and replaced with the backward pulse. 4. The clock control circuit according to claim 3, further comprising means for controlling the pulse of the internal clock to be output from the second delay circuit. 6. The means initializes the second delay circuit based on a backward pulse output from the delay unit at the first stage after the pulse of the internal clock is output from the second delay circuit. The clock control circuit according to claim 5, wherein 7. The delay array according to claim 1, wherein the delay array is arranged midway between a position where the buffer is arranged and a position where the second delay circuit is arranged, and the pattern of the first delay circuit is the A pattern similar to the pattern of the buffer and the wiring from the buffer to the delay array, and a similar pattern to the pattern of the wiring from the second delay circuit and the delay array to the second delay circuit. The clock control circuit according to claim 3, wherein the clock control circuit is laid out so as to be configured by a combination with a clock signal. 8. A memory cell array, a write / read circuit for writing or reading data to or from the memory cell array, an input circuit for inputting the data from a bus, and the data. A clock control circuit according to claim 3, wherein the write / read circuit is controlled by an internal clock output from a buffer of the clock control circuit. The memory circuit is characterized in that the operation of the input circuit or the output circuit is controlled by at least a corrected internal clock output from the second delay circuit of the clock control circuit. 9. A bus and a control block for transmitting and receiving data to and from the bus and for generating an external clock.
9. A synchronous control system, comprising: the memory circuit according to claim 8; and a memory block for transmitting and receiving data to and from the bus and receiving the external clock. 10. A plurality of delay units connected in series, each delay unit having a constant forward pulse.
And delay it to the delay unit in the subsequent stage.
Forward pulse delay circuit and backward pulse to the fixed delay amount
Reverse pal that delays only by and transmits to the delay unit of the previous stage
A delay circuit and a state holding unit that is set to a first state by the forward pulse and is set to a second state by the backward pulse, and the forward pulse is input to a delay unit at the first stage and The front edge of the pulse is the pulse of the internal clock which is the backward pulse delay time in the delay units .
When input to all of the paths , the state holding unit is formed of a delay unit closest to the first-stage delay unit among the delay units in the second state, and the backward pulse is in a direction opposite to the traveling direction of the forward pulse. And a delay array which is output from the delay unit of the first stage. 11. A plurality of first and second parts connected in series
The first delay unit delays the forward pulse by a predetermined delay amount and transmits the forward pulse to the delay unit in the subsequent stage, and the first backward pulse delay unit delays the first backward pulse by the constant delay amount. A first backward pulse delay circuit for transmitting to a preceding delay unit; and a first state when the forward pulse is input when no internal clock pulse is input to the plurality of first delay units, A state holding unit that is set to a second state when the first backward pulse is input when the pulses of the internal clock are input to the plurality of first delay units, each second delay unit Is composed of a second backward pulse delay circuit that delays the second backward pulse by the predetermined delay amount and transmits it to the delay unit at the previous stage, wherein the forward pulse is at the first stage. Is input to the first delay unit, a front edge of said first rearward pulse, prepulse of the internal clock in the plurality of first delay units
The state holding unit is formed of the first delay unit closest to the first delay unit in the first stage among the first delay units in the second state when input to all of the first reverse pulse delay circuits. A pulse is output from the first delay unit of the first stage, and a pulse of the internal clock is output from the plurality of second delay units.
Input to all of the second backward pulse delay circuits in the
And the front edge of the second backward pulse is equal to the first edge of the first backward pulse.
A second delay unit corresponding to a first delay unit forming a front edge of the backward pulse, the second backward pulse is output from a second delay unit at the first stage, and the first backward pulse delay circuit and the first backward pulse delay circuit are provided. 2. The backward array pulse delay circuit has the same structure as the delay array. 12. The delay array according to claim 11, wherein edges other than the front edge of the first backward pulse are:
When the pulse of the internal clock is no longer input to the plurality of first delay units, the state holding unit is formed of a first delay unit closest to the first delay unit of the first stage among the first delay units in the second state. A delay array characterized by the following. 13. The delay array according to claim 11, wherein the number of the first delay units and the number of the second delay units are different from each other. 14. The delay array according to claim 11, wherein the number of the second delay units is smaller than the number of the first delay units. 15. The delay array according to claim 11, wherein j consecutive first delay units of the plurality of first delay units are included.
One first block is constituted by the delay units, and one second second block corresponding to the first block is constituted by the k consecutive second delay units of the plurality of second delay units.
A first block of the j blocks of the first block.
The operation of the k second delay units of the second block is controlled based on the control pulse that controls the operation of k of the delay units (where j and k are natural numbers that are coprime to each other, and , J> k). 16. The delay array according to claim 15, wherein the first delay unit comprises r (r is a natural number) blocks, and the total number of the first delay units is n (= r.
Xj), the second delay unit also constitutes r blocks, and the total number of the second delay units is m (=
r × j), and when the delay amount of the first backward pulse is Δ, the delay amount of the second backward pulse is (m /
n) × Δ, a delay array. 17. A delay array according to claim 11, a buffer having a delay amount D1, which generates the internal clock based on an external clock, and a pulse of the internal clock delayed by a delay amount A to advance the forward pulse. As a first delay circuit that supplies the first delay unit of the first stage and the first backward pulse output from the first delay unit of the first stage by delaying by a delay amount (j-1) × D1 + j × D2.
A second delay circuit for outputting as a corrected internal clock and the second backward pulse output from the first delay unit for the second stage are delayed by a delay amount (k−1) × D1 + k × D2 and output as a second corrected internal clock. And a third delay circuit (where j and k are natural numbers that are relatively prime, and
j> k. ), The delay amount D1, the delay amount D2, and the delay amount A have a relationship of A = D1 + D2. 18. A delay array according to claim 11, a buffer having a delay amount k × D1, generating the internal clock based on an external clock, and delaying a pulse of the internal clock by a delay amount A. A first delay circuit that supplies the first delay unit at the first stage as a forward pulse and the first backward pulse output from the first delay unit at the first stage are delayed by a delay amount (j−k) × D1 + j × D2. A second delay circuit for outputting as a first corrected internal clock;
And a third delay circuit for delaying the second backward pulse output from the first-stage second delay unit by a delay amount k × D2 and outputting it as a second corrected internal clock (however,
j and k are natural numbers that are relatively prime, and j> k. ), The delay amount D1, the delay amount D2, and the delay amount A have a relationship of A = D1 + D2. 19. The clock control circuit according to claim 17, wherein the pulse of the internal clock is input to the plurality of first delay units and the forward pulse is supplied to the first delay unit of the first stage. The clock control circuit further comprising a control pulse generation circuit that generates a control pulse for initializing the forward pulse delay circuits of the plurality of first delay units within a period. 20. The clock control circuit according to claim 18, wherein the number of the first delay units and the number of the second delay units are different from each other. 21. The clock control circuit according to claim 18, wherein the number of the second delay units is smaller than the number of the first delay units. 22. The clock control circuit according to claim 17, wherein j consecutive first delay units of the plurality of first delay units are provided.
One first block is constituted by the delay units, and one second second block corresponding to the first block is constituted by the k consecutive second delay units of the plurality of second delay units.
A first block of the j blocks of the first block.
A clock control circuit for controlling the operation of the k second delay units of the second block based on a control pulse for controlling the operation of k delay units. 23. The clock control circuit according to claim 22, wherein the first delay unit comprises r (r is a natural number) blocks, and the total number of the first delay units is n (= r.
Xj), the second delay unit also constitutes r blocks, and the total number of the second delay units is m (=
A clock control circuit characterized by being r × j) pieces. 24. The clock control circuit according to claim 23, wherein the second backward pulse delay circuit sets a delay amount of m / n (= k / j) of a delay amount generated by the first backward pulse delay circuit. A clock control circuit characterized by generating. 25. The clock control circuit according to claim 23, wherein j is 2, k is 1, and the second backward pulse delay circuit of the second delay unit is of the first delay unit. A clock control circuit for generating a delay amount that is half the delay amount generated by the first backward pulse delay circuit. 26. The clock control circuit according to claim 23, wherein k is 1 and the second delay unit has the second delay unit.
The backward pulse delay circuit generates a delay amount which is 1 / j of a delay amount generated by the first backward pulse delay circuit of the first delay unit. 27. An internal clock delayed by D1 from an external clock is input, and a first delay circuit that outputs a forward pulse after a delay time A has elapsed from the input of the internal clock, and the forward pulse. After being delayed by 2 × Δ, a second delay circuit that outputs a backward pulse and the backward pulse are input, and after a delay time (j−1) × D1 + j × D2 has elapsed since the backward pulse was input. , A third delay circuit that outputs a corrected internal clock whose phase matches the external clock (where j is a natural number, Δ
Is the time from the generation of the forward pulse until the first generation of the internal clock pulse, and A is j × (D1
+ D2). ) , The second delay circuit is
It consists of several delay units connected in series, each
The delay unit delays the forward pulse by a fixed amount.
Forward pulse delay circuit that transmits to the delay unit in the subsequent stage
And the backward pulse is delayed by the above-mentioned fixed delay amount,
Consists of a backward pulse delay circuit that transmits to the delay unit
And the internal clock is used in the delay units.
The clock control circuit is input to all the backward pulse delay circuits. 28. An internal clock delayed by m × D1 from an external clock is input, and a first delay circuit that outputs a forward pulse after a delay time A has elapsed from the input of the internal clock; A second delay circuit that outputs a backward pulse after delaying the pulse by 2 × Δ, the backward pulse is input, and a delay time (j−k) × D1 + j × D2 elapses after the backward pulse is input. Then, a third delay circuit that outputs a corrected internal clock whose phase matches the external clock (where j and k are natural numbers that are coprime, and j> k and Δ is the forward pulse is A is j * (D1 + D2), which is the time until the first pulse of the internal clock is generated.
And the second delay circuit includes a plurality of delay circuits connected in series.
Each delay unit is made up of
The delay is delayed by a fixed amount to the delay unit in the subsequent stage.
Forward pulse delay circuit to transmit and backward pulse to the constant
After delaying by the delay amount of
The internal clock is composed of a forward pulse delay circuit and
Is the backward pulse delay times in the plurality of delay units.
A clock control circuit characterized by being input to all of the paths . 29. An internal clock delayed by D1 from an external clock is input, and a first delay circuit that outputs a forward pulse after a delay time A has elapsed from the input of the internal clock, and the forward pulse. A second delay circuit that outputs a backward pulse after delaying by Δ + (k / j) × Δ, and the backward pulse is input, and the delay time (k−1) × D1 + k × after the backward pulse is input. After the passage of D2, the phase is (k / j) × with respect to the external clock.
A third delay circuit that outputs a corrected internal clock delayed by T (where j and k are natural numbers that are coprime, j> k,
Δ is the time from the generation of the forward pulse until the first generation of the internal clock pulse, and A is j × (D
1 + D2), T is the period of the external clock. ) , The second delay circuit includes a plurality of delay units connected in series.
Each delay unit has a forward pulse
Is delayed by a fixed amount and transmitted to the delay unit in the subsequent stage.
Forward pulse delay circuit and the backward pulse
Reverse power that is delayed by the total amount and transmitted to the delay unit in the previous stage
And a delay circuit.
All of the backward pulse delay circuits in a plurality of delay units
The clock control circuit is characterized in that it is input to the clock. 30. An internal clock delayed by k × D1 from an external clock is input, and a first delay circuit that outputs a forward pulse after a delay time A has elapsed since the internal clock was input; The pulse is Δ + (k / j) ×
A second delay circuit that outputs a backward pulse after delaying by Δ, and the backward pulse is input, and after a delay time k × D2 has elapsed after the backward pulse was input, a phase is generated with respect to the external clock. Is delayed by (k / j) × T and a third delay circuit that outputs a corrected internal clock (however,
j and k are mutually prime natural numbers, j> k, and Δ are the times from the occurrence of the forward pulse to the first occurrence of the internal clock pulse, and A is j × (D1 + D2), T
Is the period of the external clock. ), And the second
The delay circuit consists of multiple delay units connected in series.
Each delay unit is configured with a constant forward pulse.
Forward that is delayed by the delay amount and transmitted to the delay unit in the subsequent stage
Pulse delay circuit and backward pulse by the fixed delay amount
Reverse pulse delay that is delayed and transmitted to the preceding delay unit
And a circuit, the internal clock is
Input to all of the backward pulse delay circuits in the delay unit
Clock control circuit, characterized in that it is.