KR100292127B1 - Clock synchronous delay control circuit - Google Patents

Abstract

In a system that performs data transfer in synchronization with an internal clock, the internal clock is accurately synchronized with the external clock.

The external clock CK becomes the internal clock CLK having the skew D1 via the buffer 13. The internal clock CLK includes a delay circuit 32 having a delay amount A, delay unit arrays 33-1 to 33-n forming a delay amount 2xA and a delay amount D2 The internal clock signal CK 'becomes the corrected internal clock signal CK', and is synchronized with the external clock signal CK. Each delay unit has a state maintaining unit, and with respect to the delay unit passed by the forward pulse, the state holding unit is fixed to a predetermined state. Thus, a delay amount (2 x DELTA) is accurately formed.

Description

Clock synchronous delay control circuit

The present invention relates to a control circuit for controlling the timing of an external block generated by a CPU and the timing of an internal clock used in a memory (IC) using a delay array.

Recent memory is a trend of achieving high-speed data transfer by transferring data in synchronization with a clock. For example, in a clock synchronous DRAM such as a synchronous DRAM, data is exchanged with a block such as a CPU in synchronization with clocks of 100 MHz and 250 MHz, respectively.

In a system for exchanging data between blocks in synchronization with such a clock, there is a slight timing deviation between an external clock given to the memory from a block such as a CPU and an internal clock generated inside the memory, that is, skew skew) is generated.

For example, when an external clock of 100 MHz is used, since 1 cycle is 10 ns (nanosecond), if a 1 ns shift occurs between the external clock and the internal clock, this shift corresponds to 10% of one cycle time And interrupts the high-speed synchronous control.

Particularly, when data is transferred from a memory to another block, the skew of the external clock and the internal clock directly affects the data output time of the memory and delays the data transfer time.

FIG. 48 shows an example of a system for synchronous control using a high-speed clock. FIG. 49 shows the relationship between the external clock and the internal clock in the system of FIG. 48.

An external clock CK generated by, for example, the CPU 12 is input to a memory (a clock synchronous type DRAM such as a synchronous DRAM). The external clock CK is converted into an internal clock CLK by the buffer 13 and the internal clock CLK is supplied to the input circuit 14, the output circuit 15, the write / read circuit 16 And controls input and output operations of data.

Since the internal clock CLK is generated by the buffer 13 as the trigger of the external clock CK, there is inevitably skew between the external clock CK and the internal clock CLK.

Since the operation of the internal memory 11 is controlled by the internal clock CLK, when data is exchanged between the memory 11 and other blocks (CPU 12, etc.), the external clock CK) and the internal clock (CLK).

However, as described above, the timing setting considering skew delays the data transmission speed.

Therefore, in recent years, development of techniques for eliminating skew has been progressing. Hereinafter, two examples of the present technology at the present time will be described.

The first is a technology that uses PLL (phase lock loop). This technique detects the skew width by the PLL and sets the skew to zero. This technique is effective when the external clock applied to the memory always has a constant frequency because it feeds back the internal clock.

The second is a technique for constructing a circuit for generating a corrected internal clock that coincides with an external clock, based on a predetermined circle. This technique is extremely promising because even if the frequency of the external clock changes and the external clock is interrupted, the external clock and the internal clock can be matched with each other instantaneously.

Therefore, the latter technique will be described in detail.

First, with reference to FIG. 50, the principle of this technique will be described.

The skew width (delay amount) of the external clock CK and the internal clock CLK is D1 and the cycle of the external clock CK and the internal clock CLK is T. [

Here, a delayed imitation pulse FCL is generated at a point of time A elapsing from the time when the first pulse of the internal clock CLK is generated (time of rising). In this case, the time from the generation of the delayed impulse pulse FCL to the generation of the second pulse of the internal clock CLK is DELTA

Further, this delay time DELTA is copied, and a delayed imitation pulse RCL is generated at the time point when the time (2xA) has elapsed from the point of time at which the delayed imitation pulse FCL is generated. Then, the time point at which the time A has elapsed from the point in time at which the delayed imitation pulse RCL is generated coincides with the time point at which the third pulse of the internal clock CLK is generated.

(A + W) < T. And W is the width of delay imitation pulses FCL and RCL.

Here, let D2 be the time from when the delay imitation pulse RCL is generated to when the third pulse of the external clock CK is generated. If the delay imitation pulse RCL is delayed by the time D2, The corrected internal clock CK 'that coincides with the timing of the clock signal CK can be obtained.

That is, if a delay circuit for generating the delay amounts A, 2, and D2 is formed and the internal clock CLK is delayed by the time [A + (2xA) + D2] It is possible to obtain the corrected internal clock CK 'that matches the timing.

Since there is a relation of A = Dl + D2 as apparent from the 50th road, the delay amount D2 can be obtained from A and D1.

Since the period T of the external clock CK and the internal clock CLK is assumed to be not constant, the time? Does not have a constant value. Therefore, the delay circuit for generating the time (2 x DELTA) must be configured so as to accurately generate the time (2 x DELTA) according to the period T of the external clock CK and the internal clock CLK .

According to this principle, regardless of the period T of the external clock CK and the internal clock CLK, the first pulse of the corrected internal clock CLK always coincides with the third pulse of the external clock CK . Further, after the third pulse of the external clock CK, the timing of the external clock CK and the timing of the corrected internal clock CLK coincide with each other. Therefore, even when the external clock CK is interrupted in the middle, So that the external clock and the internal clock can be matched with each other.

Next, a circuit configuration for matching the timing of the internal clock with the timing of the external clock based on the above principle will be examined.

FIG. 51 shows an example of the circuit configuration.

The external clock CK is input to the input buffer 22 via the input terminal 21. The internal clock (CLK) is output from the input buffer (22). Here, since the input buffer 22 has the delay amount D1, a skew of the delay amount D1 occurs between the external clock CK and the internal clock CLK.

The internal clock CLK is input to the forward delay array 24 via the delay circuit 23 having the delay amount A. [ The forward delay array 24 is composed of a plurality of delay circuits 25-1, 25-2, ..., and 25-n having a delay amount d.

The mirror control circuit 26 has the number of control elements 27-1, 27-2, ..., 27-n corresponding to the number of the delay circuits 25-1, 25-2, ..., 25-n have. The mirror control circuit 26 determines the delay amount? F in the forward delay array 24 and sets the delay amount? B in the backward delay array 28 equal to the delay amount? F .

Like the forward delay array 24, the backward delay array 28 is composed of a plurality of delay circuits 29-1, 29-2, ..., 29-n having a delay amount d.

The clock output from the backward delay array 28 becomes the corrected internal clock CK 'having the timing coinciding with the timing of the external clock CK by passing through the delay circuit 30 having the delay amount D2 .

In the circuit having the above-described configuration, the delay amount? F of the forward pulse is copied as it is by making the configuration of the forward delay array 24 and the configuration of the backward delay array 28 the same as the delay amount? B of the backward pulse , 2? (? F =? B =?).

However, in the above-described circuit, since the forward pulse has a constant pulse width, there is a problem that it is difficult to completely match the delay amount? F of the forward pulse and the delay amount? B of the backward pulse.

This problem will be described

FIG. 52 shows the circuit state of FIG. 51 at the time point t of the 50th degree (that is, the time point at which the delay amounts? F and? B are determined).

Here, the state in which the forward pulse is input to the delay circuit of the forward delay array is set to an active state (indicated by an oblique line), and the state in which the forward pulse is not input to the delay circuit of the forward delay array is made inactive. In this case, for example, when a forward pulse is input to the delay circuit 25-k, the delay circuit 25-k becomes active and the other delay circuit becomes inactive.

When the pulse of the internal clock CLK is generated after the forward pulse is inputted to the delay circuit 25-k, the delay circuit 29-k of the backward delay array becomes active and the delay circuit 29- Generates a backward pulse.

That is, since the pulse of the forward pulse and the internal clock (CLK) are inputted to the kth control element 27-k from the head of the delay array, the control element 27-k is connected to the delay circuit 29- k to an active state, and generates a backward pulse from the delay circuit 29-k.

However, in this case, the position from the head of the delay circuit 29-k to which the forward pulse is inputted is the same as the position from the head of the delay circuit 29-k which generates the backward pulse.

Therefore, the front F1 of the forward pulse for determining the delay amount? F and the front F2 of the backward pulse for determining the delay amount? B necessarily have a delay amount of one delay circuit , The pulse width (W) of the forward pulse). That is, in the circuit having the configuration of FIG. 27, there is a problem that the delay amount? B becomes shorter than the delay amount? F by the delay amount of one stage of the maximum delay circuit.

As described above, conventionally, in the technique of constructing the circuit for generating the corrected internal clock that coincides with the external clock based on a predetermined principle, since a circuit for accurately copying a predetermined delay amount can not be constructed, Lt; / RTI &gt; to an external clock.

An object of the present invention is to solve such a problem, and an object of the present invention is to provide a circuit for generating a corrected internal clock corresponding to an external clock based on a predetermined principle, And make the corrected internal clock completely match the external clock.

It is also an object of the present invention to provide a circuit for generating a corrected internal clock having a constant phase relationship with respect to an external clock, that is, a phase delayed by a predetermined amount with respect to an external clock, based on a predetermined principle.

In order to achieve the above object, the delay array of the present invention is constituted of a plurality of delay units connected in series, and each of the delay units includes a forward pulse delay for delaying the forward pulse by a predetermined delay amount, A backward pulse delay circuit for delaying the backward pulse by the predetermined delay amount and transmitting the delayed backward pulse to the delay unit of the previous stage; and, when the forward pulse is inputted when the pulse of the internal clock is not inputted to the plurality of delay units, And a state holding unit that is set to a reset state when the backward pulse is input when a pulse of the internal clock is input to the plurality of delay units, And the front edge of the backward pulse is input to the plurality of delay units when a pulse of the internal clock is input to the plurality of delay units Condition holding portion is formed in the near delay unit in the delay unit of the delay unit and the reset state of the initial stage of the reverse pulse is output from the delay units of the initial stage.

When the pulse of the internal clock is not input to the plurality of delay units, the edge other than the front edge of the backward pulse is delayed by a delay unit closest to the delay unit of the initial stage among the delay units of the reset state, .

The clock synchronous delay control circuit of the present invention includes the delay array, a buffer having a delay amount D1 and generating an internal clock based on an external clock, and a delay circuit for delaying the pulse of the internal clock by a delay amount A A second delay circuit for delaying a backward pulse outputted from the delay unit at the initial stage by a delay amount D2 and outputting the backward pulse as a correction internal clock, And the delay amount D1, the delay amount D2 and the delay amount A have a relationship of A = D1 + D2.

The clock synchronous delay control circuit of the present invention is characterized in that in a period from when the pulse of the internal clock is input to the plurality of delay units of the delay array to the time when the forward pulse is supplied to the delay unit of the initial stage, And a control pulse generating circuit for generating a control pulse for initializing the forward pulse delay circuit of the delay unit of the delay unit.

Further, the clock control circuit of the present invention is configured such that, when the forward pulse is output from the delay unit of the last stage of the delay array, the clock control circuit interrupts the backward pulse output from the delay unit of the initial stage, And means for controlling the pulse of the internal clock to be outputted from the second delay circuit.

The means initializes the second delay circuit based on a backward pulse output from the delay unit of the initial stage after a pulse of the internal clock is output from the second delay circuit.

The delay array is disposed between a position where the buffer is arranged and a position where the second delay circuit is arranged. Wherein the pattern of the first delay circuit is the same as the pattern of the wiring from the buffer and the buffer to the delay array and the same pattern as the pattern of the wiring from the second delay circuit and the delay array to the second delay circuit Pattern and the like.

The memory circuit of the present invention comprises a memory cell array, a write / read circuit for writing or reading data to / from the memory cell array, an input circuit for inputting the data from the bus, And the clock control circuit, wherein the operation of the write / read circuit is controlled by an internal clock outputted from the buffer of the clock control circuit, and the operation of the input circuit or the output circuit Is controlled by a corrected internal clock output from at least the second delay circuit of the clock control circuit.

A synchronous control system according to the present invention comprises a bus, a control block for transmitting data to the bus and generating an external clock, and the memory circuit, And a memory block for receiving a clock.

Further, the delay array of the present invention is constituted by a plurality of delay units connected in series, and each of the delay units includes a delay circuit for delaying the forward pulse and the backward pulse asynchronously by a predetermined delay amount, Wherein the forward pulse is input to a delay unit of an initial stage and a front edge of the backward pulse is a pulse of an internal clock which is set to a set state and is set to a reset state by the backward pulse, When the delay unit is input to the plurality of delay units, the state-holding unit is formed in a delay unit closest to the delay unit of the initial stage among the delay units of the reset state, and the backward pulse is generated in a direction opposite to the advancing direction of the forward pulse And output from the delay unit of the initial stage.

The delay array of the present invention is composed of a plurality of first and second delay units connected in series. Each of the first delay units includes a forward pulse delay circuit for delaying the pulses by a predetermined delay amount and transmitting the delayed pulses to a delay unit at a subsequent stage, a first delay unit for delaying the first advancing pulses by a predetermined delay amount, A reverse pulse delay circuit and a first state when the forward pulse is input when a pulse of an internal clock is not input to the plurality of first delay units, And when the first backward pulse is inputted, the second backward pulse is set to the second state. Each of the second delay units is constituted by a second backward pulse delay circuit for delaying the second backward pulse by the predetermined delay amount and transferring the delayed second backward pulse to the preceding delay unit. Wherein the forward pulse is input to a first delay unit of an initial stage and a front edge of the first reverse pulse is delayed when a pulse of the internal clock is input to the plurality of first delay units, A first delay unit closest to the first delay unit of the initial stage among the delay units, and the first reverse pulse is output from the first delay unit of the initial stage. The front edge of the second backward pulse is formed in a second delay unit corresponding to the first delay unit forming the front edge of the first backward pulse and the backward pulse is output from the second delay unit of the initial stage. The delay amount of the first backward pulse delay circuit is equal to the delay amount of the second backward pulse delay circuit.

Wherein the edges of the first backward pulse other than the front edge are selected such that when a pulse of the internal clock is not input to the plurality of first delay units, Is formed in the first unit closest to the unit.

The number of the first delay units and the number of the second delay units are different from each other. It is effective that the number of the second delay units is smaller than the number of the first delay units.

And a second delay unit that constitutes one first block by j successive delay units among the plurality of first delay units, and a second delay unit which is constituted by k successive second delay units among the plurality of second delay units, And controls the operations of k second delay units of the second block based on control pulses that control k operations of the j first delay units of the first block. However, j and k are natural numbers that are small, and j &gt; k.

Wherein the first delay unit constitutes r (r is a natural number) blocks, the total number of the first delay units is n (= rx j), the second delay unit also constitutes r blocks, And the delay amount of the second backward pulse is (m / n) 占 when the total number of the second units is m (= rxj), and the delay amount of the first backward pulse is?.

The clock control circuit of the present invention includes the above-described delay array, a buffer having the delay amount D1 and generating the internal clock based on an external clock, and a delay circuit for delaying the pulse of the internal clock by the delay amount (A) (J-1) x D1 + j x D2, which is the first delayed pulse outputted from the first delay unit at the initial stage, to the first delay unit of the initial stage as a pulse (K-1) x D1 + k x D2 to output the second backward pulse outputted from the second delay unit of the initial stage by delaying the delay amount And a second delay circuit for outputting a second correction internal clock. However, j and k are natural numbers that are small numbers, and j &gt; k.

The delay amount D1, the delay amount D2, and the delay amount A have a relationship of A = j 占 (D1 + D2).

The clock control circuit of the present invention comprises the delay array described above, a buffer having a delay amount k x D1 and generating the internal clock on the basis of an external clock, and a buffer for delaying the pulse of the internal clock by the delay amount A A second delay circuit for delaying the first backward pulse outputted from the first delay unit at the initial stage by a delay amount (jk) x D1 + j x D2 as a forward pulse to the first delay unit at the initial stage; A second delay circuit for delaying the second backward pulse outputted from the second delay unit at the initial stage by a delay amount k D2 and outputting the delayed second clock as a second corrected internal clock; 3 delay circuit. However, j and k are natural numbers that are small numbers, and j &gt; k.

The delay amount D1, the delay amount D2, and the delay amount A have a relationship of A = j 占 (D1 占 D2).

The clock control circuit of the present invention is characterized in that in a period from when the pulse of the internal clock is input to the plurality of first delay units to when the forward pulse is supplied to the first delay unit of the initial stage, And a control pulse generating circuit for generating a control pulse for initializing the forward pulse delay circuit of the first delay unit.

The number of the first delay units and the number of the second delay units are different from each other. It is effective that the number of the second delay units is smaller than the number of the first delay units.

The first delay unit constituting a first block by j consecutive first delay units among the plurality of first delay units and constituting a first block by k consecutive second delay units among the plurality of second delay units, And controls the operation of k second delay units of the second block based on control pulses that control k operations of the j first delay units of the first block .

Wherein the first delay unit constitutes r (r is a natural number) blocks, the total number of the first delay units is n (= r x j), the second delay unit also constitutes r blocks, The total number of the second units is m (= r x j).

The second backward pulse delay circuit generates a delay amount of m / n (= k / j) of the delay amount generated by the first backward pulse delay circuit.

J is 2, k is 1, and the second backward pulse delay circuit of the second delay unit generates a delay amount of half of the delay amount generated by the first backward pulse delay circuit of the first delay unit do.

K is 1 and the second backward pulse delay circuit of the second delay unit generates a delay amount of 1 / j of the delay amount generated by the first backward pulse delay circuit of the first delay unit.

The memory system of the present invention includes a plurality of memories, a controller for controlling the plurality of memories, a dummy memory having an input capacity equal to an input capacity of the plurality of memories, with respect to an external clock output from the controller, A first wiring arranged so that a delay time of the external clock from the controller to the plurality of memories is equal to a delay time of the external clock from the controller to the dummy memory, A data bus for introducing data from one of the plurality of memories to the controller based on a clock and a second wiring for returning the external clock to the dummy memory as a return clock to the controller.

Further, the delay time of the data from one of the plurality of memories to the controller is equal to the delay time of the return clock from the dummy memory to the controller, and the controller receives the data based on the return clock do.

A clock control circuit of the present invention includes a first delay circuit for receiving an internal clock delayed by D1 with respect to an external clock and outputting a backward pulse after the delay time A has elapsed after the internal clock is input; A second delay circuit for delaying a forward pulse by 2 占 and outputting a backward pulse; and a second delay circuit for receiving the backward pulse and for generating a delay time [(i-1) 占 D1 + j 占 D2 ), And outputs a corrected internal clock whose phase coincides with the external clock. J is a natural number, DELTA is a time from the generation of the forward pulse until the pulse of the internal clock is generated first, and A is j (D1 + D2)

A clock control circuit of the present invention includes a first delay circuit for inputting an internal clock delayed by m x D1 with respect to an external clock and outputting an advancing pulse after the delay time A has elapsed after the internal clock is input A second delay circuit for delaying the forward pulse by 2 x? And outputting a backward pulse; and a second delay circuit for receiving the backward pulse and delay time jk D1 + j D2 after inputting the backward pulse And a third delay circuit for outputting a corrected internal clock whose phase coincides with the external clock after elapsing. J and k are natural numbers that are prime to each other, j? K, and? Is the time from the generation of the forward pulse to the generation of the pulse of the internal clock first, and A is jx (D1 + D2).

The clock control circuit of the present invention includes a first delay circuit for receiving an internal clock delayed by D1 with respect to an external clock and outputting a forward pulse after the delay time A has elapsed after the internal clock is input; A second delay circuit for delaying the forward pulse by? + (K / j) 占 and outputting a backward pulse; and a second delay circuit for delaying the delay time (k-1) And a third delay circuit for outputting a corrected internal clock whose phase is delayed by (k / j) x T with respect to the external clock after D1 + k x D2 has elapsed. J is a natural number with a small number of j, k is k, k is a time from when the forward pulse is generated until the pulse of the internal clock is generated first, A is j x (D1 + D2) It is the cycle of the clock.

A clock control circuit of the present invention includes a first delay circuit for inputting an internal clock delayed by k x D1 with respect to an external clock and outputting a forward pulse after the delay time A has elapsed after the internal clock is input A second delay circuit for delaying the forward pulse by Δ + (k / j) × Δ and then outputting a backward pulse; and a second delay circuit for receiving the backward pulse, And outputs a corrected internal clock whose phase is delayed by (k / j) *? With respect to the external clock, wherein j and k are constants of j, DELTA is the time from the generation of the forward pulse until the pulse of the internal clock is generated first, A is j (D1 + D2), and T is the period of the external clock.

FIG. 1 shows the main part of a system with a memory having a circuit of the invention; FIG.

FIG. 2 shows the configuration of a clock control circuit in the memory of FIG. 1;

3 is a circuit diagram showing in detail the delay unit in the circuit of Fig. 2; Fig.

FIG. 4 is a circuit diagram showing in detail the state maintaining unit in the delay unit of FIG. 3;

FIG. 5 shows in detail the control pulse generating circuit in the circuit of FIG. 2; FIG.

FIG. 6 is a view showing the principle of the present invention. FIG.

FIG. 7 is a timing diagram showing the operation of the circuits of FIGS. 2 to 5; FIG.

FIG. 8 shows the state of a in the timing chart of FIG. 7; FIG.

FIG. 9 shows the state of FIG. 7 b; FIG.

Figure 10 shows the state of c in the timing diagram of Figure 7;

Fig. 11 shows the state of d in the timing chart of Fig. 7; Fig.

FIG. 12 shows the state of e in the timing chart of FIG. 7;

FIG. 13 shows the state of f in the timing chart of FIG. 7; FIG.

FIG. 14 shows the state of g in the timing chart of FIG. 7; FIG.

Fig. 15 shows the state of h in the timing chart of Fig. 7; Fig.

Fig. 16 shows the state of i in the timing chart of Fig. 7; Fig.

Figure 17 shows a modification of the circuit of Figure 2 of Figure 17;

FIG. 18 shows a modification of the circuit of FIG. 2; FIG.

19 shows in detail the delay circuit 34 in the circuit of FIG. 18; FIG.

20 shows in detail the control pulse generation delay circuit 61 in the circuit of FIG. 18;

21 shows the problem of the operation of the circuit of FIG. 2; FIG.

FIG. 22 is a timing diagram showing the operation of the circuits of FIG. 18 to FIG. 20; FIG.

Figure 23 shows a layout when the circuit of the invention is incorporated into a chip.

24 shows the operation of the circuits of FIGS. 2 and 18; FIG.

FIG. 25 shows the operation of the circuits of FIGS. 2 and 18; FIG.

Figure 26 shows the operation of the circuits of Figures 2 and 18;

FIG. 27 shows the operation of the circuits of FIGS. 2 and 18; FIG.

Figure 28 shows a schematic configuration of a clock control circuit of Figure 2;

29 is a diagram showing a first example of a clock control circuit of the present invention;

FIG. 30 shows a second example of the clock control circuit of the present invention; FIG.

FIG. 31 shows a third example of the clock control circuit of the present invention; FIG.

Figure 32 shows a fourth example of the clock control circuit of the present invention.

FIG. 33 shows a fifth example of the clock control circuit of the present invention; FIG.

34 is a detailed circuit diagram of the configuration of the clock control circuit of FIG. 1;

FIG. 35 shows in detail the configuration of a delay unit Ui in the circuit of FIG. 34; FIG.

FIG. 36 shows in detail the configuration of a delay unit Ui in the circuit of FIG. 34; FIG.

FIG. 37 is a view showing a first example of the configuration of the HBD; FIG.

Figure 38 shows a second example of the configuration of an HBD;

FIG. 39 shows the configuration of the delay unit bdi of FIG. 37 or 38; FIG.

FIG. 40 is a diagrammatic representation of the circuit of FIG. 39; FIG.

FIG. 41 is a view showing a first example of the configuration of 1/3 BD; FIG.

Figure 42 shows a second example of the configuration of a 1 / 3BD;

Figure 43 shows the configuration of m / nBD;

FIG. 44 shows a block B (i) of FIG. 43; FIG.

Figure 45 is a diagram illustrating the principles of the present invention.

Figure 46 illustrates the principles of the present invention.

Figure 47 is a diagram showing the configuration of a memory system of the present invention;

Figure 48 shows the main part of a conventional system.

49 is a circuit diagram showing the external clock of the system of FIG. 48 and the skew of the internal clock; FIG.

Figure 50 shows the principle of a synchronization system on which the present invention is based;

51 shows an example of a circuit for achieving the principle of FIG. 50; FIG.

FIG. 52 is a view showing a determination of the delay amounts? F and? B in the circuit of FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

11: memory 12: CPU

13: buffer 14: input circuit

15: output circuit 16: write / read circuit

17: memory cell array 18: data bus

21: input terminal 22: input buffer

23, 25-1 to 25-n, 29-1 to 29-n, 30:

24: forward delay array 26: mirror control circuit

27-1 to 27-n: control element 28: reverse delayed array

31: Clock synchronous delay control circuit

32, 33-1 to 33-n, 34, 57, 62: delay circuit

41 to 46, 59, 63, 66 to 68, 70: Inverter

47: state maintaining section 48, 49, 64: NAND circuit

51, 52: P-channel type MOS transistor

53 to 56: N-channel type MOS transistor

58, 69, 71, 72: NOR circuit

60, 61: control pulse generating circuit

73: NAND circuit 74: delay circuit

75: Inverters 81 to 84: Circuit pattern

Hereinafter, the clock synchronization delay control circuit of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of a synchronous control system having a memory block having a clock synchronous delay control circuit of the present invention.

An external clock CK generated by, for example, the CPU 12 is input to a memory (a clock synchronous type DRAM such as a synchronous DRAM). The external clock (CK) is converted into an internal clock (CLK) by the buffer (13). The internal clock CLK is supplied to the write / read circuit 16 and controls write / read operations of data.

Since the internal clock CLK is generated by the buffer 13 as the trigger of the external clock CK, there is inevitably skew between the external clock CK and the internal clock CLK.

The clock synchronization delay control circuit 31 generates a corrected internal clock CK 'that coincides with the timing of the external clock CK based on the internal clock CLK. The corrected internal clock CK 'is supplied to the input circuit 14 and the output circuit 15, and controls the input / output operation of data.

FIG. 2 shows the configuration of the clock synchronization delay control circuit 31 in the memory 11 of FIG.

The external clock CK is applied to the memory input terminal 30. The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CLK having a skew of D1 with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A and the delay circuit 32 outputs the forward pulse FCLi (delayed imitation pulse CL).

The internal clock CLK and the inverted internal clock CLK inverted by the inverter 35 by the internal clock CLK are supplied to n delay units 33-1, 33-2, ..., 33- .

The n delay units 33-1, 33-2, ..., 33-n are connected in series with each other. The forward pulse FCLi is input to the initial stage delay unit 33-1 and the backward pulse RCL1 is output from the initial stage delay unit 33-1.

The backward pulse RCL1 passes through the delay circuit 34 having the delay amount D2 to become the corrected internal clock CK '.

FIG. 3 shows the arrangement of the delay unit of FIG. 2 in detail.

The delay unit 33-i is composed of three parts: a forward pulse delay circuit, a state maintaining circuit, and a backward pulse delay circuit.

The forward pulse delay circuit is composed of three inverters 41 to 43. The inverter 41 and 42 are connected in series and the output signal FCLi of the preceding stage delay unit is input to the inverter 41. The inverter 42 outputs the output signal FCLi + . The operation of the inverter (clocked inverter) 41 is controlled by the control pulse / P. For example, when the control pulse / P is &quot; 1 &quot;, the inverter 41 becomes active.

The output terminal of the inverter 43 is connected to the input terminal of the inverter 42 and the input terminal of the inverter 43 is always supplied with a potential of "0" (for example, ground potential). The operation of the inverter (clocked inverter) 43 is controlled by the control pulse P, for example, when the control pulse P is &quot; 1 &quot;, the inverter 43 becomes active.

The backward pulse delay circuit is composed of three inverters 44 to 46. The inverters 44 and 45 are connected in series and the output signal RCLi + 1 or the internal clock CLK of the delay unit at the subsequent stage is input to the inverter 44. The inverter 45 is connected to the delay unit at the previous stage And outputs the output signal RCLi. The operation of the inverter (clocked inverter) 44 is controlled by the control pulse Q, and the inverter 44 is activated only when, for example, the control pulse Q is &quot; 1 &quot;.

The output terminal of the inverter 46 is connected to the input terminal of the inverter 45 and the input terminal of the inverter 46 is always supplied with the internal clock CLK. The operation of the inverter (clocked inverter) 46 is controlled by the control pulse / Q, for example, when the control pulse / Q is &quot; 1 &quot;, the inverter 46 becomes active .

The state retaining circuit is composed of a state retaining unit 47 and NAND circuits 48 and 49. [ The output signal FCLi and the inverted internal clock signal / CLK of the preceding stage delay unit are input to the NAND circuit 48. The output signal of the inverter 45 and the internal clock signal CLK are input to the NAND circuit 49 .

The output signal of the NAND circuit 48 becomes the set input / S of the state holding unit 47 and the output signal of the NAND circuit 49 becomes the reset input / R of the state holding unit 47 have. Therefore, when the output signal (set input) / S of the NAND circuit 48 becomes &quot; 0 &quot;, the state holding unit 47 becomes the set state and the output signal of the NAND circuit 49 ) / R becomes &quot; 0 &quot;, the state holding unit 47 is in the reset state.

The state maintaining unit 47 is configured to output control pulses Q and / Q. The control pulse Q becomes "1" when the state maintaining unit 47 is in the set state and the control pulse / Q becomes "1" when the state maintaining unit 47 is in the reset state.

FIG. 4 shows an example of the configuration of the state maintaining unit in FIG.

The P-channel type MOS transistor 51 and the N-channel type MOS transistors 53 and 54 are connected in series to each other, and high-potential VDD and low-potential VSS are applied to both ends thereof.

Likewise, the P-channel type MOS transistor 52 and the N-channel type MOS transistors 55, 56 are connected in series to each other, and high-potential VDD and low-potential VSS are applied to both ends thereof.

The set input / S is input to the gates of the MOS transistors 51 and 54 and the reset input / R is input to the gates of the MOS transistors 52 and 56.

The gate of the MOS transistor 53 is connected to the drain of the MOS transistor 52 and the gate of the MOS transistor 55 is connected to the drain of the MOS transistor 51. [

The control pulse Q is output from the drain of the MOS tran- sistor 51 and the control pulse / Q is output from the drain of the MOS transistor 52. [

FIG. 5 shows an example of the configuration of the control pulse generating circuit P / / P.

The internal clock CLK is input to one input of the NOR circuit 58 via the delay circuit 57 having the delay amount A 'and the inverted internal clock / CLK is input to the other input of the NOR circuit 58 Side input terminal. The NOR circuit 58 outputs the control pulse P. The control pulse P becomes the control pulse / P by way of the inverter 59. [

The pulse width of the control pulses P, / P is determined by the delay amount A 'of the delay circuit 57. However, this delay amount A 'is set to be smaller than the delay amount A of the delay circuit 32 for outputting the delay-mimetic pulse. This is because it is necessary to initialize the forward delay circuits of all the delay units before the forward pulse is inputted to the delay unit of the initial stage.

Next, the principle of the present invention will be confirmed with reference to FIG. 6.

The skew width (delay amount) of the external clock CK and the internal clock CLK is D1 and the cycle of the external clock CK and the internal clock CLK is T. [

The delayed mimic pulse FCL1 is generated at a point in time when the first pulse of the internal clock CLK has passed since the time point when the first pulse of the internal clock CLK is generated. In this case, the time from the generation of the delay imitation pulse FCL1 to the generation of the second pulse of the internal clock CLK is? F.

The time Δf is copied to make Δb and the delay imitation pulse RCL1 (2) is generated at the time point when the time (2 × Δ) (Δf = Δb = Δ) ). Then, the time point at which the time (A) elapses from the point in time at which the delay mimic pulse RCL1 is generated coincides with the time point at which the third pulse of the internal clock CLK is generated. (A + W) < T. And W is the width of delay imitation pulses FCL and RCL.

Assuming that the time from the generation of the delay mimic pulse RCL1 to the generation of the third pulse of the external clock CK is D2, if the delay mimic pulse RCL1 is delayed by the time D2, the external clock CK (CK ') corresponding to the timing of the internal clock CK'.

That is, by forming a delay circuit for generating the delay amounts A, (2 占 and D2) and delaying the internal clock CLK by the time A + (2 占?) + D2, It is possible to obtain the corrected internal clock CK 'that coincides with the timing of the internal clock CK.

Further, since there is a relationship of A = D1 + D2, the delay amount D2 can be obtained from A and D1. The control pulse P is for initializing the forward delay circuits of all the delay units before the forward pulse is inputted to the delay unit at the initial stage.

Next, the operation of the clock synchronization delay control circuit of FIG. 2 to FIG. 5 will be described.

1. State at a point of time in the timing chart of FIG. 7

As shown in Fig. 8, the internal clock CLK becomes &quot; 1 &quot; (rises). Therefore, the output signal of the control pulse generating circuit 60 becomes P = &quot; 1 &quot;, / P = &quot; 0 &quot;, and the control pulses P, / P having a pulse width determined by the delay amount A ' Are generated and input to the respective delay units 33-1, 33-2, ..., 33-n.

P = "1" and / P = "0" in each of the delay units 33-1 to 33-n so that the inverter 43 becomes active and the inverter 41 It becomes inactive. Therefore, the input / output signals FCL1 to FCLn of the forward pulse delay circuits of all the delay units 33-1, 33-2, ..., 33-n are all "0", and the line to which the forward pulse is transmitted is initialized do.

Thereafter, in the delay units 33-1, 33-2, ..., 33-n, when P = "1" and / P = "0", the inverter 41 becomes active, 43 are in an inactive state. That is, the forward pulse delay circuits of the delay units 33-1, 33-2, ..., 33-n are electrically connected to each other, and the input terminal of the forward pulse delay circuit of the delay unit 33-1 is connected to the delay circuit (32), and preparation for transfer of the forward pulse is completed.

The period of the control pulses P and / P (P is "1" and / P = "0") is shorter than the period determined by the delay amount A of the delay circuit 32 It is a prerequisite. The transmission line of the forward pulse of all the delay units 33-1, 33-2, ..., 33-n is initialized before the advance pulse (delay imitation pulse) FCL1 is input to the delay unit 33-1 It is necessary to put it.

2. State of the timing point b in the timing chart of Fig. 7

As shown in Fig. 9, the internal clock CLK becomes "0" and the inversion internal clock / CLK becomes "1". Since the internal clock CLK and the inverted internal clock / CLK are common to all the delay units 33-1, 33-2, ..., 33-n, all the delay units 33-1, 33-2, ..., 33-n becomes &quot; 1 &quot;.

On the other hand, the state holding unit 47 of each of the delay units 33-1, 33-2, ..., 33-n is in the reset state R, Q = &quot; 0 &quot; and / Q = &quot; 1 &quot;.

Therefore, the inverter 46 of each of the delay units 33-1, 33-2, ..., 33-n becomes active, the inverter 44 becomes inactive, all the delay units 33-1, 33 The input / output signals RCL1 to RCLn of the backward pulse delay circuits of the first, second, ..., and 33-n are all "0".

3. The state at point c in the timing chart of Figure 7

As shown in Fig. 10, a forward pulse (delay imitation pulse) FCL1 is outputted from the delay circuit (delay amount A) 32 and inputted to the delay unit 33-1. It is also necessary to set the period of time that is determined by the pulse width of the forward pulse (the period of &quot; 1 &quot;) and the delay amount A to be shorter than the period T of the internal clock CLK.

When the forward pulse FCL1 (= "1") is input to the delay unit 33-1, the other input of the NAND circuit 48 of the delay unit 33-1 becomes "1" The output [set input (/ S)] of the input terminal 48 becomes "0". Therefore, the state of the state holding section 47 changes to the set state S.

In the delay unit 33-1 in which the state maintaining unit 47 is set to the set state S, the control pulses outputted from the state holding unit 47 are Q = "1" and / Q = "0" The inverter 44 becomes active, and the inverter 46 becomes inactive.

4. The state at the point d and e in the timing chart of Fig. 7

As shown in Fig. 11, the forward pulse advances through the delay units 33-1, 33-2, ..., 33-n sequentially.

In the delay unit 33-1 in which the forward pulse has passed excessively, the other input of the NAND circuit 48 becomes "0" and the output (set input / S) of the NAND circuit 48 becomes " 1 &quot;, but the state of the state holding unit 47 is maintained in the set state S.

Similarly, when the forward pulse is inputted to the delay unit 33-2, the state holding unit 47 of the delay unit 33-2 changes to the set state S. Even if the forward pulse excessively passes through the delay unit 33-2, the state dependent unit 47 of the delay unit 33-2 maintains the set state S.

When the internal clock CLK becomes "1" and the inverted internal clock / CLK becomes "0", the delay units 33-1, 33-2, ..., 33- (CLK) and an inverted internal clock (/ CLK) are input.

Therefore, one input of the NAND circuit 48 of all the delay units 33-1, 33-2, ..., 33-n becomes "0", and one input of the NAND circuit 49 Quot; 1 &quot;.

Since Q = &quot; 1 &quot; in the delay units 33-1 and 33-2 in which the state maintaining unit 47 is in the set state S and the inverter 44 is active, the output signal of the backward pulse delay circuit Quot; 1 &quot; in the delay units 33-3 to 33-n in which the state maintaining unit 47 is in the reset state R, while the delay units RCL1 and RCL2 maintain the state &quot; 0 & Since the inverter 46 is active, the output signals RCL3 to RCLn of the backward pulse delay circuit become &quot; 1 &quot;.

Thereby, the front edge F2 of the backward pulse is formed.

Here, the front edge F2 of the backward pulse is the state in which the state holding unit is the earliest stage among the delay units 33-3 to 33-n in the reset state R when the internal clock CLK becomes &quot; 1 & Is formed in the delay unit 33-3 located on the side of the delay unit 33-1.

At this time, since the front edge F1 of the forward pulse can be considered to be positioned immediately before the delay unit 33-3, the front edge F1 of the forward pulse and the front edge F2 of the backward pulse coincide with each other.

Therefore, after the time Δf from when the forward pulse (delay imitation pulse) FCL1 is generated to when the internal clock CLK is generated and when the pulse of the internal clock CLK is generated The backward pulse RCL1 is output and the time? B until the delay circuit 34 is input becomes equal.

Thereafter, as shown in Fig. 12, the output signal of the control pulse generating circuit 60 becomes P = "1" and / P = "0", and a pulse determined by the delay amount A ' Control pulses P and / P having a width are generated and input to the respective delay units 33-1, 33-2, ..., 33-n.

P = "1" and / P = "0" in each of the delay units 33-1 to 33-n so that the inverter 43 becomes active and the inverter 41 It becomes inactive. Therefore, the input / output signals FCL1 to FCLn of the forward pulse delay circuits of all the delay units 33-1, 33-2, ..., 33-n are all "0", the forward pulse is eliminated, Is initialized.

On the other hand, when the front of the backward pulse (= &quot; 1 &quot;) is input to the delay unit 33-1, both of the two inputs of the NAND circuit 49 in the delay unit 33-2 become &quot; The output [reset input (/ R)] d1 of the NAND circuit 49 becomes "0" and the state maintaining unit 47 changes to the reset state R (initialized).

The initialization (reset state R) of the state maintaining unit 47 of each delay unit is performed only during the period in which the internal clock CLK is &quot; 1 &quot;. That is, when a backward pulse (= "1") is input when the internal clock CLK is "1", both inputs of the NAND circuit 49 become "1".

Since the state holding unit 47 of each delay unit is initialized only during the period in which the internal clock CLK is &quot; 1 &quot;, the state holding unit 47 of all the delay units is initialized, However, there is no particular problem. This is because it is clear that the next advance pulse is excessively passed through to the uninitialized delay unit 33-1.

5. State of f at the timing chart of Fig. 7

As shown in Fig. 13, the internal clock CLK becomes "0" and the inversion internal clock / CLK becomes "1". The internal clock CLK and the inverted internal clock / CLK are input to all the delay units 33-1, 33-2, ..., 33-n.

P = &quot; 0 &quot; and / P = &quot; 1 &quot; in each of the delay units 33-1, 33-2, ..., 33-n. Thus, the inverter 41 becomes active, Is in an inactive state. That is, the forward pulse delay circuits of the delay units 33-1, 33-2, ..., 33-n are electrically connected to each other, and the input terminal of the forward pulse delay circuit of the delay unit 33-1 is connected to the delay circuit (32), and preparation for transfer of the forward pulse is completed.

On the other hand, in the delay units 33-2 to 33-n in which the state maintaining unit 47 is in the reset state R, / Q = "1" and the inverter 46 is in an active state. Therefore, when the internal clock CLK becomes &quot; 0 &quot;, the output signals RCL2 to RCLn of the delay units 33-2 to 33-n whose state holding unit 47 is in the reset state R are &quot; 0 &quot;, and the back edge of the backward pulse is formed.

Therefore, the pulse width of the backward pulse is equal to or shorter than the period corresponding to the delay amount of one delay unit (the delay amount of two inverters).

If it is desired to make the pulse width of the backward pulse longer than the delay amount of one delay unit, the other input of the NAND circuit 49 of the delay circuit 33- (RCLn-1) of the delay circuit 33- (n-1) of Fig. In this case, the maximum pulse width of the backward pulse is a period corresponding to the delay amount of two delay units (the delay amount of four inverters).

In the delay unit 33-1 in which the state maintaining unit 47 is in the set state S, Q = &quot; 1 &quot;, and the inverter 44 is in the active state. Thus, preparation for introducing the backward pulse to the delay circuit 34 via the delay unit 33-1 is completed.

6. State of g point in the timing chart of Figure 7

As shown in Fig. 14, a forward pulse (delay imitation pulse) FCL1 is outputted from the delay circuit (delay amount A) 32 and inputted to the delay unit 33-1. When the forward pulse FCL1 (= "1") is input to the delay unit 33-1, the other input of the NAND circuit 48 of the delay unit 33-1 becomes "1" The output [set input (/ S)] of the input / output terminal 48 becomes &quot; 0 &quot;.

Therefore, when the state holding unit 47 of the delay unit 33-1 is in the set state, the state holding unit 47 holds the set state S and the state holding unit 47 is in the reset state R), the state holding portion 47 is changed to the set state S.

In the delay unit 33-1 in which the state maintaining unit 47 is set to the set state 5, the delay pulses outputted from the state holding unit 47 are Q = "1" and / Q = "0" The inverter 44 becomes active, and the inverter 46 becomes inactive.

On the other hand, the backward pulse is input to the delay unit 33-1 at the initial stage, is delayed by two stages of the inverter, and is output from the delay unit 33-1 at the initial stage.

7 State of h at the timing chart of Figure 7

As shown in FIG. 15, the forward pulse advances through the delay units 33-1, 33-2, ..., 33-n sequentially.

In the delay unit 33-1 in which the forward pulse has passed excessively, the other input of the NAND circuit 48 becomes "0" and the output (set input / S) of the NAND circuit 48 becomes " 1 &quot;, but the state of the state holding unit 47 is maintained in the set state S.

Similarly, when the forward pulse is inputted to the delay unit 33-2, the state holding unit 47 of the delay unit 33-2 changes to the set state S. Even if the forward pulse excessively passes through the delay unit 33-2, the state holding unit 47 of the delay unit 33-2 maintains the set state S.

On the other hand, the backward pulse is inputted to the delay circuit 34. The delay circuit 34 delays the backward pulse by the delay amount D2 to generate a pulse of the corrected internal clock CK '. The timing of the pulse of the corrected internal clock CK 'coincides with the timing of the pulse of the external clock CK.

8. State at i-point of the timing chart of Fig. 7

As shown in FIG. 16, when the internal clock CLK becomes "1" and the inverted internal clock / CLK becomes "0", the delay units 33-1, 33-2, 33-n, the internal clock CLK and the inverted internal clock / CLK are input.

Therefore, one input of the NAND circuit 48 of all the delay units 33-1, 33-2, ..., 33-n becomes "0", and one input of the NAND circuit 49 Quot; 1 &quot;.

In the delay units 33-1 and 33-2 in which the state maintaining unit 47 is in the set state 5, Q = &quot; 1 &quot;, and the inverter 44 is in the active state, Quot; 1 &quot; in the delay units 33-3 to 33-n in which the state retaining unit 47 is in the reset state R, while the delay units RCL1 and RCL2 maintain the state &quot; 0 & Since the inverter 46 is in an active state, the output signals RCL3 to RCLn of the backward pulse delay circuit become &quot; 1 &quot;.

Thereby, the front F1 of the backward pulse is formed.

Thereafter, the operations of FIG. 12 through FIG. 16 are repeatedly performed.

According to the clock synchronous delay control circuit having the above configuration, each delay unit has a state maintaining unit, whereby the time Δf (f) from the generation of the delayed imitation pulse (reverse pulse) FCL1 to the generation of the pulse of the internal clock And the delay circuit 34 having the delay amount D2 after the time Δb (= Δf) after the generation of the pulse of the internal clock CLK Can be input.

Therefore, it is possible to generate the corrected internal clock CK 'exactly synchronized with the external clock CK, and data transfer using the high-speed clock can be achieved. Further, like the synchronous DRAM, the present invention is effective for a memory in which an internal clock is temporarily suspended and data is transferred in synchronization with a high-speed clock whose frequency is changed.

FIG. 18 shows a modification of the clock synchronization delay control circuit of FIG. 2;

This clock synchronous delay control circuit differs from the circuit of FIG. 2 in that a delay circuit 34 is provided with a predetermined function, and the other configuration is the same as that of the circuit of FIG.

That is, in the present embodiment, when the period T of the external clock CK or the internal clock CLK is longer than a predetermined value, the timing of the internal clock CLK is added to the timing of the external clock CK The control of the input / output circuit of the memory is performed by the internal clock CLK having a constant skew.

This is because, when the frequency of the external clock CK is relatively low (the cycle is long), the skew itself is not so much a problem. This is because the number of delay units constituting the clock synchronous delay control circuit is not so large as compared with the occupied area on the memory chip.

Hereinafter, the circuit configuration of the present embodiment will be briefly described.

The external clock CK is applied to the input terminal 30 of the memory. The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CLK having a skew of D1 with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A and the delay circuit 32 outputs the forward pulse FCL1 (delayed oscillation pulse DL).

The internal clock CLK and the inverted internal clock CLK inverted by the inverter 35 by the internal clock CLK are supplied to n delay units 33-1, 33-2, ..., 33-n, .

The n delay units 33-1, 33-2, ..., 33-n are connected in series with each other. The forward pulse FCL1 is input to the delay unit 33-1 at the initial stage and the backward pulse RCL1 is output from the delay unit 33-1 at the initial stage.

When the period T of the external clock CK is less than a predetermined value (high-speed clock), the backward pulse RCL1 passes through the delay circuit 34 having the delay amount D2 so that the corrected internal clock CK ' ). The timing of the corrected internal clock CK 'coincides with the timing of the external clock CK.

The backward pulse RCL1 is input to the delay circuit 34 having the delay amount D2 but not outputted from the delay circuit 34 when the period T of the external clock CK is equal to or greater than a predetermined value. The internal clock CLK is output from the delay circuit 34. Naturally, the internal clock CLK has a certain skew with respect to the external clock CK, but this skew corresponds to the phase of the external clock CK So that the amount of time is not so much problematic for the cycle.

The control pulse generating circuit 61 outputs the output LST of the forward pulse delay circuit of the final stage delay unit 33-n and the output LCL of the backward pulse delay circuit of the initial stage delay unit 33-1 (L, / L) based on the control pulses L and / L. The control pulses L and / L determine whether to output the corrected internal clock CK 'or the internal clock CLK.

19 shows the configuration of the delay circuit 34 of FIG. 18 in detail.

The output RCL1 of the delay unit 33-1 is input to one input terminal of the NAND circuit 64 via the delay circuit 62 and the inverter 63 and is directly supplied to the other input terminal of the NAND circuit 64 Is input to the input terminal of the side. The output signal of the NAND circuit 64 passes through the three inverters 65 to 67, thereby becoming the corrected internal clock CK '.

The inverter 66 is a clock inverter that becomes active when the control clock (/ L) is &quot; 1 &quot;. That is, when the control clock / L is &quot; 1 &quot;, the backward pulse is delayed by a predetermined time to generate the corrected internal clock CK ' do.

The internal clock CLK is input to the inverter 67 of the delay circuit 34 via the inverter 68. The inverter 68 is a clocked inverter that becomes active when the control clock L is &quot; 1 &quot;. That is, when the control clock L is "1", the internal clock CLK is introduced to the inverter 6 ', and when the control clock L is "0", the internal clock CLK is cut off.

FIG. 20 shows the configuration of the control pulse generating circuit 61 of FIG. 18.

The output (LST) of the forward pulse delay circuit of the last-stage delay unit 33-n is input to one input terminal of the NOR circuit 69 and the output of the NOR circuit 72 is input to the other input terminal have. The output of the NOR circuit 69 is input to one input terminal of the NOR circuit 72 and the output of the NOR circuit 71 is input to the other input terminal thereof.

The NOR circuit 71 receives the output LST of the forward pulse delay circuit of the last stage delay unit 33-n and the output RCL1 of the backward pulse delay circuit of the first stage delay unit 33-1 And inverted by the inverter 70 are inputted.

The NAND circuit 73 receives the output of the NOR circuit 69 and the delayed output of the delay circuit 74 by the delay amount D3. The output of the NAND circuit 73 becomes the control clock L and the control clock L inverted by the inverter 75 becomes the control clock L.

The NAND circuit 73 and the delay circuit 74 delay the rise of the control clock L with respect to the output of the NOR circuit 69 and the delay of the control clock L by the delay amount D3, To reliably extinguish and initialize the backward pulse in the pulse generator 34.

Next, with reference to FIG. 21, the principle of the clock synchronization delay control circuit of FIG. 18 to FIG. 20 will be briefly described.

21 shows a state in which one cycle (cycle time) of the external clock CK becomes comparatively long and a maximum delay amount max DELTA by the total delay unit is equal to a time point when a pulse of the internal clock CLK is generated Is shorter than the time? F up to the time? F.

The skew width (delay amount) of the external clock CK and the internal clock CLK is D1 and the cycle of the external clock CK is T. [

The delayed mimic pulse FCL1 is generated at a point of time A elapsed from the time when the first pulse of the internal clock CLK is generated (time of rising). In this case, the time from the generation of the delayed imitation pulse FCL1 to the generation of the second pulse of the internal clock CLK is? F.

However, the maximum delay amount that can be formed in the total delay unit is max? (? F). That is, since the maximum value of the delay amount that can be copied by the clock synchronization delay control circuit of the present invention is maxΔ, at the time point when the time point maxΔ has elapsed from the time point when the second pulse of the internal clock CLK is generated, RCL1) is generated, it is possible to accurately copy the delay amount [Delta] f.

Therefore, even if the corrected internal clock CK 'is generated at the time point when the time D2 elapses from when the delayed mimic pulse RCL1 is generated, the timing of the corrected internal clock CK' is equal to the timing of the external clock CK It is out of order. In addition, this shift may be larger than the original skew, which deteriorates the memory performance.

The present embodiment is designed to avoid such a phenomenon. In the embodiment shown in FIG. 2, when the time from the generation of the pulse of the internal clock CLK to the generation of the delayed impulse pulse is A and the maximum delay by the previous delay unit is maxΔ, it is necessary to satisfy max DELTA T, but this condition is not required in the present embodiment.

Next, the operation of the clock synchronization delay control circuit of FIG. 18 to FIG. 20 will be described with reference to the timing chart of FIG.

The operation when A + max DELTA T is satisfied is the same as the timing chart shown in Fig. 7, and therefore only the operation in the case of A + max DELTA T will be described below.

When the internal clock CLK becomes "1", P = "1" and / P = "0", and the forward pulse delay circuit of all the delay units 33-1, 33-2, Output signals FCL1 to FCLn are all &quot; 0 &quot;, and the line through which the forward pulse is transmitted is initialized.

Then, when P = "0" and / P = "1", the forward pulse delay circuits of the delay units 33-1, 33-2, ..., and 33-n are electrically connected to each other, The input terminal of the forward pulse delay circuit of the unit 33-1 is electrically connected to the delay circuit 32, and preparation for transfer of the forward pulse is completed.

(Delay imposed pulse) FCL1 from the delay circuit (delay amount A) 32 after the internal clock CLK becomes "0" and the inverted internal clock / CLK becomes "1" And is input to the delay unit 33-1.

When the forward pulse FCL1 (= &quot; 1 &quot;) is input to the delay unit 33-1, the state of the state holding unit 47 of the delay unit 33-1 becomes the set state S. Further, the forward pulse advances through the delay units 33-1, 33-2, ..., 33-n sequentially. In the delay unit in which the forward pulse is excessively passed, the state of the state holding unit 47 is maintained in the set state (S).

Thereafter, the forward pulse is output as the output pulse LST (= &quot; 1 &quot;) from the delay unit 33-n via all the delay units 33-1, 33-2, ..., .

The output pulse (LST) is input to the control pulse generating circuit (61). As a result, the control pulse generating circuit 61 generates a path switching signal with L = "1" and / L = "0". That is, L = &quot; 1 &quot;, / L = &quot; 0 &quot;, the delay circuit 34 is inactivated and the timing of the internal clock CLK The corrected internal clock CK 'is output.

Further, when the time max DELTA lapses after the internal clock CLK becomes "1", the delay unit 33-1 outputs the backward pulse RCL1. When the backward pulse RCL1 is input to the control pulse generating circuit 61, the control pulse generating circuit 61 generates the backward pulse RCL1 after the timing at which the backward pulse RCL1 is output from the control circuit 34, After the disappearance, a path switching signal of L = "0" and / L = "1" is generated.

That is, the delay circuit 34 is initialized (activated), and the delay circuit 34 is changed to a state capable of outputting the output signal RCL1 of the delay unit 33-1.

The delay circuit 62, the inverter 63 and the NAND circuit 64 determine the pulse width of the backward pulse outputted from the delay unit 33-1. That is, when the internal clock CLK is used for input / output control of the memory, L = 0 and L = 1 after the backward pulse disappears in the delay circuit 34, ) Is initialized (activated).

However, the delay amounts of the delay circuits 34, 62, and 74 are set so as to have the relationship of D3> D2 + D2 '.

According to the clock synchronization delay control circuit having the above-described configuration, it is possible to generate the corrected internal clock CK 'that is exactly synchronized with the external clock CK, and data transfer using the high-speed clock can be achieved.

In this embodiment, it is possible to decide whether to use the internal clock CLK as it is or to use the corrected internal clock CK 'synchronized with the external clock CK, depending on the frequency of the external clock CK.

That is, when data is transmitted in synchronization with a high-speed clock in which skew of the external clock CK and the internal clock CLK is a problem, a corrected internal clock CK 'synchronized with the external clock CK is used , And the internal clock (CLK) is used as usual when data is received in synchronization with a clock whose skew is not a problem.

In addition, whether to use the internal clock or the corrected internal clock is determined by the number of delay units.

Therefore, when the cycle (cycle time) of the external clock CK is long, there is no possibility that the deviation between the external clock CK and the corrected internal clock CK 'becomes large.

FIG. 23 shows a layout when the clock synchronous delay control circuit of the present invention is placed on a chip. FIG.

In the case where the clock synchronous delay control circuit of the present invention is actually incorporated in a system as an IC, it is necessary to consider the delay (wiring delay) caused by the wiring capacitance.

First, an array of delay units (hereinafter referred to as STBD) 80 is connected to the input buffer 13 (or wiring delay amount) and the output buffer (delay circuit) 34 (Or the wiring delay amount) becomes equal to each other.

Next, the input buffer 13 and the STBD 80 are connected by the wiring of the wiring length L. Next, Here, the actual skew D1 is the sum of the delay amount by the input buffer 13 and the delay amount by the wiring of the wiring length L.

Next, the delay circuit 32 having the delay amount A will be examined. The actual delay amount D2 of the delay circuit (output buffer) 34 is set to be equal to the delay amount D2 of the output buffer 34 (output buffer 34), as indicated by D1 + D2 And the delay amount due to the wiring of the wiring length L.

The delay circuit having the delay amount A has the same pattern as that of the pattern 82 forming the skew D1 and the pattern 83 forming the delay amount D2 with respect to the pattern 81 forming the skew D1. (84).

This layout makes it possible to more accurately synchronize the corrected internal clock CK 'with the external clock CK since the delay amounts A, D1 and D2 can be determined in consideration of the wiring delay.

As described above, according to the clock synchronization delay control circuit of the present invention, the following effects can be obtained.

Each delay unit has a state maintaining unit to precisely copy the time? F until the pulse of the internal clock (CLK) is generated after the generation of the delay imitation pulse (forward pulse) FCL1 to form? B, It is possible to input the backward pulse RCL1 to the delay circuit having the delay amount D2 after the time? B (=? F) after the pulse of the internal clock CLK is generated.

This view is schematically shown in Figs. 24 to 27. That is, in the initial state, as shown in Fig. 24, the forward pulse delay circuit and the backward pulse delay circuit of the delay units 33-1 to 33-n are all outputting "0".

25, after the forward pulse is input to the delay unit 33-4 and the state maintaining unit of the delay unit 33-4 becomes the set state S, the internal clock CLK is set to the set state S, , The delay units 33-5 to 33-n of the state-holding unit reset state R output &quot; 1 &quot;.

That is, the front F1 of the forward pulse and the front F2 of the backward pulse coincide with each other, so that the delay amount? F and the delay amount? B become the same.

Thereafter, as shown in FIG. 26 and FIG. 27, the delay unit 33-4 is initialized to the reset state R and a backward pulse is formed, and the backward pulse is delayed by the delay units 33-3, 33-2, and output from the delay unit 33-1.

With this operation, it is possible to generate a corrected internal clock CK 'that is exactly synchronized with the external clock CK, and data transfer using a high-speed clock can be achieved.

It is also possible to monitor the signal output from the final stage of the delay unit so that the internal clock CLK is used as it is according to the frequency of the external clock CK or the corrected internal clock CK 'synchronized with the external clock CK Can be used.

That is, in the case of exchanging data in synchronization with the high-speed clock in which the skew of the external clock CK and the internal clock CLK is a problem, a corrected internal clock CK 'synchronized with the external clock CK is used, In the case where data is received in synchronization with a clock in which skew is not a problem, the internal clock CLK is used as usual.

Whether to use the internal clock or the correction internal clock is determined by the number of delay units.

Therefore, when the cycle (cycle time) of the external clock CK is long, there is no occurrence of a situation in which the discrepancy between the external clock CK and the corrected internal clock CK 'increases.

The pattern of the delay amount A is set to the same pattern as the pattern for forming the delay amounts Dl and D2 in consideration of the wiring delay in view of the point that the delay amount A is represented by (D1 + D2) Respectively.

Therefore, by a simplified layout, it is possible to constitute a system for accurately synchronizing the corrected internal clock CK 'in the memory chip with the external clock CK.

Further, like the synchronous DRAM, the present invention is effective for a memory in which the internal clock is temporarily suspended and the data is transferred in synchronization with the high-speed clock whose frequency changes.

FIG. 28 shows the clock control circuit of FIG. 2 in a simplified manner

D2 is a delay circuit having a delay amount D2; A is a delay circuit having a delay amount D1 + D2; and STBD (Synchronous Traced Backward Delay) is a delay circuit having a delay amount D1. Array. STBD consists of FD (Forward Delay) and BD (Backward Delay).

According to the clock control circuit having such a configuration, as described above, the phase of the external clock CK and the phase of the internal clock CLK coincide completely (skew is eliminated). Thus, the clock control circuit with the above configuration is effective when outputting data when the external clock CK rises (from the "L" to the "H" transition).

On the other hand, recently, when the period of the external clock CK is T, the internal clock (CLK) having no skew and the internal clock (CK) having a phase delayed by (k / CKD) (k, j are natural numbers, and j > k).

For example, in the case of outputting data when the external clock CK is rising and falling, the internal clock CK 'having the phase coincident with the external clock CK and the external clock CK' It is necessary to generate an internal clock (CKD) whose phase is delayed by T / 2 (=?).

In this case, if the phase of the internal clock CKD is not delayed by exactly T / 2 (=?) With respect to the phase of the external clock, the data window at the time of data output , There is a possibility of outputting erroneous data.

Therefore, a clock control circuit capable of correctly generating an internal clock (CKD) whose phase is delayed by (k / j) x T with respect to the external clock CK will be described below.

FIG. 29 shows a first example of the configuration of the clock control circuit of the present invention.

This clock control circuit generates an internal clock CKD whose phase is delayed by T / 2 (=?) With respect to the external clock CK in conjunction with the internal clock CK 'in phase with the external clock CK (T is the cycle of the external clock).

The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CKD having a skew of D1 with respect to the external clock CK. The internal clock CKD is input to a delay circuit 32 having a delay amount A and the delay circuit 32 outputs a delayed oscillation pulse CL (forward pulse FCL1).

The delay imitation pulse CL is input to the FD (forward delay) of STBD (Synchronous Traced Backward Delay). The backward pulse is generated in BD (Backward Delay) and HBD (Half Backward Delay) after the delay imitation pulse CL advances by the amount of delay DELTA in the FD.

The backward pulse RCL in the BD is output from the BD after being exactly backward by the amount of delay DELTA. Further, the backward pulse (HCL) in the HBD is output from the HBD after being exactly backward by the delay amount (? / 2).

The internal clock (CKD) is input to the BD and the HBD, and determines the generation timing of the backward pulse. The inverted internal clock (/ CLK) inverted by the inverter 35 by the internal clock CLK is input to the FD, and determines the period (delay amount)? During which the forward pulse advances.

The backward pulse RCL becomes the corrected internal clock CK 'that coincides with the phase of the external clock CK through the delay circuit 34 having the delay amount D1 + (D2 x 2). The backward pulse HCL passes through the delay circuit 36 having the delay amount D2 and becomes the internal clock CLK whose phase is delayed by T / 2 (= 180 degrees) with respect to the external clock CK .

Here, the delay amount A of the delay circuit 32 is set to 2 占 (D1 + D2).

FIG. 30 shows a second example of the configuration of the clock control circuit of the present invention.

The clock control circuit includes an internal clock CKD whose phase is matched with the external clock CK and an internal clock CKD whose phase is delayed by T / j (= 2π / j) with respect to the external clock CK. (T is the period of the external clock, and j is a natural number).

The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CLK having a skew of D1 with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A and the delay circuit 32 outputs the delayed imitation pulse CL (forward pulse FCL1).

The delay imitation pulse CL is input to the FD (forward delay) of STBD (Synchronous Traced Blackward Delay). The backward pulse is generated in BD (Backward Delay) and 1 / jBD (Backward Delay) after the delay imitation pulse CL advances by the amount of delay DELTA in the FD.

The backward pulse RCL in the BD is output from the BD after being exactly backward by the amount of delay DELTA. Further, the backward pulse (1 / jCL) in 1 / jBD is output from 1 / jBD after exactly backward by the amount of delay (? / J).

The internal clock CLK is output to the BD and 1 / jBD, and determines the timing of generation of the backward pulse. The inversion internal clock (/ CLK) inverted by the inverter 35 by the internal clock CLK is input to the FD, and determines the period (delay amount)? During which the forward pulse advances

When the backward pulse RCL passes through the delay circuit 34 having the delay amount [(j-1) x D1 + j x D2], the corrected internal clock CK 'coinciding with the phase of the external clock CK do. When the backward pulse 1 / jCL passes through the delay circuit 36 having the delay amount D2, the internal clock (internal clock) having the phase delayed by T / j (= 360 ° / n) with respect to the external clock CK CKD).

Here, the delay amount A of the delay circuit 32 is set to j × (D1 + D2).

FIG. 31 shows a third example of the configuration of the clock control circuit of the present invention.

This clock control circuit has an internal clock CK 'in phase with the external clock CK and a phase of (k / j) × T (= 2π × k / j) with respect to the external clock CK (T is the period of the external clock, k and j are natural numbers, j &gt; k).

The external clock CK is input to the input buffer 13 having a delay amount (k x D1). The input buffer 13 outputs an internal clock CLK having a skew of k x D1 with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A and the delay circuit 32 outputs the delayed imitation pulse CL (forward pulse FCL1).

The delay imitation pulse CL is input to the FD (forward delay) of STBD (Synchronous Traced Backward Delay). The backward pulse is generated in BD (Backward Delay) and k / jBD (Backward Belay) after the delay imitation pulse CL advances by the amount of delay DELTA in the FD.

The backward pulse RCL in the BD is output from the BD after being exactly backward by the amount of delay DELTA. Further, the backward pulse (k / jCL) in k / jBD is output from k / jBD after being backwardly delayed by exactly the delay amount [Delta] x (k / j)

The internal clock CLK is input to the BD and k / jBD, and determines the generation timing of the backward pulse. The inversion internal clock (/ CLK) inverted by the inverter 35 by the internal clock CLK is input to the FD and determines the period (delay amount)? During which the forward pulse advances.

The backward pulse RCL becomes the corrected internal clock CK 'that coincides with the phase of the external clock CK through the delay circuit 34 having the delay amount [(j-k) x D1 + j x D2]. Further, when the backward pulse (k / jCL) passes through the delay circuit 36 having the delay amount (k x D2), the phase is Tx (k / j) / j). &lt; / RTI &gt;

Here, the delay amount A of the delay circuit 32 is set to j x (D1 + D2).

FIG. 32 shows a fourth example of the configuration of the clock control circuit of the present invention.

This clock control circuit has an internal clock CK 'whose phases coincide with the external clock CK and a clock whose phase is T × (k / j) (= 2π × k / j) with respect to the external clock CK (T is the period of the external clock, k and j are natural numbers, j &gt; k).

The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CLK having a skew of D1 with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A and the delay circuit 32 outputs the delayed imitation pulse CL (forward pulse FCL1).

The delay imitation pulse CL is input to the FD (forward delay) of STBD (Synchronous Traced Backward Delay). The backward pulse is generated in BD (Backward Delay) and k / jBD (Backward Delay) after the delay imitation pearl (stitch) advances by the amount of delay DELTA in the FD.

The backward pulse RCL in the BD is output from the BD after being exactly backward by the amount of delay DELTA. Further, the backward pulse (k / jCL) in k / jBD is output from k / jBD after being backwardly delayed by exactly the delay amount [Delta] x (k / j)

The internal clock CLK is input to BD and k / jBD, and determines the generation timing of the backward pulse. The inversion internal clock (/ CLK) inverted by the inverter 35 by the internal clock CLK is input to the FD, and determines the period (delay amount)? During which the forward pulse advances

When the backward pulse RCL passes through the delay circuit 34 having the delay amount [(j-1) x D1 + j x D2], the corrected internal clock CK 'coinciding with the phase of the external clock CK do. When the backward pulse k / jCL passes through the delay circuit 36 having the delay amount [(k-1) x D1 + k x D2], the phase of the backward pulse k / j) (= 360 占 k / j).

Here, the delay amount A of the delay circuit 32 is set to j × (D1 + D2)

FIG. 33 shows a fifth example of the configuration of the clock control circuit of the present invention.

This clock control circuit has phases of T / 4 (= 90 °) and T / 2 (= 180 °) with respect to the external clock CK, together with an internal clock CK 'whose phases coincide with the external clock CK' And internal clocks CKQ, CKH, and CK3Q delayed by 3T / 4 (= 270 DEG), respectively.

The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CLK having a skew of D1 with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A and the delay circuit 32 outputs the delayed imitation pulse CL (forward pulse FCL1).

The delay imitation pulse CL is input to the FD (forward delay) of the SAD (Synchronous Adjustable Delay). The SAD includes Synchronous Traced Backward Delay (STBD), Synchronous Mirror Delay (SMD), and Measure Controlled DLL (MDLL).

The delayed impulse pulse CL advances by the amount of delay DELTA in the FD and then the driving pulses are generated in the backward delay (BD), the quarter backward delay (QBD), the half backward delay (HBD), and the 3QBD Is generated.

The backward pulse RCL in the BD is output from the BD after being delayed by the amount of delay DELTA (delay elements X). Further, the backward pulse QCL of the QBD is output from the QBD after being delayed by the delay amount DELTA x4 (delay device X / 4), and the backward pulse HCL in the HBD is delayed by DELTA / 2 ), And the backward pulse 3QCL in the 3QBD is output from the 3QBD after being backward by the amount of delay (3Δ / 4) (delay device 3X / 4) .

The internal clock (CLK) is input to BD, QBD, HBD, and 3QBD, respectively, and determines the generation timing of the backward pulse. The inverted internal clock (/ CLK) inverted by the inverter 35 by the internal clock CLK is input to the FD, and determines the period (delay amount)? During which the forward pulse advances.

The backward pulse RCL becomes the corrected internal clock CK 'that coincides with the phase of the external clock CK through the delay circuit 34 having the delay amount (D1 x 3 + D2 x 4).

Further, when the backward pulse QCL passes through the delay circuit 36a having the delay amount D2, it becomes the internal clock CKQ whose phase is delayed by T / 4 (= 90 degrees) with respect to the external clock CK .

When the backward pulse HCL passes through the delay circuit 36b having the delay amount D1 + D2 x 2, the internal clock signal whose phase is delayed by T / 2 (= 180 degrees) with respect to the external clock CK CKH).

Again, the backward pulse 3QCL is delayed by 3T / 4 (= 270 DEG) relative to the external clock CK through the delay circuit 36c having the delay amount (D1 x 2 + D2 x 3) Clock (CKD).

Here, the delay amount A of the delay circuit 32 is set to 4.times. (D1 + B2).

FIG. 34 shows the configuration of the clock control circuit of FIG. 32 in detail.

The external clock CK is applied to the memory input terminal 30. The external clock CK is input to the input buffer 13 having the delay amount D1. The input buffer 13 outputs an internal clock CLK having a skew of D1 with respect to the external clock CK. The internal clock CLK is input to the delay circuit 32 having the delay amount A and the delay circuit 32 outputs the forward pulse FCL1 (delayed imitation pulse CL).

The internal clock CLK and the inverted internal clock CLK which are inverted by the inverter 35 by the internal clock CLK are n (n is a natural number) delay units 33-1, 33-2, 33-n.

The n delay units 33-1, 33-2, ..., 33-n are connected in series with each other. The forward pulse FCL1 is input to the delay unit 33-1 at the initial stage and the backward pulse RCL1 is output from the delay unit 33-1 at the initial stage.

The control pulses P and / P to which the control pulse generating circuit 60 is output are input to the n delay units 33-1, 33-2, ..., 33-n. Further, the delay units 33-i (i = 1 to n) output control pulses Qi and / Qi. The control pulses (Qi, / Qi) are input to k / jBD (37).

The backward pulse RCL1 becomes the corrected internal clock CK 'by passing through the delay circuit 34 having the delay amount [(j-1) Dl + j D2].

The backward pulse (k / jCL) has a phase T (k / j) with respect to the external clock CK by passing through the delay circuit 36 having the delay amount [(k-1) x D1 + k x D2] (= 360 占 k / j).

FIG. 35 shows a first example of the configuration of the delay unit of FIG. 34 in detail.

The delay unit Ui (i = 1 to n) is composed of three parts: a forward pulse delay circuit, a state maintaining circuit, and a backward pulse delay circuit.

The forward pulse delay circuit is composed of three inverters 41 to 43. The inverters 41 and 42 are connected in series and the output signal FCLi of the delay unit of the preceding stage is inputted to the inverter 41 and the inverter 42 outputs the output signal FCLi + 1 to the delay unit of the following stage . The operation of the inverter (clock inverter) 41 is controlled by the control pulse / P. For example, when the control pulse / P is &quot; 1 &quot;, the inverter 41 becomes active.

The output terminal of the inverter 43 is connected to the input terminal of the inverter 42 and the input terminal of the inverter 43 is always supplied with the potential of "0" (for example, the ground potential). The operation of the inverter (clocked inverter) 43 is controlled by the control pulse P, for example, when the control pulse P is &quot; 1 &quot;, the inverter 43 becomes active.

The backward pulse delay circuit is composed of three inverters 44 to 46. The inverters 44 and 45 are connected in series and the output signal RCLi + 1 or the internal clock CLK of the delay unit at the subsequent stage is input to the inverter 44. The inverter 45 outputs the output signal (RCL1). The operation of the inverter (clocked inverter) 44 is controlled by the control pulse Qi, and the inverter 44 is activated only when, for example, the control pulse Qi is &quot; 1 &quot;.

The output terminal of the inverter 46 is connected to the input terminal of the inverter 45 and the internal clock CLK is always input to the input terminal of the inverter 46. The operation of the inverter (clocked inverter) 46 is controlled by the control pulse / Qi. For example, when the control pulse / Q is &quot; 1 &quot;, the inverter 46 becomes active.

The state retaining circuit is constituted by a state retaining section 47 and NAND circuits 48 and 49. The output signal FCLi and the inverted internal clock signal / CLK of the preceding stage delay unit are input to the NAND circuit 48 and the output signal of the inverter 45 and the internal clock signal CLK are input to the NAND circuit 49 .

The output signal of the NAND circuit 48 becomes the set input / S of the state holding unit 47 and the output signal of the NAND circuit 49 becomes the reset input / R of the state holding unit 47 have. Therefore, when the output signal (set input) / S of the NAND circuit 48 becomes &quot; 0 &quot;, the state holding unit 47 becomes the set state and the output signal of the NAND circuit 49 ) / R becomes &quot; 0 &quot;, the state holding unit 47 is in the reset state.

The state maintaining unit 47 is configured to output control pulses Q and / Q. The control pulse Q becomes "1" when the state maintaining unit 47 is in the set state and the control pulse / Q becomes "1" when the state maintaining unit 47 is in the reset state

The state maintaining unit 47 can use the same structure as the fourth state, for example.

In the delay unit Ui through which the forward pulse has passed, the control pulse Qi becomes &quot; H &quot;, and / Q becomes &quot; L &quot;. On the other hand, in the delay unit Ui through which the backward pulse passes, the control pulse Qi becomes &quot; L &quot;, and / Qi becomes &quot; H &quot;.

FIG. 36 illustrates a second example of the configuration of the delay unit of FIG. 34 in detail.

The delay unit Ui (i = 1 to n) is composed of three parts: a forward pulse delay circuit fdi, a state holding circuit sri, and a backward pulse delay circuit bdi.

The forward pulse delay circuit fdi is composed of five inverters 91 to 95. The inverters 91 to 93 are connected in series and the output signal FCLi of the delay unit of the preceding stage is inputted to the inverter 91 and the inverter 92 outputs the output signal FCLi + 1 to the delay unit of the following stage . The operation of the inverter (clocked inverter) 91 is controlled by the control pulse / P. For example, when the control pulse / P is &quot; 1 &quot;, the inverter 91 becomes active.

The output terminal of the inverter 94 is connected to the output terminal of the inverter 91 and at the same time is connected to the input terminal of the inverters 92 and 95. The input terminal of the inverter 94 is always connected to the ground potential ) Is applied. The operation of the inverter (clocked inverter) 94 is controlled by the control pulse P, for example, when the control pulse P is &quot; 1 &quot;, the inverter 94 becomes active.

The backward pulse delay circuit bdi is composed of five inverters 96-100. The inverters 96 to 98 are connected in series and the output signal RCLi + 1 or the internal clock CLK of the delay unit at the subsequent stage is input to the inverter 96. The inverter 97 outputs the output signal (RCLi). The operation of the inverter (clocked inverter) 96 is controlled by the control pulse Qi + 2, and the inverter 96 is activated only when, for example, the control pulse Qi + 2 is "1"

The output terminal of the inverter 99 is connected to the output terminal of the inverter 96 and is also connected to the input terminal of the inverters 97 and 100. The input terminal of the inverter 99 is always supplied with the internal clock CLK. The operation of the inverter (clocked inverter) 99 is controlled by the control pulse (/ Qi + 2). For example, when the control pulse (/ Q + 2) .

The state retaining circuit sri comprises P-channel MOS transistors 101 and 102, N-channel MOS transistors 103 and 104, and an inverter 105. [

The P-channel MOS transistors 101 and 102 are connected in series between the power supply terminal and the node Z and the N-channel MOS transistors 103 and 104 are connected in series between the ground terminal and the node Z.

The clock signal / CLK obtained by inverting the internal clock CLK is input to the gates of the MOS transistors 101 and 104 and the output signal of the delay unit Ui-3 / RCLi- 3 is input to the gate of the MOS transistor 103 and the output signal FFCLi of the delay unit Ui-1 is input to the gate of the MOS transistor 103. [

The input terminal of the inverter 105 is connected to the node Z and the control pulse Qi is outputted from the output terminal of the inverter 105. [ And the control pulse / Qi is output from the node Z. [

37 and 38 show an example of the configuration of k / jBD in Fig. 34. Fig.

In this example, a case where k is 1 and j is 2, that is, a case where the phase is delayed by T / 2 with respect to the external clock will be described. In this case, k / jBD becomes HBD (Half Backward Delay).

The HBD is composed of m delay units bdi (i = 1 to m) connected in series (m is a natural number). The configuration of each delay unit bdi is the same as that of the backward pulse delay circuit bdi of the delay unit Ui of SAD (Synchronous Adjustable Delay).

Thus, the ratio of the delay amount of the backward pulse in the BD to the backward pulse amount in the HBD is the ratio of the number of delay units in the BD to the number of the erratic units in the HBD, that is, the BD Of the number of delay units of the HBD and the number of delay units of the HBD.

Specifically, in this example, n delay units Ui (i = 1 to n) and m delay units bdi (i = 1 to m) are denoted by r (r is a natural number) 1), B (2), ... , B (r)].

For example, the block B (1) is composed of two delay units U1 and U2 and one delay unit bd1, and the control pulses Q1 and / Q2 output from the delay unit U1 and Either one of the control pulses Q2 and / Q2 output from the delay unit U2 is given to the delay unit bd1.

Similarly, the block B (r) is composed of two delay units Un-1, Un and one delay unit bdm, and the control pulses Qn-1, / Qn-1 output from the delay unit Un and the control pulses Qn and / Qn output from the delay unit Un to the delay unit bdm.

That is, in this example, one delay unit of the HBD is provided for the two delay units of the SAD. Thus, in the BD, the backward pulse is delayed by?, Whereas in HBD, the backward pulse is delayed by? / 1.

In the case of this example, r and m are equally m = n / 2. J = 2 (equal to the number of delay units of the SAD in one block), k = 1 (the number of delay units of one HBD in one block) .

The total number n of delay units of the SAD is j (2 in this example) x r, and the total number m of delay units of the HBD is k (1 in this example) x r.

It is also preferable that the delay units bd1 to bdm of the HBD are arranged evenly with respect to the delay units U1 to Un of the SAD. That is, if one delay unit of the HBD is associated with two delay units to which the SAD is connected, a delay of exactly? / 2 can be generated.

FIG. 39 shows the construction of the delay unit bdi in the HBD.

The present example is an example in which the delay unit Ui of FIG. 35 is used. That is, since the backward pulse delay circuit of the delay unit Ui is composed of the three inverters 44 to 46, the delay unit bdi in the HBD is also composed of the three inverters 44 'to 46' .

The inverters 44 'and 45' are connected in series, and the output signal (HCLi + 1) or the internal clock (CLK) of the delay unit at the subsequent stage is input to the inverter 44 '. The inverter 45' And outputs an output signal HCLi to the unit. The operation of the inverter (clocked inverter) 44 'is controlled by the control pulse Qi, and the inverter 44' is activated only when, for example, the control pulse Qi is &quot; 1 &quot;.

The output terminal of the inverter 46 'is connected to the input terminal of the inverter 45', and the internal clock CLK is always inputted to the input terminal of the inverter 46 '. The operation of the inverter (clocked inverter) 46 'is controlled by the control pulse / Qi. For example, when the control pulse / Qi is &quot; 1 &quot;, the inverter 46 becomes active.

FIG. 40 shows a symbolized delay unit bdi of FIG. 39. Therefore, the circuit of FIG. 39 and the circuit of FIG. 40 show the same thing.

FIG. 41 shows an example of the configuration of k / jBD in FIG.

In this example, the case where j is 3 and k is 1, that is, the phase is delayed by T / 3 with respect to the external clock will be described.

1 / 3BD is composed of m delay units bdi (i = 1 to m) connected in series.

The configuration of each delay unit bdi is the same as that of the backward pulse delay circuit bdi of the delay unit ui of SAD (Synchronous Adjustable Delay).

Therefore, the ratio of the delay amount of the backward pulse in BD and the backward pulse amount in 1/3 BD is the ratio of the number of delay units in BD to the number of delay units in 1/3 BD, exactly 1 Becomes equal to the ratio of the number of delay units of the BD and the number of delay units of 1/3 BD in one block.

Specifically, in this example, n delay units Ui (i = 1 to n) and m delay units bdi (i = 1 to m) are divided into r blocks B (1) ), ... , B (r)].

For example, the block B (1) is composed of three delay units U1 to U2 and one delay unit bdl, and the control pulses Q1 and / Q1 output from the delay unit U1 are To the delay unit bd1. However, the control pulses Q1 and / Q1 may be changed to give the control pulse output from the delay unit U2 or the delay unit U3 to the delay unit bdi.

That is, in this example, one delay unit of 1/3 BD is provided for the three delay units of the SAD. Therefore, in the BD, the backward pulse is delayed by?, Whereas in 1/3 BD, the backward pulse is delayed by? / 3.

That is, in the case of this example, r and m are equally m = n / 3. In the above description, the frequent natural numbers j and k appearing in the above description are j = 3 (equal to the number of delay units of SAD in one block), k = 1 (equal to the number of delay units of HBD in one block ).

The total number n of delay units of the SAD is j (3 in this example) x r, and the total number m of delay units of the HBD is k (1 in this example) x r.

It is also preferable to arrange the 1 / 3BD delay units bd1 to bdm equally with respect to the delay units U1 to Un of the SAD. That is, if one delay unit of 1/3 BD is mapped to three delay units to which SAD is connected, it is possible to generate a delay of exactly? / 3.

FIG. 42 shows an example of the configuration of k / jBD in FIG. 34.

In this example, the case where k is 2 and j is 3, that is, the phase is 2T / 3 lower than the external clock will be described.

2 / 3BD is composed of m delay units bdi (i = 1 to n) connected in series. The configuration of each delay unit bdi is the same as that of the backward pulse delay circuit bdi of the delay unit Ui of SAD (Synchronous Adjustable Delay).

Therefore, the ratio of the delay amount of the backward pulse in BD and the backward pulse amount in 2 / 3BD is the ratio of the number of delay units in BD to the number of delay units in 2 / 3BD, Is equal to the ratio of the number of delay units of the BD and the number of delay units of 2 / 3BD in the BD.

Specifically, in this example, n delay units Ui (i = 1 to n) and m delay units bdi (i = 1 to m) are divided into r blocks B (1) ), ... , B (r)].

For example, the block B (1) is composed of three delay units U1 to U3 and two delay units bd1 and bd2, and the control pulses Q1 and / Q1 To the delay unit bdi and the control pulses Q3 and / Q3 output from the delay unit U3 to the delay unit bd2.

However, the control pulses Q1, / Q1, Q2 and / Q2 may be supplied to the delay units bd1 and bd2 by changing the control pulses Q1 and / Q1, Q3 and / Q3, Q2, / Q2, Q3, / Q3 may be given to the delay units ba1, bd2.

That is, in this example, two delay units of 2 / 3BD are provided for the three delay units of the SAD. Therefore, in BD, the backward pulse is delayed by?, Whereas in 2 / 3BD, the backward pulse is delayed by 2? / 3.

In the case of this example, there is a relation of m = 2n / 3. In the above description, the frequent small natural numbers j and k are j = 3 (equal to the number of delay units of SAD in one block), k = 2 (equal to the number of delay units of HBD in one block ).

The total number n of the delay units of the SAD is j (3 in this example) x r, and the total number m of the delay units of the HBD is k (2 in this example) x r. Also, since m / n = k x r / j x r, there is a relation of m / n = k / j.

It is also preferable to arrange the 2 / 3BD delay units bd1 to bdm equally with respect to the delay units U1 to Un of the SAD. That is, if two delay units of 2 / 3BD are associated with the three delay units to which the SAD is connected, it is possible to generate a delay of exactly 2? / 3.

FIG. 43 generally shows the configuration of k / jBD of FIG. FIG. 44 shows the configuration of k / jBD in one block [B (i)] of FIG.

SAD is composed of r blocks [B (1) to B (r)]. In the SAD, each block contains j delay units. Similarly, k / jBD consists of r blocks [B (1) to B (r)]. Each block in k / jBD contains k delay units.

j and k are natural numbers having a small number of each other, and j > k is generally set.

Since there are r blocks, the total number (n) of delay units of the SAD is r x j, and the total number (m) of delay units of k / jBD is r x k.

The number of blocks of SAD and the number of blocks of k / jBD are the same, for example, block B (1) of SAD corresponds to block 1 of k / / jBD, and the block B (r) of the SAD corresponds to the block r of k / jBD.

For example, in block 1 of the SAD, j control pulses Q1, / Q1, Q2, / Q2, ..., Qj, / Qj are generated. However, only k (<j) combinations in the control pulse of the j-th group are selected, and the k control pulses are supplied to the block 1 of k / jBB.

The k control pulses are regularly or evenly selected from the j-th control pulses Q1, / Q1, Q2, / Q2, ..., Qj, / Qj.

Further, the selected k control pulses are regularly given to k corresponding delay units of k / jBD. For example, when the control pulses Q1 and / Q1, Q1 and / Q2 are selected, the control pulses Q1 and / Q1 are applied to the delay unit bd1 of k / jBD ) And the control pulses Q2 and / Q2 to the delay unit bd2 of k / jBD (not to bd1).

According to such a configuration, the ratio of the number of delay units of SAD to the number of delay units of k / jBD, kj = m / n is always satisfied regardless of the position of the delay unit in which the forward pulse of the SAD reaches. Therefore, irrespective of the position of the delay unit to which the forward pulse arrives, it is possible to generate a delay amount of k / j DELTA in k / jBD.

Next, the principle of the present invention (in the example of FIG. 31) will be described with reference to FIG. 45.

The skew width (delay amount) of the external clock CK and the internal clock CLK is k × D1 and the cycle of the external clock CK and the internal clock CLK is T.

The delayed mimic pulse CL is generated at a point of time A elapsed from the time when the first pulse of the internal clock CLK is generated (the time of the rise). In this case, the time from when the delay imitation pulse CL is generated to when the second pulse of the internal clock CLK is generated is? F.

This time Δf is copied to make Δb and the delay imitation pulse RCL (1) is generated at the time point when the time (2 × Δ) (Δf = Δb = Δ) ). Then, the time point at which the time (A) elapses from the point in time at which the delay imitation pulse (RCL) is generated coincides with the time point at which the third pulse of the internal clock (CLK) occurs. (A + W) &lt; T. And W is the width of delay imitation pulses CL and RCL.

(Jk) × D1 + j × D2 from the time point when the delay imitation pulse RCL is generated to the time point when the third pulse of the external clock CK is generated and the delay imitation pulse RCL to the time jk × D1 + j D2, a corrected internal clock CK 'that matches the timing of the external clock CK can be obtained.

That is, a delay circuit for generating the delay amounts A, (2 占?), (Jk) 占 D1 + j 占 D2 is formed and the internal clock CLK is multiplied by the time A + × D1 + j × D2}, it becomes possible to obtain the corrected internal clock CK 'that matches the timing of the external clock CK.

The delay amount (2 × Δ) is generated by the SAD, and the delay amount [(j-k) × D1 + j × D2] is generated by the delay element. The delay amount A is as follows.

From the relationship of FIG. 50,

Can be obtained.

From equation (1), T = A + Δ ... A + 2? + J (D1 + D2) = 2? T + 3? (4) can be obtained.

From equations (3) and (4)

.

The principle of generating the internal clock CKD delayed by (k / j) x T with respect to the external clock CK is as follows.

(K / j) DELTA] (DELTA = DELTA f = DELTA b), and at the point in time [Delta] + (k / jCL) is generated. Also, the internal clock CKD is generated at the time point when the time (k x D2) elapses from when the delayed pulse (k / jCL) occurs.

At this time, as apparent from the 45th road, the internal clock CKD is set to the external clock CK,

.

When the equation (6) is modified,

.

(7) can be obtained from the equations (3) and (5)

.

That is, the internal clock CKD means that the phase is behind the external clock CK by (k / j) × T.

Therefore, the delay circuit for generating the delay amount [A, DELTA + (k / j) DELTA, k D2) + k D2], it is possible to obtain an internal clock CKD whose phase is delayed by (k / j) xT with respect to the external clock CK.

The delay amount DELTA is generated by the FD of the SAD, and the delay amount (k x D2) is generated by the delay element. The delay amount A is set to j (D1 + D2) as shown in expression (5) by the above-described method.

Next, the principle of the present invention (in the case of the example of FIG. 32) will be described with reference to FIG.

The skew width (delay amount) of the external clock CK and the internal clock CLK is D1 and the cycle of the external clock CK and the internal clock CLK is T. [

The delayed mimic pulse CL is generated at a point of time A elapsed from the time when the first pulse of the internal clock CLK has been generated In this case, the time from when the delay imitation pulse CL is generated to when the second pulse of the internal clock CLK is generated is? F.

Further, this time? F is copied to make? B, and delay imitation. The delay imitation pulse RCL is generated at the time point when the time (2xA) (DELTA f = DELTA b = DELTA) has elapsed from the point of time when the pulse CL is generated. Then, the time point at which the time (A) elapses from the point in time at which the delay mimic pulse (RCL) is generated coincides with the time point at which the third pulse of the internal clock (CLK) occurs. (A + W) < T. And W is the width of delay imitation pulses CL and RCL.

By delaying the time from when the delay imitation pulse RCL is generated to when the third pulse of the external clock CK is generated by (j-1) x D1 + j x D2, the timing of the external clock CK The corrected internal clock CK 'can be obtained.

That is, a delay circuit for generating the delay amount [(A), (2xA), (j-1) xD1 + jD2] is formed and the internal clock CLK is set to the time [A + + {(j-1) x D1 + j x D2}], it becomes possible to obtain the corrected internal clock CK 'that matches the timing of the external clock CK.

The delay amount (2 × Δ) is generated by the SAD, and the delay amount [(j-k) × D1 + j × D2] is generated by the delay element. The delay amount A is determined as follows.

From the relationship of FIG. 50,

You can get

From equation (9), T = A + Δ ... A + 2? + J (D1 + D? 2) = 2T? (12) can be obtained.

From equations (11) and (12)

Become

The principle of generating the internal clock CKD delayed by (k / j) x T with respect to the external clock CK is as follows.

(K / j) DELTA] (DELTA = DELTA f = DELTA b), and at the point in time [Delta] + (k / jCL) is generated. Further, the internal clock CKD is generated at the time point when the time [(k-1) D2 + k D2] elapses from the point in time at which the delay pulse k / jCL is generated.

At this time, as apparent from the 46th road, the internal clock (CKD) corresponds to the external clock (CK)

.

When the equation (14) is modified,

.

(15) can be obtained from the equations (11) and (12)

.

That is, the internal clock CKD means that the phase is behind the external clock CK by (k / j) × T.

Therefore, a delay circuit for generating the delay amount [A, [Delta] + (k / j) x, k x D2) is formed, and the internal clock CLK is multiplied by the time [A + + k D2], it is possible to obtain an internal clock CKD whose phase is delayed by (k / j) xT with respect to the external clock CK.

The delay amount DELTA is generated by the FD of the SAD, and the delay amount (k x B2) is generated by the delay element. The delay amount A is set to j (D1 + D2) as shown in expression (13) by the above-described method.

FIG. 47 shows a connection relationship between a controller for generating an external clock and receiving data, and a memory for outputting data based on an internal clock generated from the external clock.

In the above-described example, a technique of clearly determining the phase relationship between the external clock and the internal clock and outputting the correct data from the memory has been described. In this example, description will be given of a technique by which the controller can correctly receive correct data read from such a memory.

Generally, the memory system includes a controller (CPU) and a plurality of memories (IC). It takes a certain time for the external clock CK to reach the memories 1 and 2 from the controller. Therefore, first, the wiring lengths of the external clocks from the controller to the memories 1 and 2 are made equal.

Further, the memory 1 or the memory 2 outputs data based on an internal clock having a constant phase relationship with respect to the external clock CK. The data reaches the controller via the data bus.

The controller displays data from the memory 1 or the memory 2 but the data is outputted from the memory 1 or the memory 2 by the wiring length of the data bus or the wiring capacity or the like It takes a while.

That is, in order to obtain accurate data, the controller needs to take data by timing taking into account the transmission time of data on the data bus.

Therefore, a dummy memory (IC) having the same external clock input capacity as the memories 1 and 2 is used. The wiring length of the external clock from the controller to the dummy memory is made equal to the wiring length of the external clock from the controller to each of the memories 1 and 2.

Further, the external clock CK input to the dummy IC is returned to the controller, which is used as a return clock.

The return clock determines the timing at which the controller receives the output data of the memory 1 or the memory 2. [ Therefore, the wiring length of the return clock from the dummy memory to the controller becomes equal to the data bus length from the memory 1 or the memory 2 to the controller.

Thus, the controller receives data from the memory 1 or the memory 2 based on the return clock. Therefore, the erroneous data is not input to the controller.

As described above, according to the clock control circuit of the present invention, the following effects can be obtained.

It is possible to stably generate an internal clock that always has a constant phase relationship with respect to the external clock. In addition, even if the cycle of the external clock changes, the internal clock always has a constant phase relationship with respect to the external clock I have.

Therefore, the present invention is most suitable for controlling a data input / output circuit of a clock synchronous DRAM such as a so-called synchronous memory.

In the case of outputting a plurality of data in one cycle of the clock by controlling the data output by dividing the cycle of the clock, a plurality of internal clocks whose phases are shifted by a predetermined amount with respect to the external clock are required, According to the invention, such a plurality of internal clocks can be easily generated without using a complicated system such as a PLL.

Claims (39)

Each of the delay units comprising: a forward pulse delay circuit for delaying the forward pulse by a predetermined delay amount and transmitting the delayed forward pulse to a delay unit at the subsequent stage; and a delay circuit for delaying the backward pulse by the predetermined delay amount A delay circuit for delaying the output of the delay unit of the preceding stage and a delay circuit for delaying the output of the delay unit of the previous stage when the pulse of the internal clock is inputted to the plurality of delay units; Wherein the forward pulse is input to a delay unit at an initial stage and a front edge of the backward pulse is input to a delay unit of the internal When a pulse of a clock is input to the plurality of delay units, Wherein the delay unit is formed in a delay unit close to the delay unit of the initial stage, and the backward pulse is outputted from the delay unit of the initial stage. The apparatus according to claim 1, wherein edges other than the front edge of the backward pulse are arranged such that, when a pulse of the internal clock is not inputted to the plurality of delay units, Gt; delay &lt; / RTI &gt; Each of the delay units comprising: a forward pulse delay circuit for delaying the forward pulse by a predetermined delay amount and transmitting the delayed forward pulse to a delay unit at the subsequent stage; and a delay circuit for delaying the backward pulse by the predetermined delay amount A delay circuit for delaying the output of the delay unit of the preceding stage and a delay circuit for delaying the output of the delay unit of the previous stage when the pulse of the internal clock is inputted to the plurality of delay units; Wherein the forward pulse is input to a delay unit at an initial stage and a front edge of the backward pulse is input to a delay unit of the internal When a pulse of a clock is input to the plurality of delay units, Wherein the delay unit is formed in a delay unit close to an initial stage delay unit, and the backward pulse is output from the delay unit of the initial stage; and an internal clock having a delay amount (D1) A first delay circuit for delaying a pulse of the internal clock by a delay amount A and supplying the delayed pulse as a forward pulse to a delay unit at an initial stage of the delay array; And a second delay circuit for delaying the backward pulse by a delay amount D2 and outputting the delayed backward pulse as a correction internal clock, wherein the delay amount D1, the delay amount D2 and the delay amount A are A = D1 + D2. &Lt; / RTI &gt; The apparatus according to claim 3, wherein the pulses of the internal clock are constituted by a plurality of delay units connected in series, each of the delay units including a forward pulse delay for delaying the forward pulse by a predetermined delay amount, A backward pulse delay circuit for delaying the backward pulse by the predetermined delay amount and transmitting the delayed backward pulse to the delay unit of the previous stage; and, when the forward pulse is inputted when the pulse of the internal clock is not inputted to the plurality of delay units, And a state holding unit that is set to a reset state when the backward pulse is input when a pulse of the internal clock is input to the plurality of delay units, And a front edge of the backward pulse is input to the plurality of delay units when a pulse of the internal clock is input to the plurality of delay units Is formed in a delay unit closest to the delay unit of the initial stage among the delay units of the reset state, and the backward pulse is outputted from the delay unit of the initial stage And a control pulse generating circuit for generating control pulses for initializing the forward pulse delay circuits of the plurality of delay units within a period from when the forward pulse is supplied to the delay unit at the initial stage Clock synchronous delay control circuit. The apparatus according to claim 3, wherein the forward pulse is composed of a plurality of delay units connected in series, each of the delay units comprising: an advancing pulse delay circuit for delaying the forward pulse by a predetermined delay amount and transmitting the delayed forward delay to the delay unit; A backward pulse delay circuit for delaying the backward pulse by the predetermined delay amount and transmitting the delayed backward pulse to the delay unit of the previous stage; and, when the forward pulse is inputted when the internal clock pulse is not inputted to the plurality of delay units, And a state holding unit that is set to a reset state when the backward pulse is input when a pulse of the internal clock is input to the plurality of delay units, and the forward pulse is input to a delay unit of an initial stage , And the front edge of the backward pulse is a state in which when the pulse of the internal clock is input to the plurality of delay units, And the backward pulse is output from the delay unit of the initial stage, characterized in that the backward pulse is output from the delay unit of the final stage of the delay array, And means for interrupting a backward pulse output from the delay unit at the initial stage and controlling the pulse of the internal clock to be output from the second delay circuit instead of the backward pulse, Delay control circuit. 6. The semiconductor memory device according to claim 5, wherein the means initializes the second delay circuit based on a backward pulse output from the delay unit of the initial stage after a pulse of the internal clock is output from the second delay circuit Clock synchronous delay control circuit. The apparatus of claim 3, further comprising: a plurality of delay units connected in series, each delay unit comprising: an advancing pulse delay circuit for delaying a forward pulse by a predetermined delay amount and delivering the forward pulse to a delay unit at a subsequent stage; A backward pulse delay circuit for delaying a predetermined delay amount to a delay unit of the preceding stage and a set state when the forward pulse is inputted when a pulse of an internal clock is not inputted to the plurality of delay units, And a state holding unit that is set to a reset state when the backward pulse is input when a pulse of a clock is input to the plurality of delay units, wherein the forward pulse is input to a delay unit of an initial stage, When the pulse of the internal clock is inputted to the plurality of delay units, the state edge of the state- Characterized in that the delay array is formed at a delay unit nearest to the delay unit of the initial stage among the plurality of delay units and the backward pulse is outputted from the delay unit at the initial stage, Wherein the pattern of the first delay circuit is the same as the pattern of the wiring from the buffer and the buffer to the delay array and the second pattern from the second delay circuit and the delay array, And the second delay circuit is laid out so as to be constituted by a combination of the same pattern and the same pattern as the wiring pattern up to the second delay circuit. An input circuit for inputting the data from the bus; an output circuit for outputting the data to the bus; and an output circuit for outputting the data to the bus, And a plurality of delay units connected in series, each delay unit comprising: a forward pulse delay circuit for delaying the forward pulse by a predetermined delay amount and transmitting the delayed forward pulse to a delay unit at a subsequent stage; A delay pulse generation circuit for generating a delay pulse of the internal clock by the delay circuit of the preceding stage and outputting the pulse of the internal clock signal to the delay unit of the previous stage when the pulse of the internal clock is not inputted to the plurality of delay units; A state in which a reset pulse is inputted to the plurality of delay units, Wherein the front edge of the backward pulse is a delay unit of a state in which the state holding unit is in the reset state when a pulse of the internal clock is input to the plurality of delay units, Wherein the delay unit is formed in a delay unit nearest to the delay unit of the initial stage, and the backward pulse is outputted from the delay unit of the initial stage, and a delay array having a delay amount (D1) A first delay circuit for delaying a pulse of the internal clock by a delay amount A and supplying the delayed pulse as a forward pulse to a delay unit at an initial stage of the delay array; And a second delay circuit for delaying the backward pulse outputted from the delay circuit by a delay amount D2 and outputting it as a correction internal clock, And the delay amount (D2) and the delay amount (A) have a relation of A = D1 + D2, and the operation of the write / Characterized in that the operation of the input circuit or the output circuit is controlled by at least a corrected internal clock output from the second delay circuit of the clock synchronous delay control circuit . A control block for transferring data to the bus and generating an external clock, a memory cell array, a write / read circuit for writing or reading data to / from the memory cell array, An input circuit for inputting data from a bus; an output circuit for outputting the data to the bus; and a plurality of delay units connected in series, wherein each delay unit is configured to delay the forward pulse by a predetermined delay amount A backward pulse delay circuit for delaying the backward pulse by the predetermined delay amount and transmitting the backward pulse to the delay unit at the previous stage; and a pulse of the internal clock is input to the plurality of delay units The pulse of the internal clock is set to the set state, Wherein the forward pulse is input to a delay unit at an initial stage and a front edge of the backward pulse is input to a delay unit of the internal When a pulse of a clock is inputted to the plurality of delay units, the state holding unit is formed in a delay unit closest to the delay unit of the initial stage among the delay units of the reset state, and the backward pulse is generated from the delay unit of the initial stage A buffer having a delay amount D1 and generating an internal clock based on an external clock; and a delay circuit for delaying the pulse of the internal clock by a delay amount A, A first delay circuit for supplying a delayed pulse output from the delay unit at the initial stage to a delay unit at an initial stage of the array, The delay amount D2 and the delay amount A are delayed by a predetermined delay time D2 and output as a corrected internal clock, and the delay amount D1, the delay amount D2 and the delay amount A are expressed by the following equation: A = D1 + D2 And the operation of the write / read circuit is controlled by an internal clock output from the buffer of the clock synchronization delay control circuit, and the operation of the input / output circuit Wherein the operation is controlled by a corrected internal clock output from at least the second delay circuit of the clock synchronous delay control circuit, wherein the memory circuit memory circuit performs data transfer to the bus, And a memory block for receiving the synchronization signal. Each delay unit comprising a delay circuit for delaying the forward pulse and the backward pulse asynchronously by a predetermined delay amount, and a delay circuit for setting the set state by the forward pulse, Wherein the forward pulse is input to a delay unit of an initial stage and the front edge of the backward pulse is set to a state in which a pulse of the internal clock is input to the plurality of delay units Wherein the state maintaining unit is formed in a delay unit closest to the delay unit of the initial stage among the delay units of the reset state and the reverse pulse advances in a direction opposite to the advancing direction of the forward pulse, &Lt; / RTI &gt; Each of the first delay units includes an advancing pulse delay circuit for delaying the advancing pulse by a predetermined delay amount and delivering the advancing pulse to the delay unit at the subsequent stage, A first backward pulse delay circuit for delaying a pulse by a predetermined delay amount and transferring the pulse to a delay unit of the preceding stage; and a second backward pulse delay circuit for delaying the pulse when the pulse of the internal clock is not input to the plurality of first delay units, 1 state and is set to a second state when the first backward pulse is input when a pulse of the internal clock is input to the plurality of first delay units, Unit is constituted by a second backward pulse delay circuit for delaying the second backward pulse by the predetermined delay amount and delivering the second backward pulse to the preceding delay unit, And the front edge of the first backward pulse is input to the first delay unit when a pulse of the internal clock is input to the plurality of first delay units, The first backward pulse being generated from a first delay unit of the initial stage and the front edge of the second backward pulse being generated at a front edge of the first backward pulse, And the second backward pulse is output from a second delay unit at an initial stage, and the delay amount of the first backward pulse delay circuit and the second backward pulse And the delay amount of the pulse delay circuit is the same. The apparatus of claim 11, wherein the edges other than the front edge of the first backward pulse are arranged such that when a pulse of the internal clock is not input to the plurality of first delay units, Wherein the first delay unit is formed in the first unit closest to the first delay unit of the initial stage. 12. The delay array of claim 11, wherein the number of the first delay units and the number of the second delay units are different. 12. The delay array of claim 11, wherein the number of the second delay units is less than the number of the first delay units. 12. The apparatus according to claim 11, wherein one of the plurality of first delay units is constituted by one j delay units and one of k second delay units among the plurality of second delay units is constituted by the first Blocks constituting one second block corresponding to the number of the first delay units of the first block and a control pulse for controlling k operations of the j first delay units of the first block, Wherein j and k are natural numbers that are small, and j > k. The apparatus of claim 15, wherein the first delay unit comprises r (r is a natural number) blocks, the total number of the first delay units is n (= r x j) And the delay amount of the second backward pulse is (m / n) when the total number of the second units is m (= rxj) and the delay amount of the first backward pulse is? ) X DELTA. Each of the first delay units includes an advancing pulse delay circuit for delaying the advancing pulse by a predetermined delay amount and delivering the advancing pulse to the delay unit at the subsequent stage, A first backward pulse delay circuit for delaying a pulse by a predetermined delay amount and transferring the pulse to a delay unit of the preceding stage; and a second backward pulse delay circuit for delaying the pulse when the pulse of the internal clock is not input to the plurality of first delay units, 1 state and is set to a second state when the first backward pulse is input when a pulse of the internal clock is input to the plurality of first delay units, Unit is constituted by a second backward pulse delay circuit for delaying the second backward pulse by the predetermined delay amount and delivering the second backward pulse to the preceding delay unit, And the front edge of the first backward pulse is input to the first delay unit when a pulse of the internal clock is input to the plurality of first delay units, The first backward pulse being generated from a first delay unit of the initial stage and the front edge of the second backward pulse being generated at a front edge of the first backward pulse, And the second backward pulse is output from a second delay unit at an initial stage, and the delay amount of the first backward pulse delay circuit and the second backward pulse A buffer for generating the internal clock on the basis of an external clock and having a delay amount D1; A first delay circuit for delaying a pulse of the first delay unit output from the first delay unit at the initial stage by a delay amount A and supplying the delayed pulse as the forward pulse to the first delay unit at the initial stage; A second delay circuit for delaying the second backward pulse outputted from the second delay unit at the initial stage by a delay amount (k-1) × D1 + j × D2 and outputting it as a first corrected internal clock; -1) 占 D1 + k 占 D2 and outputs the result as a second corrected internal clock (where j and k are natural numbers that are close to each other and j> k), the delay amount D1 , The delay amount D2 and the delay amount (A) A = j x (D1 + D2) Of the clock control circuit. Each of the first delay units includes an advancing pulse delay circuit for delaying the advancing pulse by a predetermined delay amount and delivering the advancing pulse to the delay unit at the subsequent stage, A first backward pulse delay circuit for delaying a pulse by a predetermined delay amount and transferring the pulse to a delay unit of the preceding stage; and a second backward pulse delay circuit for delaying the pulse when the pulse of the internal clock is not input to the plurality of first delay units, 1 state and is set to a second state when the first backward pulse is input when a pulse of the internal clock is input to the plurality of first delay units, Unit is constituted by a second backward pulse delay circuit for delaying the second backward pulse by the predetermined delay amount and delivering the second backward pulse to the preceding delay unit, And the front edge of the first backward pulse is input to the first delay unit when a pulse of the internal clock is input to the plurality of first delay units, The first backward pulse being generated from a first delay unit of the initial stage and the front edge of the second backward pulse being generated at a front edge of the first backward pulse, And the second backward pulse is output from a second delay unit at an initial stage, and the delay amount of the first backward pulse delay circuit and the second backward pulse A buffer having a delay amount k x D1 and generating the internal clock based on an external clock; A first delay circuit for delaying a pulse of the lock by a delay amount A and supplying the delayed pulse as the forward pulse to the first delay unit of the initial stage; A second delay circuit for delaying the delay amount jk by D1 + j 占 D2 and outputting it as a first correction internal clock; and a second delay circuit for delaying the second backward pulse outputted from the second delay unit at the initial stage by a delay amount k D2 (Where j and k are natural numbers that are close to each other and j > k), and outputs the delay amount D1, the delay amount D2, and the delay amount D2 (A) has a relation of A = j x (D1 + D2). The method as claimed in claim 17, wherein, in a period from when the pulse of the internal clock is input to the plurality of first delay units to when the forward pulse is supplied to the first delay unit of the initial stage, Further comprising a control pulse generating circuit for generating a control pulse for initializing the forward pulse delay circuit of the unit. 18. The clock control circuit of claim 17, wherein the number of the first delay units and the number of the second delay units are different. 18. The clock control circuit according to claim 17, wherein the number of the second delay units is smaller than the number of the first delay units. The method as claimed in claim 17, wherein one of the plurality of first delay units is constituted by one j first delay units and one of k second delay units among the plurality of second delay units A second block corresponding to the first block and a second delay corresponding to k second delay of the second block based on a control pulse for controlling k operations of the j first delay units of the first block, And controls the operation of the unit. The apparatus according to claim 22, wherein the first delay unit comprises r (r is a natural number) blocks, the total number of the first delay units is n (= r x j) , And the total number of said second units is m (= r x j). The clock control circuit according to claim 23, wherein the second backward pulse delay circuit generates a delay amount of m / n (= k / j) of a delay amount generated by the first backward pulse delay circuit . The apparatus as claimed in claim 23, wherein j is 2, k is 1, and the second backward pulse delay circuit of the second delay unit counts the amount of delay generated by the first backward pulse delay circuit of the first delay unit And generates a half of the delay amount. The delay circuit according to claim 23, wherein k is 1 and the second backward pulse delay circuit of the second delay unit is delayed by 1 / j of a delay amount generated by the first backward pulse delay circuit of the first delay unit The clock control circuit generates a clock signal. A controller for controlling the plurality of memories; a dummy memory having an input capacity equal to an input capacity of the plurality of memories, with respect to an external clock outputted from the controller; The first wiring being arranged such that a delay time of the external clock of the external clock and a delay time of the external clock from the controller to the dummy memory are equal to each other; A data bus for introducing data from one of the memories to the controller and a second wiring for returning the external clock to the dummy memory as a return clock back to the controller, When the data is delayed And the dummy memory from becoming equal to the delay of the return of a clock to the controller, wherein the controller is a memory system, characterized in that takes the data on the basis of the return clock. An internal clock delayed by D1 (an external clock and a skew width (delay amount) of the internal clock) is input to the external clock, and after the delay time A has elapsed from the input of the internal clock, A second delay circuit for delaying the forward pulse by 2 占 후 and outputting a backward pulse; and a second delay circuit for receiving the backward pulse and outputting the delay time [(i-1) A delay circuit for outputting a corrected internal clock whose phase coincides with that of the external clock after passing through the first delay circuit after the forward pulse is generated, D is the skew width of the external clock and the internal clock, D2 is the time from when the delayed imitation pulse RCL1 is generated to the external clock (The time until the third pulse of the pulse CK is generated) The clock control circuit according to claim. A first delay circuit for receiving an internal clock delayed by m x D1 with respect to an external clock and outputting an advancing pulse after the delay time A has elapsed after the internal clock is input; (Jk) × D1 + j × D2 after the backward pulse is input, and then the external clock is input to the second delay circuit after the delay time Wherein j and k denote a natural number, j &gt; k, and DELTA k are the number of pulses of the internal clock when the forward pulse is generated after the generation of the forward pulse, A is j × (D1 + D2), D1 is the skew width of the external clock and the internal clock, and m is the total number of the second delay units. A first delay circuit for inputting an internal clock delayed by D1 with respect to an external clock and outputting a forward pulse after the internal clock is input and after the delay time A has elapsed; (k-1) x D1 + k x D2 after the backward pulse is input and the backward pulse is input, and a second delay circuit for delaying the delay time A third delay circuit for outputting a corrected internal clock whose phase is delayed by (k / j) × T with respect to the external clock, wherein j and k are a natural number, D is the period of the external clock, D1 is the skew width of the external clock and the internal clock, D2 is the delay time of the internal clock, From the time when the imitation pulse RCL1 is generated to the time when the third pulse of the external clock CK is generated] And a clock control circuit. A first delay circuit for inputting an internal clock delayed by k x D1 with respect to the external clock and outputting an advancing pulse after the delay time A has elapsed after the internal clock is input; a second delay circuit for outputting a backward pulse after the backward pulse is input and after the delay time (k x D2) has elapsed from the input of the backward pulse, A third delay circuit for outputting a corrected internal clock whose phase is delayed by a phase (k / j) × T with respect to the clock (where j and k are a natural number, D is the width of the skew of the internal clock, D2 is the delay time of the delayed clock signal CLK1 (RCL1) ) From the time when the third pulse of the external clock CK is generated to the time when the third pulse of the external clock CK is generated] That the compared clock control circuit according to claim. The method as claimed in claim 18, wherein, in a period from when the pulse of the internal clock is input to the plurality of first delay units to when the forward pulse is supplied to the first delay unit of the initial stage, Further comprising a control pulse generating circuit for generating a control pulse for initializing the forward pulse delay circuit of the unit. 19. The clock control circuit of claim 18, wherein the number of the first delay units and the number of the second delay units are different. 19. The clock control circuit according to claim 18, wherein the number of the second delay units is smaller than the number of the first delay units. 19. The apparatus according to claim 18, wherein one j first delay unit of the plurality of first delay units constitutes one first block, and the k second delay units of the plurality of second delay units A second block corresponding to the first block and a second delay corresponding to k second delay of the second block based on a control pulse for controlling k operations of the j first delay units of the first block, And controls the operation of the unit. The apparatus of claim 35, wherein the first delay unit comprises r (r is a natural number) blocks, the total number of the first delay units is n (= r x j) , And the total number of said second units is m (= r x j). 37. The clock control circuit according to claim 36, wherein the second backward pulse delay circuit generates a delay amount of m / n (= k / j) of the delay amount generated by the first backward pulse delay circuit . 37. The semiconductor device according to claim 36, wherein j is 2, k is 1, and the second backward pulse delay circuit of the second delay unit is a delay amount of the delay amount generated by the first backward pulse delay circuit of the first delay unit And generates a half of the delay amount. 37. The method of claim 36, wherein k is 1 and the second backward pulse delay circuit of the second delay unit is delayed by 1 / j of a delay amount generated by the first backward pulse delay circuit of the first delay unit The clock control circuit generates a clock signal.

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