JP3860546B2 - Clock control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a control circuit that uses a delay array to control the timing of an external clock generated by a CPU and the timing of an internal clock used in a memory (IC).
[0002]
[Prior art]
An increasing number of recent memories achieve high-speed data transfer by transferring data in synchronization with a clock. For example, in a clock synchronous DRAM such as a synchronous DRAM, data is exchanged with blocks such as a CPU in synchronization with clocks of 100 MHz and 250 MHz, respectively.
[0003]
In a system in which data is exchanged between blocks in synchronization with such a clock, there is a slight timing between an external clock given to a memory from a block such as a CPU and an internal clock generated inside the memory. There is a problem that the deviation, that is, the skew occurs.
[0004]
For example, when a 100 MHz external clock is used, one cycle is 10 nsec (nanoseconds). Therefore, if a deviation of 1 nsec occurs between the external clock and the internal clock, this deviation corresponds to 10% of one cycle time. This hinders high-speed synchronization control.
[0005]
In particular, when data is transferred from the memory to another block, the skew of the external clock and the internal clock directly affects the data output time of the memory and delays the data transfer time.
[0006]
FIG. 48 shows an example of a system that performs synchronous control using a high-speed clock. FIG. 49 shows the relationship between the external clock and the internal clock in the system of FIG.
[0007]
For example, an external clock CK generated by the CPU 12 is input to the memory (clock synchronous DRAM such as a synchronous DRAM) 11. The external clock CK is converted into the internal clock CLK by the buffer 13, and the internal clock CLK is supplied to the input circuit 14, the output circuit 15, the write / read circuit 16, and the like, and controls the input / output operation of the data.
[0008]
Since the internal clock CLK is generated by the buffer 13 using the external clock CK as a trigger, there is necessarily a skew between the external clock CK and the internal clock CLK.
[0009]
Since the internal clock CLK controls the internal operation of the memory 11, when data is exchanged between the memory 11 and another block (CPU 12 or the like), the external clock CK and the internal clock CLK It is necessary to set the timing in consideration of the skew between.
[0010]
However, as described above, the timing setting in consideration of the skew delays the data transfer rate.
[0011]
Therefore, recently, development of a technique for eliminating this skew has been promoted. Hereinafter, two examples of the technology at present will be described.
[0012]
The first is a technique using a PLL (phase lock loop). In this technique, the width of a skew is detected by a PLL, and this skew is made zero. In addition, since this technique applies feedback to the internal clock, it is effective when the external clock supplied to the memory always has a constant frequency and is not interrupted.
[0013]
The second is a technique for configuring a circuit that generates a corrected internal clock that matches an external clock based on a predetermined principle. This technology is very promising because it can immediately match the external clock and the internal clock even if the external clock frequency changes or the external clock is interrupted. Yes.
[0014]
The latter technique will be described in detail below.
[0015]
First, the principle of this technique will be described with reference to FIG.
[0016]
The skew width (delay amount) of the external clock CK and the internal clock CLK is D1, and the period of the external clock CK and the internal clock CLK is T.
[0017]
Here, the delayed imitation pulse FCL is generated when the time A elapses from the time when the first pulse of the internal clock CLK is generated (when it rises). In this case, the time from the time when the delayed imitation pulse FCL is generated to the time when the second pulse of the internal clock CLK is generated is Δ.
[0018]
Also, this time Δ is copied so that the delayed imitation pulse RCL is generated when the time (2 × Δ) has elapsed since the generation of the delayed imitation pulse FCL. Then, the time when the time A has elapsed from the time when the delayed imitation pulse RCL is generated coincides with the time when the third pulse of the internal clock CLK is generated.
[0019]
However, (A + W) <T. W is the width of the delayed mimic pulses FCL, RCL.
[0020]
Here, assuming that the time from the time when the delayed imitation pulse RCL is generated to the time when the third pulse of the external clock CK is generated is D2, if the delay imitation pulse RCL is delayed by the time D2, the external clock CK A corrected internal clock CK ′ matching the timing is obtained.
[0021]
That is, if a delay circuit for generating delay amounts A, (2 × Δ), D2 is formed and the internal clock CLK is delayed by time A + (2 × Δ) + D2, a corrected internal clock that matches the timing of the external clock CK is obtained. CK 'is obtained.
[0022]
As apparent from FIG. 50, since the relationship A = D1 + D2 exists, the delay amount D2 can be obtained from A and D1.
[0023]
Further, since it is assumed that the period T of the external clock CK and the internal clock CLK is not constant, the time Δ does not have a constant value. Therefore, the delay circuit that generates time (2 × Δ) must be configured to be able to generate time (2 × Δ) accurately according to the period T of the external clock CK and the internal clock CLK. .
[0024]
According to such a principle, the first pulse of the corrected internal clock can always coincide with the third pulse of the external clock CK regardless of the period T of the external clock CK and the internal clock CLK. Further, after the third pulse of the external clock CK, the timing of the external clock CK coincides with the timing of the corrected internal clock CLK. Therefore, even when the external clock CK is interrupted, this immediately Correspondingly, the external clock and the internal clock can be matched.
[0025]
Next, a circuit configuration for matching the timings of the external clock and the internal clock based on the above principle will be examined.
[0026]
FIG. 51 shows an example of the circuit configuration.
[0027]
The external clock CK is input to the input buffer 22 via the input terminal 21. The internal clock CLK is output from the input buffer 22. Here, since the input buffer 22 has the delay amount D1, a skew corresponding to the delay amount D1 is generated between the external clock CK and the internal clock CLK.
[0028]
The internal clock CLK is input to the forward delay array 24 via the delay circuit 23 having the delay amount A. The forward delay array 24 includes a plurality of delay circuits 25-1, 25-2 to 25-n having a delay amount d.
[0029]
The mirror control circuit 26 has a number of control elements 27-1, 27-2, to 27-n corresponding to the number of delay circuits 25-1, 25-2 to 25-n. The mirror control circuit 26 has a function of determining the delay amount Δf in the forward delay array 24 and making the delay amount Δb in the backward delay array 28 equal to the delay amount Δf.
[0030]
Similar to the forward delay array 24, the backward delay array 28 is composed of a plurality of delay circuits 29-1, 29-2, to 29-n having a delay amount d.
[0031]
The clock output from the backward delay array 28 passes through the delay circuit 30 having the delay amount D2, and becomes a corrected internal clock CK ′ having a timing that matches the timing of the external clock CK.
[0032]
In the circuit having the above configuration, the configuration of the forward delay array 24 and the configuration of the backward delay array 28 are the same, and the delay amount Δf of the forward pulse is copied as it is to obtain the delay amount Δb of the backward pulse. 2Δ (Δf = Δb = Δ ).
[0033]
However, the circuit having the above configuration has a drawback that it is difficult to completely match the forward pulse delay amount Δf and the reverse pulse delay amount Δb due to the forward pulse having a constant pulse width. .
[0034]
This drawback will be described.
[0035]
FIG. 52 shows the circuit state of FIG. 51 at time t in FIG. 50 (that is, when the delay amounts Δf and Δb are determined).
[0036]
Here, a state in which the forward pulse is input to the delay circuit of the forward delay array is an active state (indicated by hatching), and a state in which the forward pulse is not input to the delay circuit of the forward delay array is an inactive state. . In this case, for example, when a forward pulse is input to the delay circuit 25-k, the delay circuit 25-k is activated and the other delay circuits are deactivated.
[0037]
When a pulse of the internal clock CLK is generated after the forward pulse is input to the delay circuit 25-k, the delay circuit 29-k of the backward delay array is activated, and the delay circuit 29-k generates a backward pulse.
[0038]
That is, since the forward pulse and the pulse of the internal clock CLK are input to the kth control element 27-k from the head of the delay array, the control element 27-k activates the delay circuit 29-k of the backward delay array. Then, the backward pulse is generated from the delay circuit 29-k.
[0039]
However, in this case, the position from the head of the delay circuit 29-k to which the forward pulse is input and the position from the head of the delay circuit 29-k that generates the backward pulse are the same.
[0040]
Accordingly, the forward pulse front F1 for determining the delay amount Δf and the reverse pulse front F2 for determining the delay amount Δb inevitably have a delay amount equivalent to one stage of the delay circuit (for example, the pulse width W of the forward pulse). ) Will be different. That is, the circuit having the configuration of FIG. 51 has a disadvantage that the delay amount Δb is at most shorter than the delay amount Δf by the delay amount of one stage of the delay circuit.
[0041]
[Problems to be solved by the invention]
As described above, conventionally, in a technique for configuring a circuit that generates a corrected internal clock that matches an external clock based on a predetermined principle, a circuit that accurately copies a predetermined delay amount cannot be configured. Therefore, it is difficult to make the corrected internal clock completely coincide with the external clock.
[0042]
The present invention has been made to solve the above-described drawbacks, and an object of the present invention is to provide a predetermined delay amount in a technique for constructing a circuit that generates a corrected internal clock that matches an external clock based on a predetermined principle. A circuit that can be copied accurately is constructed, and the corrected internal clock is perfectly matched with the external clock.
[0043]
Another object of the present invention is to provide a circuit that generates a corrected internal clock having a fixed phase relationship with respect to the external clock, that is, a phase delayed by a predetermined amount with respect to the external clock, based on a predetermined principle. It is to be.
[0044]
[Means for Solving the Problems]
  The memory system of the present invention includes:A memory that outputs data based on an internal clock generated from an external clock, a dummy memory having an input capacity of the external clock equal to the memory, the external clock, and a return clock from the dummy memory A controller for determining a timing of receiving data output from the memory, and a wiring length of the external clock from the controller to the dummy memory is equal to a wiring length of the external clock from the controller to the memory The wiring length of the return clock from the dummy memory to the controller is equal to the data bus length from the memory to the controller.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a clock control circuit of the present invention will be described in detail with reference to the drawings.
[0046]
FIG. 1 shows an example of a synchronous control system including a memory block having a clock control circuit of the present invention.
[0047]
For example, an external clock CK generated by the CPU 12 is input to the memory (clock synchronous DRAM such as a synchronous DRAM) 11. The external clock CK is converted into the internal clock CLK by the buffer 13. The internal clock CLK is supplied to the write / read circuit 16 to control the data write / read operation.
[0048]
Since the internal clock CLK is generated by the buffer 13 using the external clock CK as a trigger, there is necessarily a skew between the external clock CK and the internal clock CLK.
[0049]
Based on the internal clock CLK, the clock control circuit 31 generates a corrected internal clock CK ′ that matches the timing of the external clock. The corrected internal clock CK ′ is supplied to the input circuit 14 and the output circuit 15, and controls the input / output operation of the data.
[0050]
FIG. 2 shows a configuration of the clock control circuit 31 in the memory 11 of FIG.
[0051]
The external clock CK is given to the input terminal 30 of the memory. The external clock CK is input to the input buffer 13 having a delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to a delay circuit 32 having a delay amount A, and the delay circuit 32 outputs a forward pulse FCL1 (delay imitation pulse CL).
[0052]
The internal clock CLK and the inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 are input to n delay units 33-1, 33-2,... 33-n, respectively.
[0053]
The n delay units 33-1, 33-2,... 33-n are connected in series with each other. A forward pulse FCL1 is input to the first-stage delay unit 33-1 and a backward pulse RCL1 is output from the first-stage delay unit 33-1.
[0054]
The backward pulse RCL1 becomes the corrected internal clock CK ′ by passing through the delay circuit 34 having the delay amount D2.
[0055]
FIG. 3 shows the configuration of the delay unit of FIG. 2 in detail.
[0056]
The delay unit 33-i includes three parts: a forward pulse delay circuit, a state holding circuit, and a reverse pulse delay circuit.
[0057]
The forward pulse delay circuit is composed of three inverters 41-43. The inverters 41 and 42 are connected in series, and the inverter 41 receives the output signal FCLi of the preceding delay unit, and the inverter 42 outputs the output signal FCLi + 1 to the subsequent delay unit. The operation of the inverter (clocked inverter) 41 is controlled by the control pulse / P. For example, when the control pulse / P is “1”, the inverter 41 is activated.
[0058]
The output terminal of the inverter 43 is connected to the input terminal of the inverter 42, and a potential of “0” (for example, ground potential) is always applied to the input terminal of the inverter 43. The operation of the inverter (clocked inverter) 43 is controlled by the control pulse P. For example, when the control pulse P is “1”, the inverter 43 is activated.
[0059]
The reverse pulse delay circuit is composed of three inverters 44-46. The inverters 44 and 45 are connected in series, and the inverter 44 receives the output signal RCLi + 1 of the subsequent delay unit or the internal clock CLK, and the inverter 45 receives the output signal RCLi to the previous delay unit. Output. The operation of the inverter (clocked inverter) 44 is controlled by the control pulse Q. For example, the inverter 44 is activated only when the control pulse Q is “1”.
[0060]
The output terminal of the inverter 46 is connected to the input terminal of the inverter 45, and the internal clock CLK is always input to the input terminal of the inverter 46. The operation of the inverter (clocked inverter) 46 is controlled by the control pulse / Q. For example, when the control pulse / Q is “1”, the inverter 46 is activated.
[0061]
The state holding circuit includes a state holding unit 47 and NAND circuits 48 and 49. The NAND circuit 48 receives the output signal FCLi of the preceding delay unit and the inverted internal clock / CLK, and the NAND circuit 49 receives the output signal of the inverter 45 and the internal clock CLK.
[0062]
The output signal of the NAND circuit 48 becomes the set input / S of the state holding unit 47, and the output signal of the NAND circuit 49 becomes the reset input / R of the state holding unit 47. Therefore, when the output signal (set input) / S of the NAND circuit 48 becomes “0”, the state holding unit 47 is set, and the output signal (reset input) / R of the NAND circuit 49 becomes “0”. When this happens, the state holding unit 47 enters a reset state.
[0063]
The state holding unit 47 is also configured to output control pulses Q and / Q. The control pulse Q is “1” when the state holding unit 47 is in the set state, and the control pulse / Q is “1” when the state holding unit 47 is in the reset state.
[0064]
FIG. 4 shows an example of the configuration of the state holding unit of FIG.
[0065]
The P-channel MOS transistor 51 and the N-channel MOS transistors 53 and 54 are connected in series with each other, and a high potential VDD and a low potential VSS are applied to both ends thereof.
[0066]
Similarly, the P-channel MOS transistor 52 and the N-channel MOS transistors 55 and 56 are connected in series with each other, and a high potential VDD and a low potential VSS are applied to both ends thereof.
[0067]
The set input / S is input to the gates of the MOS transistors 51 and 54, and the reset input / R is input to the gates of the MOS transistors 52 and 56.
[0068]
The gate of the MOS transistor 53 is connected to the drain of the MOS transistor 52, and the gate of the MOS transistor 55 is connected to the drain of the MOS transistor 51.
[0069]
The control pulse Q is output from the drain of the MOS transistor 51, and the control pulse / Q is output from the drain of the MOS transistor 52.
[0070]
FIG. 5 shows an example of the configuration of the control pulse P, / P generation circuit.
[0071]
The internal clock CLK is input to one input terminal of the NOR circuit 58 via the delay circuit 57 having the delay amount A ′, and the inverted internal clock / CLK is input to the other input terminal of the NOR circuit 58. The NOR circuit 58 outputs a control pulse P. Further, the control pulse P becomes the control pulse / P through the inverter 59.
[0072]
The pulse widths of the control pulses P and / P are determined by the delay amount A ′ of the delay circuit 57. However, the delay amount A ′ is set smaller than the delay amount A of the delay circuit 32 that outputs the delay imitation pulse. This is because it is necessary to initialize the forward delay circuits of all the delay units before the forward pulse is input to the first delay unit.
[0073]
Next, the principle of the present invention will be confirmed with reference to FIG.
[0074]
The skew width (delay amount) of the external clock CK and the internal clock CLK is D1, and the period of the external clock CK and the internal clock CLK is T.
[0075]
The delayed imitation pulse FCL1 is generated when the time A elapses from the time when the first pulse of the internal clock CLK is generated (when it rises). In this case, the time from the time when the delay imitation pulse FCL1 is generated to the time when the second pulse of the internal clock CLK is generated is Δf.
[0076]
Further, the time Δf is copied to make Δb, and when the time 2 × Δ (where Δf = Δb = Δ) elapses from the time when the delay imitation pulse FCL1 is generated, the delay imitation pulse RCL1 is generated. To. Then, the time when the time A elapses from the time when the delayed imitation pulse RCL1 is generated coincides with the time when the third pulse of the internal clock CLK is generated. However, (A + W) <T. W is the width of the delayed mimic pulses FCL, RCL.
[0077]
If the time from the time when the delayed imitation pulse RCL1 is generated to the time when the third pulse of the external clock CK is generated is D2, if the delay imitation pulse RCL1 is delayed by the time D2, it matches the timing of the external clock CK. The corrected internal clock CK ′ is obtained.
[0078]
That is, if a delay circuit for generating delay amounts A, (2 × Δ), D2 is formed and the internal clock CLK is delayed by time A + (2 × Δ) + D2, a corrected internal clock that matches the timing of the external clock CK is obtained. CK 'is obtained.
[0079]
Since the relationship A = D1 + D2 exists, the delay amount D2 can be obtained from A and D1. The control pulse P is for initializing the forward delay circuits of all the delay units before the forward pulse is input to the first delay unit.
[0080]
Next, the operation of the clock control circuit of FIGS. 2 to 5 will be described.
[0081]
1. State at timing a of the timing chart of FIG.
As shown in FIG. 8, the internal clock CLK becomes “1” (rises). Accordingly, the output signals of the control pulse generation circuit 60 are P = “1” and / P = “0”, and control pulses P and / P having a pulse width determined by the delay amount A ′ are generated. Input to the units 33-1, 33-2, to 33-n.
[0082]
In each of the delay units 33-1 and 33-2 to 33-n, P = “1” and / P = “0”, so that the inverter 43 is activated and the inverter 41 is inactivated. It becomes a state. Accordingly, the input / output signals FCL1 to FCLn of the forward pulse delay circuits of all the delay units 33-1, 33-2, to 33-n are all “0”, and the line for transmitting the forward pulse is initialized.
[0083]
Thereafter, in each of the delay units 33-1 and 33-2 to 33-n, when P = “0” and / P = “1”, the inverter 41 is activated and the inverter 43 is inactive. Become active. That is, the forward pulse delay circuits of the delay units 33-1, 33-2, to 33-n are electrically connected to each other, and the input terminal of the forward pulse delay circuit of the delay unit 33-1 is connected to the delay circuit 32. Electrically connected and ready for forward pulse transmission.
[0084]
Note that the pulse widths of the control pulses P and / P (period in which P is “1” and / P is “0”) must be shorter than the period determined by the delay amount A of the delay circuit 32. is there. Before the forward pulse (delay mimic pulse) FCL1 is input to the delay unit 33-1, it is necessary to initialize the forward pulse transmission lines of all the delay units 33-1, 33-2 to 33-n. Because there is.
[0085]
2. State at timing b of the timing chart of FIG.
As shown in FIG. 9, the internal clock CLK becomes “0” and the inverted internal clock / CLK becomes “1”. Since the internal clock CLK and the inverted internal clock / CLK are common to all the delay units 33-1, 33-2, to 33-n, all the delay units 33-1, 33-2, to 33- One input of the n NAND circuit 48 is “1”.
[0086]
On the other hand, the state holding unit 47 of each of the delay units 33-1, 33-2, to 33-n is in the reset state R, and the control pulse output from the state holding unit 47 is Q = “0”, / Q = “1”.
[0087]
Accordingly, the inverter 46 of each delay unit 33-1, 33-2,..., 33-n is activated, the inverter 44 is deactivated, and all the delay units 33-1, 33-2,. The input / output signals RCL1 to RCLn of the backward pulse delay circuit 33-n are all “0”.
[0088]
3. State at time point c in the timing chart of FIG.
As shown in FIG. 10, a forward pulse (delay mimic pulse) FCL1 is output from the delay circuit (delay amount A) 32 and input to the delay unit 33-1. Note that the sum of the pulse width of the forward pulse (period of “1”) and the period determined by the delay amount A needs to be set to be shorter than the cycle T of the internal clock CLK.
[0089]
When the forward pulse FCL1 (= “1”) is input to the delay unit 33-1, the other input of the NAND circuit 48 of the delay unit 33-1 becomes “1”, and the output (set input / S ) Becomes “0”. Accordingly, the state of the state holding unit 47 changes to the set state S.
[0090]
In the delay unit 33-1 in which the state holding unit 47 is in the set state S, the control pulses output from the state holding unit 47 are Q = “1” and / Q = “0”. Becomes active and the inverter 46 becomes inactive.
[0091]
4). State at time d and e of the timing chart of FIG.
As shown in FIG. 11, the forward pulse advances while sequentially passing through the delay units 33-1, 33-2 to 33 -n.
[0092]
In the delay unit 33-1 in which the forward pulse has passed, the other input of the NAND circuit 48 becomes “0” again, and the output (set input / S) of the NAND circuit 48 becomes “1”. The state is maintained in the set state S.
[0093]
Similarly, when the forward pulse is input to the delay unit 33-2, the state holding unit 47 of the delay unit 33-2 changes to the set state S. Even if the forward pulse passes through the delay unit 33-2, the state holding unit 47 of the delay unit 33-2 maintains the set state S.
[0094]
When the internal clock CLK becomes “1” again and the inverted internal clock / CLK becomes “0”, each of the delay units 33-1 and 33-2 to 33-n includes the internal clock CLK and the inverted internal clock / CLK. CLK is input.
[0095]
Therefore, one input of the NAND circuit 48 of all the delay units 33-1, 33-2,..., 33-n is “0”, and one input of the NAND circuit 49 is “1”.
[0096]
In the delay units 33-1 and 33-2 in which the state holding unit 47 is in the set state S, since Q = “1” and the inverter 44 is in the active state, the output signal RCL1, RCL2 maintains the state of “0”, but in the delay units 33-3 to 33-n in which the state holding unit 47 is in the reset state R, / Q = “1” and the inverter 46 is in the active state. Therefore, the output signals RCL3 to RCLn of the backward pulse delay circuit are “1”.
[0097]
Thereby, the front edge F2 of the backward pulse is formed.
[0098]
Here, the front edge F2 of the backward pulse indicates that the delay unit 33- of the first stage among the delay units 33-3 to 33-n whose state holding unit is in the reset state R when the internal clock CLK becomes "1". It is formed by a delay unit 33-3 located on one side.
[0099]
At this time, since the front edge F1 of the forward pulse is considered to be located immediately before the delay unit 33-3, the front edge F1 of the forward pulse and the front edge F2 of the backward pulse coincide.
[0100]
Accordingly, the time Δf from when the forward pulse (delayed imitation pulse) FCL1 is generated until the internal clock CLK pulse is generated, and the backward movement after the internal clock CLK pulse is generated (after the backward pulse is generated). The time Δb until the pulse RCL1 is output and input to the delay circuit 34 becomes equal.
[0101]
Thereafter, as shown in FIG. 12, the output signal of the control pulse generation circuit 60 becomes P = “1”, / P = “0”, and the control pulse P having a pulse width determined by the delay amount A ′, / P is generated and input to each delay unit 33-1, 33-2, to 33-n.
[0102]
In each of the delay units 33-1 and 33-2 to 33-n, P = “1” and / P = “0”, so that the inverter 43 is activated and the inverter 41 is inactivated. It becomes a state. Accordingly, the input / output signals FCL1 to FCLn of the forward pulse delay circuits of all the delay units 33-1 and 33-2 to 33-n are all “0”, the forward pulse disappears, and the forward pulse is transmitted. Is initialized.
[0103]
On the other hand, when the front of the backward pulse (= “1”) is input to the delay unit 33-1, the two inputs of the NAND circuit 49 are both “1” in the delay unit 33-2. Output (reset input / R) becomes “0”, and the state holding unit 47 changes to the reset state R (initialized).
[0104]
Initialization (setting to the reset state R) of the state holding unit 47 of each delay unit is performed only during a period in which the internal clock CLK is “1”. That is, when the backward clock (= “1”) is input when the internal clock CLK is “1”, the two inputs of the NAND circuit 49 both become “1”.
[0105]
Since the initialization of the state holding unit 47 of each delay unit is performed only during the period when the internal clock CLK is “1”, the state holding units 47 of all delay units can be initialized, that is, set to the reset state R. There are cases where this is not possible, but there is no particular problem. This is because it is clear that the next forward pulse passes through the delay unit 33-1 which is not initialized.
[0106]
5). State at time f of timing chart in FIG.
As shown in FIG. 13, the internal clock CLK becomes “0” and the inverted internal clock / CLK becomes “1”. The internal clock CLK and the inverted internal clock / CLK are input to all the delay units 33-1, 33-2, to 33-n.
[0107]
In each of the delay units 33-1 and 33-2 to 33-n, P = “0” and / P = “1”, so that the inverter 41 is activated and the inverter 43 is inactive. Become active. That is, the forward pulse delay circuits of the delay units 33-1, 33-2, to 33-n are electrically connected to each other, and the input terminal of the forward pulse delay circuit of the delay unit 33-1 is connected to the delay circuit 32. Electrically connected and ready for forward pulse transmission.
[0108]
On the other hand, in the delay units 33-2 to 33-n in which the state holding unit 47 is in the reset state R, / Q = "1" and the inverter 46 is in the active state. Therefore, when the internal clock CLK becomes “0”, the output signals RCL2 to RCLn of the delay units 33-2 to 33-n in the state holding unit 47 in the reset state R become “0”, and the back edge of the backward pulse is formed. Is done.
[0109]
Therefore, the pulse width of the backward pulse is the same as or shorter than the period corresponding to the delay amount for one stage of the delay unit (delay amount for the two inverter stages).
[0110]
If the pulse width of the backward pulse is desired to be longer than the delay amount for one stage of the delay unit, as shown in FIG. 17, the other input of the NAND circuit 49 of the delay circuit 33-n is connected to the preceding delay circuit. The output RCLn-1 may be 33- (n-1). In this case, the maximum pulse width of the backward pulse is a period corresponding to a delay amount corresponding to two delay units (a delay amount corresponding to four inverter stages).
[0111]
In the delay unit 33-1 in which the state holding unit 47 is in the set state S, Q = “1” and the inverter 44 is in the active state. Therefore, the preparation for guiding the backward pulse to the delay circuit 34 via the delay unit 33-1 is completed.
[0112]
6). State at timing g of the timing chart in FIG.
As shown in FIG. 14, a forward pulse (delay mimic pulse) FCL1 is output from the delay circuit (delay amount A) 32 and input to the delay unit 33-1. When the forward pulse FCL1 (= “1”) is input to the delay unit 33-1, the other input of the NAND circuit 48 of the delay unit 33-1 becomes “1”, and the output (set input / S ) Becomes “0”.
[0113]
Therefore, when the state holding unit 47 of the delay unit 33-1 is in the set state, the state holding unit 47 maintains the set state S, and when the state holding unit 47 is in the reset state R, the state holding unit 47 is , Change to the set state S.
[0114]
In the delay unit 33-1 in which the state holding unit 47 is in the set state S, the control pulses output from the state holding unit 47 are Q = “1” and / Q = “0”. Becomes active and the inverter 46 becomes inactive.
[0115]
On the other hand, the backward pulse is input to the first-stage delay unit 33-1, receives the delay of two inverter stages, and is output from the first-stage delay unit 33-1.
[0116]
7). State at time point h in the timing chart of FIG.
As shown in FIG. 15, the forward pulse advances while sequentially passing through the delay units 33-1, 33-2 to 33 -n.
[0117]
In the delay unit 33-1 in which the forward pulse has passed, the other input of the NAND circuit 48 becomes “0” again, and the output (set input / S) of the NAND circuit 48 becomes “1”. The state is maintained in the set state S.
[0118]
Similarly, when the forward pulse is input to the delay unit 33-2, the state holding unit 47 of the delay unit 33-2 changes to the set state S. Even if the forward pulse passes through the delay unit 33-2, the state holding unit 47 of the delay unit 33-2 maintains the set state S.
[0119]
On the other hand, the backward pulse is input to the delay circuit 34. The delay circuit 34 delays the backward pulse by the delay amount D2, and generates a pulse of the corrected internal clock CK ′. The timing of the pulse of the corrected internal clock CK ′ coincides with the timing of the pulse of the external clock CK.
[0120]
8). State at timing i of the timing chart of FIG.
As shown in FIG. 16, when the internal clock CLK becomes “1” again and the inverted internal clock / CLK becomes “0”, each delay unit 33-1, 33-2,. Clock CLK and inverted internal clock / CLK are input.
[0121]
Therefore, one input of the NAND circuit 48 of all the delay units 33-1, 33-2,..., 33-n is “0”, and one input of the NAND circuit 49 is “1”.
[0122]
In the delay units 33-1 and 33-2 in which the state holding unit 47 is in the set state S, since Q = “1” and the inverter 44 is in the active state, the output signal RCL1, RCL2 maintains the state of “0”, but in the delay units 33-3 to 33-n in which the state holding unit 47 is in the reset state R, / Q = “1” and the inverter 46 is in the active state. Therefore, the output signals RCL3 to RCLn of the backward pulse delay circuit are “1”.
[0123]
As a result, a reverse pulse front F1 is formed.
[0124]
Thereafter, the operations of FIGS. 12 to 16 are repeated.
[0125]
According to the clock control circuit having the above configuration, each delay unit has a state holding unit, so that the time Δf from when the delayed imitation pulse (forward pulse) FCL1 is generated to when the internal clock CLK is generated can be accurately determined. By copying, Δb is formed, and the backward pulse RCL1 can be input to the delay circuit 34 having the delay amount D2 after time Δb (= Δf) after the pulse of the internal clock CLK is generated.
[0126]
Therefore, it becomes possible to generate the corrected internal clock CK ′ that is accurately synchronized with the external clock CK, and it is possible to achieve data transfer using a high-speed clock. The present invention is effective for a memory such as a synchronous DRAM in which the internal clock may be temporarily interrupted and data is transmitted and received in synchronization with a high-speed clock whose frequency changes.
[0127]
FIG. 18 shows a modification of the clock control circuit of FIG.
[0128]
This clock control circuit is different from the circuit of FIG. 2 in that a predetermined function is added to the delay circuit 34, and the other configuration is the same as that of the circuit of FIG.
[0129]
That is, in this embodiment, when the cycle T of the external clock CK or the internal clock CLK is longer than a predetermined value, the process of matching the timing of the internal clock CLK with the timing of the external clock CK is not performed, and The output circuit is controlled by an internal clock CLK having a fixed skew.
[0130]
This is because when the frequency of the external clock CK is relatively low (the period is long), the skew itself is not a problem. This is also because the number of delay units constituting the clock control circuit is not so large due to the relationship with the occupied area on the memory chip.
[0131]
The configuration of the circuit according to this embodiment will be briefly described below.
[0132]
The external clock CK is given to the input terminal 30 of the memory. The external clock CK is input to the input buffer 13 having a delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to a delay circuit 32 having a delay amount A, and the delay circuit 32 outputs a forward pulse FCL1 (delay imitation pulse CL).
[0133]
The internal clock CLK and the inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 are input to n delay units 33-1, 33-2,... 33-n, respectively.
[0134]
The n delay units 33-1, 33-2,... 33-n are connected in series with each other. A forward pulse FCL1 is input to the first-stage delay unit 33-1 and a backward pulse RCL1 is output from the first-stage delay unit 33-1.
[0135]
When the period T of the external clock CK is less than a predetermined value (high-speed clock), the backward pulse RCL1 becomes the corrected internal clock CK ′ through the delay circuit 34 having the delay amount D2. The timing of the corrected internal clock CK ′ coincides with the timing of the external clock CK.
[0136]
When the period T of the external clock CK is equal to or greater than a predetermined value, the backward pulse RCL1 is input to the delay circuit 34 having the delay amount D2, but is not output from the delay circuit 34. Instead, the internal clock CLK is output from the delay circuit 34. In this case, of course, the internal clock CLK has a fixed skew with respect to the external clock CK, but this skew is of an amount that does not cause much problem with respect to the period of the external clock CK. Yes.
[0137]
Based on the output LST of the forward pulse delay circuit of the last delay unit 33-n and the output RCL1 of the reverse pulse delay circuit of the first delay unit 33-1, the control pulse generation circuit 61 controls the control pulses L, / L. Is output. The control pulses L and / L determine whether to output the corrected internal clock CK ′ or the internal clock CLK.
[0138]
FIG. 19 shows the configuration of the delay circuit 34 of FIG. 18 in detail.
[0139]
The output RCL1 of the delay unit 33-1 is input to one input terminal of the NAND circuit 64 via the delay circuit 62 and the inverter 63 and directly input to the other input terminal of the NAND circuit 64. Yes. The output signal of the NAND circuit 64 passes through the three inverters 65 to 67 and becomes the corrected internal clock CK ′.
[0140]
The inverter 66 is a clocked inverter that is activated when the control clock / L is "1". That is, when the control clock / L is “1”, the backward pulse is delayed by a fixed time to generate the corrected internal clock CK ′, and when the control clock / L is “0”, the backward pulse is cut off.
[0141]
The internal clock CLK is input to the inverter 67 of the delay circuit 34 via the inverter 68. The inverter 68 is a clocked inverter that is activated when the control clock L is “1”. That is, when the control clock L is “1”, the internal clock CLK is guided to the inverter 67, and when the control clock L is “0”, the internal clock CLK is cut off.
[0142]
FIG. 20 shows a configuration of the control pulse generation circuit 61 of FIG.
[0143]
The output LST of the forward pulse delay circuit of the final delay unit 33-n is input to one input terminal of the NOR circuit 69, and the output of the NOR circuit 72 is input to the other input terminal. The output of the NOR circuit 69 is input to one input terminal of the NOR circuit 72, and the output of the NOR circuit 71 is input to the other input terminal.
[0144]
The NOR circuit 71 is obtained by inverting the output LST of the forward pulse delay circuit of the delay unit 33-n at the final stage and the output RCL1 of the reverse pulse delay circuit of the first delay unit 33-1 by the inverter 70, respectively. Have been entered.
[0145]
Further, the output of the NOR circuit 69 and the output obtained by delaying the output by the delay circuit 74 by the delay amount D3 are input to the NAND circuit 73, respectively. The output of the NAND circuit 73 is the control clock L, and the control clock L is obtained by inverting the control clock L with the inverter 75.
[0146]
The NAND circuit 73 and the delay circuit 74 do not delay the rise of the control clock L with respect to the output of the NOR circuit 69, and delay only the fall of the control clock L by the delay amount D3. It is for surely extinguishing and initializing.
[0147]
Next, the principle of the clock control circuit of FIGS. 18 to 20 will be briefly described with reference to FIG.
[0148]
FIG. 21 shows that the period (cycle time) of the external clock CK becomes relatively long, and the maximum delay amount maxΔ by all delay units is the time from the time when the delayed imitation pulse is generated to the time when the pulse of the internal clock CLK is generated. The timing chart in the case where it becomes shorter than Δf is shown.
[0149]
The skew width (delay amount) between the external clock CK and the internal clock CLK is D1, and the cycle of the external clock CK is T.
[0150]
The delayed imitation pulse FCL1 is generated when the time A elapses from the time when the first pulse of the internal clock CLK is generated (when it rises). In this case, the time from the time when the delay imitation pulse FCL1 is generated to the time when the second pulse of the internal clock CLK is generated is Δf.
[0151]
However, the maximum delay amount that can be formed by all delay units is maxΔ (<Δf). That is, since the maximum delay amount that can be copied by the clock control circuit of the present invention is maxΔ, the delay imitation pulse RCL1 is generated when the time maxΔ has elapsed from the time when the second pulse of the internal clock CLK is generated. As a result, the delay amount Δf cannot be copied accurately.
[0152]
Therefore, even if the corrected internal clock CK ′ is generated when the time D2 has elapsed from the time when the delayed imitation pulse RCL1 is generated, the timing of the corrected internal clock CK ′ is shifted from the timing of the external clock CK. In addition, this shift may be larger than the skew that originally existed, which rather degrades the performance of the memory.
[0153]
This embodiment is conceived to avoid such a phenomenon. In the embodiment of FIG. 2, when A is the time from the generation of the internal clock CLK pulse until the delay imitation pulse is generated, and the maximum delay amount by all delay units is maxΔ, A + maxΔ ≦ T However, in this embodiment, such a condition is not required.
[0154]
Next, the operation of the clock control circuit of FIGS. 18 to 20 will be described with reference to the timing chart of FIG.
[0155]
Since the operation when A + maxΔ ≦ T is the same as the timing chart shown in FIG. 7, only the operation when A + maxΔ> T will be described below.
[0156]
When the internal clock CLK becomes “1”, P = “1”, / P = “0”, and the input / output signal FCL1 of the forward pulse delay circuit of all the delay units 33-1, 33-2, to 33-n. ... FCLn are all "0", and the line for transmitting the forward pulse is initialized.
[0157]
Thereafter, when P = “0” and / P = “1”, the forward pulse delay circuits of the delay units 33-1, 33-2, to 33-n are electrically connected to each other, and the delay unit The input terminal of the forward pulse delay circuit 33-1 is electrically connected to the delay circuit 32, and preparation for transmission of the forward pulse is completed.
[0158]
After the internal clock CLK becomes “0” and the inverted internal clock / CLK becomes “1”, the forward pulse (delay imitation pulse) FCL1 is output from the delay circuit (delay amount A) 32, and is supplied to the delay unit 33-1. Entered.
[0159]
When the forward pulse FCL1 (= “1”) is input to the delay unit 33-1, the state of the state holding unit 47 of the delay unit 33-1 becomes the set state S. Further, the forward pulse advances while sequentially passing through the delay units 33-1, 33-2, to 33-n. In the delay unit where the forward pulse has passed, the state of the state holding unit 47 is maintained in the set state S.
[0160]
Thereafter, the forward pulse is output as an output pulse LST (= “1”) from the delay unit 33-n via all the delay units 33-1, 33-2, to 33-n.
[0161]
The output pulse LST is input to the control pulse generation circuit 61. As a result, the control pulse generation circuit 61 generates a path switching signal with L = “1” and / L = “0”. That is, when the output pulse LST is output, L = “1”, / L = “0”, the delay circuit 34 is deactivated, and the delay circuit 34 generates a corrected internal signal that matches the timing of the internal clock CLK. The clock CK ′ is output.
[0162]
Further, when the time maxΔ elapses after the internal clock CLK becomes “1” again, the backward pulse RCL1 is output from the delay unit 33-1. When the reverse pulse RCL1 is input to the control pulse generation circuit 61, the control pulse generation circuit 61 outputs L = "" after the timing when the reverse pulse RCL1 is output from the delay circuit 34, that is, after the reverse pulse RCL1 disappears. A path switching signal of “0”, / L = “1” is generated.
[0163]
That is, the delay circuit 34 is initialized (activated), and the delay circuit 34 changes to a state in which the output signal RCL1 of the delay unit 33-1 can be output.
[0164]
The delay circuit 62, the inverter 63 and the NAND circuit 64 determine the pulse width of the backward pulse output from the delay unit 33-1. That is, when the internal clock CLK is used for input / output control of the memory, after the backward pulse disappears in the delay circuit 34, L = “0”, / L = “1”, and the delay circuit 34 is initialized (activated). ) To be configured.
[0165]
However, the delay amounts of the delay circuits 34, 62, and 74 are set to have a relationship of D3> D2 + D2 ′.
[0166]
According to the clock control circuit having the above configuration, it is possible to generate the corrected internal clock CK ′ that is accurately synchronized with the external clock CK, and it is possible to achieve data transfer using a high-speed clock.
[0167]
In the present embodiment, it is possible to determine whether to use the internal clock CK as it is or to use the corrected internal clock CK ′ synchronized with the external clock CK according to the frequency of the external clock CK.
[0168]
That is, when data is transferred in synchronization with a high-speed clock in which the skew between the external clock CK and the internal clock CLK becomes a problem, the corrected internal clock CK ′ synchronized with the external clock CK is used. When data is exchanged in synchronization with a clock that does not cause a problem with the skew, the internal clock CK is used as usual.
[0169]
Whether to use an internal clock or a corrected internal clock is determined by the number of delay units.
[0170]
Therefore, when the period (cycle time) of the external clock CK is long, a situation in which the difference between the external clock CK and the corrected internal clock CK ′ does not occur is not caused.
[0171]
FIG. 23 shows a layout when the clock control circuit of the present invention is arranged on a chip.
[0172]
When the clock control circuit of the present invention is actually incorporated into a system as an IC, it is necessary to consider a delay (wiring delay) caused by wiring capacitance.
[0173]
Therefore, first, an array of delay units (hereinafter referred to as STBD, Synchronous Traced Backward Delays) 80 has a distance (or wiring delay amount) from the input buffer 13 and a distance (or wiring delay amount) to the output buffer (delay circuit) 34. ) In the same position.
[0174]
Next, the input buffer 13 and the STBD 80 are connected by a wiring having a wiring length L. Here, the actual skew D1 is the sum of the delay amount due to the input buffer 13 and the delay amount due to the wiring having the wiring length L.
[0175]
Next, the delay circuit 32 having the delay amount A will be considered. The delay amount A is represented by D1 + D2 as described above (see, for example, FIG. 6). The actual delay amount D2 of the delay circuit (output buffer) 34 is the sum of the delay amount due to the output buffer 34 and the delay amount due to the wiring having the wiring length L.
[0176]
Accordingly, the delay circuit having the delay amount A has the same pattern 82 as the pattern 82 that forms the delay amount D2 and the pattern 82 that is reversed right and left with respect to the pattern 81 that forms the skew D1. 84.
[0177]
By adopting such a layout, the delay amounts A, D1, and D2 can be determined in consideration of the wiring delay. Therefore, the corrected internal clock CK ′ can be more accurately synchronized with the external clock CK. It becomes possible.
[0178]
As described above, the clock control circuit of the present invention has the following effects.
[0179]
Since each delay unit has a state holding unit, the time Δf from the generation of the delayed imitation pulse (forward pulse) FCL1 to the generation of the internal clock CLK pulse is accurately copied to form Δb, The backward pulse RCL1 can be input to the delay circuit having the delay amount D2 after time Δb (= Δf) from the generation of the pulse of the internal clock CLK.
[0180]
This state is schematically shown in FIGS.
[0181]
That is, in the initial state, as shown in FIG. 24, the forward pulse delay circuit and the backward pulse delay circuit of the delay units 33-1 to 33-n are all in the state of outputting “0”.
[0182]
Further, as shown in FIG. 25, after the forward pulse is input to the delay unit 33-4 and the state holding unit of the delay unit 33-4 is set to the set state S, the state is held when the internal clock CLK pulse is generated. The delay units 33-5 to 33-n whose units are in the reset state R output “1”.
[0183]
That is, the forward pulse front F1 and the reverse pulse front F2 coincide, so that the delay amount Δf and the delay amount Δb are the same.
[0184]
Thereafter, as shown in FIGS. 26 and 27, the delay unit 33-4 is initialized to the reset state R, and a backward pulse is formed. The backward pulse passes through the delay units 33-3 and 33-2. And output from the delay unit 33-1.
[0185]
Such an operation makes it possible to generate a corrected internal clock CK ′ that is accurately synchronized with the external clock CK, and achieve data transfer using a high-speed clock.
[0186]
Whether the internal clock CK is used as it is or the corrected internal clock CK ′ synchronized with the external clock CK is used according to the frequency of the external clock CK by monitoring the signal output from the final stage of the delay unit. Can be determined.
[0187]
That is, when data is transferred in synchronization with a high-speed clock in which the skew between the external clock CK and the internal clock CLK becomes a problem, the corrected internal clock CK ′ synchronized with the external clock CK is used. When data is exchanged in synchronization with a clock that does not cause a problem with the skew, the internal clock CK is used as usual.
[0188]
Whether to use an internal clock or a corrected internal clock is determined by the number of delay units.
[0189]
Therefore, when the period (cycle time) of the external clock CK is long, a situation in which the difference between the external clock CK and the corrected internal clock CK ′ does not occur is not caused.
[0190]
Further, paying attention to the fact that the delay amount A is represented by (D1 + D2) and considering the wiring delay, the pattern of the delay amount A is the same as the pattern forming the delay amounts D1 and D2. -Is formed.
[0191]
Therefore, a system that accurately synchronizes the corrected internal clock CK ′ with the external clock CK can be configured in the memory chip with a simplified layout.
[0192]
The present invention is effective for a memory such as a synchronous DRAM in which the internal clock may be temporarily interrupted and data is exchanged in synchronization with a high-speed clock whose frequency changes.
[0193]
FIG. 28 shows the clock control circuit of FIG. 2 in a simplified manner.
[0194]
D1 is a delay circuit having a delay amount D1, D2 is a delay circuit having a delay amount D2, A is a delay circuit having a delay amount D1 + D2, and STBD (Synchronous Traced Backward Delay) is an array of delay units. The STBD is composed of an FD (Forward Delay) and a BD (Backward Delay).
[0195]
According to the clock control circuit having such a configuration, as described above, the phase of the external clock CK and the phase of the internal clock CK ′ completely match (no skew). Therefore, the clock control circuit having the above configuration is effective when outputting data when the external clock CK rises (at the time of transition from “L” to “H”).
[0196]
On the other hand, in recent years, when the cycle of the external clock CK is T, in addition to the internal clock CK ′ without skew, the internal clock CKD whose phase is delayed by (k / j) × T with respect to the external clock CK. It is required to be generated accurately (k and j are relatively prime natural numbers and j> k).
[0197]
For example, when data is output when the external clock CK rises and falls, the internal clock CK ′ having the same phase as the external clock CK and the phase T / It is necessary to generate the internal clock CKD delayed by 2 (= π).
[0198]
Further, in such a case, if the phase of the internal clock CKD is not exactly delayed by T / 2 (= π) with respect to the phase of the external clock, the data window (data is displayed at the time of data output). There is a possibility that erroneous data will be output.
[0199]
Therefore, hereinafter, a clock control circuit capable of accurately generating the internal clock CKD whose phase is delayed by (k / j) × T with respect to the external clock CK will be described.
[0200]
FIG. 29 shows a first example of the configuration of the clock control circuit of the present invention.
[0201]
This clock control circuit generates an internal clock CKD whose phase is delayed by T / 2 (= π) with respect to the external clock CK, together with the internal clock CK ′ whose phase is matched with the external clock CK (T is External clock period).
[0202]
The external clock CK is input to the input buffer 13 having a delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to a delay circuit 32 having a delay amount A, and the delay circuit 32 outputs a delay imitation pulse CL (forward pulse FCL1).
[0203]
The delayed imitation pulse CL is input to an FD (Forward Delay) of an STBD (Synchronous Traced Backward Delay). After the delay imitation pulse CL advances by the delay amount Δ in the FD, backward pulses are generated in the BD (Backward Delay) and the HBD (Half Backward Delay), respectively.
[0204]
The reverse pulse RCL in the BD is output from the BD after moving backward exactly by the delay amount Δ. The backward pulse HCL in the HBD is output from the HBD after moving backward by the delay amount Δ / 2 accurately.
[0205]
The internal clock CLK is input to BD and HBD, and determines the generation timing of the backward pulse. The inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 is input to the FD and controls the period (delay amount) in which the forward pulse advances.
[0206]
The backward pulse RCL becomes a corrected internal clock CK ′ that matches the phase of the external clock CK after passing through the delay circuit 34 having the delay amount D1 + (D2 × 2). Further, the backward pulse HCL, when passing through the delay circuit 36 having the delay amount D2, becomes the internal clock CKD whose phase is delayed by T / 2 (= 180 °) with respect to the external clock CK.
[0207]
Here, the delay amount A of the delay circuit 32 is set to 2 × (D1 + D2).
[0208]
FIG. 30 shows a second example of the configuration of the clock control circuit of the present invention.
[0209]
This clock control circuit generates an internal clock CKD whose phase is delayed by T / j (= 2π / j) with respect to the external clock CK together with the internal clock CK ′ whose phase is identical to that of the external clock CK. (T is the period of the external clock, j is a natural number).
[0210]
The external clock CK is input to the input buffer 13 having a delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to a delay circuit 32 having a delay amount A, and the delay circuit 32 outputs a delay imitation pulse CL (forward pulse FCL1).
[0211]
The delayed imitation pulse CL is input to an FD (Forward Delay) of an STBD (Synchronous Traced Backward Delay). After the delay imitation pulse CL advances by the delay amount Δ in the FD, backward pulses are generated in the BD (Backward Delay) and 1 / jBD (Backward Delay), respectively.
[0212]
The reverse pulse RCL in the BD is output from the BD after moving backward exactly by the delay amount Δ. Further, the backward pulse 1 / jCL in 1 / jBD is outputted from 1 / jBD after being advanced by the delay amount Δ / j accurately.
[0213]
The internal clock CLK is input to BD and 1 / jBD, and determines the generation timing of the backward pulse. The inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 is input to the FD and controls the period (delay amount) in which the forward pulse advances.
[0214]
The backward pulse RCL becomes the corrected internal clock CK ′ that matches the phase of the external clock CK after passing through the delay circuit 34 having the delay amount (j−1) × D1 + j × D2. Further, the backward pulse 1 / jCL becomes an internal clock CKD whose phase is delayed by T / j (= 360 ° / n) with respect to the external clock CK through the delay circuit 36 having the delay amount D2.
[0215]
Here, the delay amount A of the delay circuit 32 is set to j × (D1 + D2).
[0216]
FIG. 31 shows a third example of the configuration of the clock control circuit of the present invention.
[0217]
The clock control circuit includes an internal clock CK ′ whose phase is identical to that of the external clock CK and an internal clock whose phase is delayed by (k / j) × T (= 2π × k / j) with respect to the external clock CK. CKD is generated (T is the period of the external clock, k, j are relatively prime natural numbers, j> k).
[0218]
The external clock CK is input to the input buffer 13 having a delay amount k × D1. The input buffer 13 outputs an internal clock CLK having a skew of k × D1 with respect to the external clock CK. The internal clock CLK is input to a delay circuit 32 having a delay amount A, and the delay circuit 32 outputs a delay imitation pulse CL (forward pulse FCL1).
[0219]
The delayed imitation pulse CL is input to an FD (Forward Delay) of an STBD (Synchronous Traced Backward Delay). After the delay imitation pulse CL advances by the delay amount Δ in the FD, backward pulses are generated in the BD (Backward Delay) and k / jBD (Backward Delay), respectively.
[0220]
The reverse pulse RCL in the BD is output from the BD after moving backward exactly by the delay amount Δ. Further, the backward pulse k / jCL in k / jBD moves backward by exactly the delay amount Δ × (k / j) and is then output from k / jBD.
[0221]
The internal clock CLK is input to BD and k / jBD, and determines the generation timing of the backward pulse. The inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 is input to the FD and controls the period (delay amount) in which the forward pulse advances.
[0222]
The backward pulse RCL becomes a corrected internal clock CK ′ that matches the phase of the external clock CK after passing through the delay circuit 34 having the delay amount (j−k) × D1 + j × D2. Further, the backward pulse k / jCL is delayed by T × (k / j) (= 360 ° × k / j) from the external clock CK through the delay circuit 36 having the delay amount k × D2. It becomes the internal clock CKD.
[0223]
Here, the delay amount A of the delay circuit 32 is set to j × (D1 + D2).
[0224]
FIG. 32 shows a fourth example of the configuration of the clock control circuit according to the present invention.
[0225]
The clock control circuit includes an internal clock CK ′ whose phase is identical to that of the external clock CK and an internal clock whose phase is delayed by T × (k / j) (= 2π × k / j) with respect to the external clock CK. CKD is generated (T is the period of the external clock, k, j are relatively prime natural numbers, j> k).
[0226]
The external clock CK is input to the input buffer 13 having a delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to a delay circuit 32 having a delay amount A, and the delay circuit 32 outputs a delay imitation pulse CL (forward pulse FCL1).
[0227]
The delayed imitation pulse CL is input to an FD (Forward Delay) of an STBD (Synchronous Traced Backward Delay). After the delay imitation pulse CL advances by the delay amount Δ in the FD, backward pulses are generated in the BD (Backward Delay) and k / jBD (Backward Delay), respectively.
[0228]
The reverse pulse RCL in the BD is output from the BD after moving backward exactly by the delay amount Δ. Further, the backward pulse k / jCL in k / jBD moves backward by exactly the delay amount Δ × (k / j) and is then output from k / jBD.
[0229]
The internal clock CLK is input to BD and k / jBD, and determines the generation timing of the backward pulse. The inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 is input to the FD and controls the period (delay amount) in which the forward pulse advances.
[0230]
The backward pulse RCL becomes the corrected internal clock CK ′ that matches the phase of the external clock CK after passing through the delay circuit 34 having the delay amount (j−1) × D1 + j × D2. Further, when the backward pulse k / jCL passes through the delay circuit 36 having the delay amount (k−1) × D1 + k × D2, the phase thereof is T × (k / j) (= 360 ° × k) with respect to the external clock CK. / J) becomes the internal clock CKD delayed by a delay.
[0231]
Here, the delay amount A of the delay circuit 32 is set to j × (D1 + D2).
[0232]
FIG. 33 shows a fifth example of the configuration of the clock control circuit of the present invention.
[0233]
This clock control circuit has an internal clock CK ′ that is in phase with the external clock CK, and a phase that is T / 4 (= 90 °), T / 2 (= 180 °), 3T / Internal clocks CKQ, CKH, and CK3Q delayed by 4 (= 270 °) are generated.
[0234]
The external clock CK is input to the input buffer 13 having a delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to a delay circuit 32 having a delay amount A, and the delay circuit 32 outputs a delay imitation pulse CL (forward pulse FCL1).
[0235]
The delayed imitation pulse CL is input to an FD (Forward Delay) of a SAD (Synchronous Adjustable Delay). SAD includes STBD (Synchronous Traced Backward Delay) and the like.
[0236]
After the delay imitation pulse CL advances by the delay amount Δ in the FD, backward pulses are generated in the BD (Backward Delay), QBD (Quarter Backward Delay), HBD (Half Backward Delay) and 3QBD (3 Quarters Backward Delay), respectively. The
[0237]
The backward pulse RCL in the BD is output from the BD after moving backward by a delay amount Δ (X delay elements). Further, the backward pulse QCL in the QBD moves backward by a delay amount Δ / 4 minutes (corresponding to four delay elements X) and then is output from the QBD. The backward pulse HCL in the HBD has a delay amount Δ / 2 minutes ( The backward pulse 3QCL is output from the HBD after moving backward by the delay element X / 2), and the backward pulse 3QCL in the 3QBD is output from the 3QBD after moving backward by the delay amount 3Δ / 4 minutes (for the delay element 3X / 4). The
[0238]
The internal clock CLK is input to each of BD, QBD, HBD, and 3QBD, and determines the generation timing of the backward pulse. The inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 is input to the FD and controls the period (delay amount) in which the forward pulse advances.
[0239]
The backward pulse RCL passes through the delay circuit 34 having a delay amount (D1 × 3 + D2 × 4) and becomes a corrected internal clock CK ′ that matches the phase of the external clock CK.
[0240]
Further, the backward pulse QCL becomes the internal clock CKQ whose phase is delayed by T / 4 (= 90 °) with respect to the external clock CK when passing through the delay circuit 36a having the delay amount D2.
[0241]
Further, the backward pulse HCL passes through the delay circuit 36b having the delay amount (D1 + D2 × 2), and becomes the internal clock CKH whose phase is delayed by T / 2 (= 180 °) with respect to the external clock CK.
[0242]
Further, the backward pulse 3QCL becomes an internal clock CKD whose phase is delayed by 3T / 4 (= 270 °) with respect to the external clock CK when passing through a delay circuit 36c having a delay amount (D1 × 2 + D2 × 3).
[0243]
Here, the delay amount A of the delay circuit 32 is set to 4 × (D1 + D2).
[0244]
FIG. 34 shows the configuration of the clock control circuit of FIG. 32 in detail.
[0245]
The external clock CK is given to the input terminal 30 of the memory. The external clock CK is input to the input buffer 13 having a delay amount D1. The input buffer 13 outputs an internal clock CLK having a D1 skew with respect to the external clock CK. The internal clock CLK is input to a delay circuit 32 having a delay amount A, and the delay circuit 32 outputs a forward pulse FCL1 (delay imitation pulse CL).
[0246]
The internal clock CLK and the inverted internal clock / CLK obtained by inverting the internal clock CLK by the inverter 35 are respectively input to n (n is a natural number) delay units 33-1, 33-2, ... 33-n. .
[0247]
The n delay units 33-1, 33-2,... 33-n are connected in series with each other. A forward pulse FCL1 is input to the first-stage delay unit 33-1 and a backward pulse RCL1 is output from the first-stage delay unit 33-1.
[0248]
The control pulses P and / P output from the control pulse generation circuit 60 are input to the n delay units 33-1, 33-2,... 33-n. The delay unit 33-i (i is 1 to n) outputs control pulses Qi and / Qi. The control pulses Qi, / Qi are input to the k / jBD 37.
[0249]
The backward pulse RCL1 becomes the corrected internal clock CK ′ by passing through the delay circuit 34 having the delay amount (j−1) × D1 + j × D2.
[0250]
The backward pulse k / jCL passes through the delay circuit 36 having the delay amount (k−1) × D1 + k × D2, so that the phase is T × (k / j) (= 360 ° × k) with respect to the external clock CK. / J) becomes the internal clock CKD delayed by a delay.
[0251]
FIG. 35 shows the first example of the configuration of the delay unit of FIG. 34 in detail.
[0252]
The delay unit Ui (i = 1 to n) includes three parts: a forward pulse delay circuit, a state holding circuit, and a reverse pulse delay circuit.
[0253]
The forward pulse delay circuit is composed of three inverters 41-43. The inverters 41 and 42 are connected in series, and the inverter 41 receives the output signal FCLi of the preceding delay unit, and the inverter 42 outputs the output signal FCLi + 1 to the subsequent delay unit. The operation of the inverter (clocked inverter) 41 is controlled by the control pulse / P. For example, when the control pulse / P is “1”, the inverter 41 is activated.
[0254]
The output terminal of the inverter 43 is connected to the input terminal of the inverter 42, and a potential of “0” (for example, ground potential) is always applied to the input terminal of the inverter 43. The operation of the inverter (clocked inverter) 43 is controlled by the control pulse P. For example, when the control pulse P is “1”, the inverter 43 is activated.
[0255]
The reverse pulse delay circuit is composed of three inverters 44-46. The inverters 44 and 45 are connected in series, and the inverter 44 receives the output signal RCLi + 1 of the subsequent delay unit or the internal clock CLK, and the inverter 45 receives the output signal RCLi to the previous delay unit. Output. The operation of the inverter (clocked inverter) 44 is controlled by the control pulse Qi. For example, the inverter 44 is activated only when the control pulse Qi is “1”.
[0256]
The output terminal of the inverter 46 is connected to the input terminal of the inverter 45, and the internal clock CLK is always input to the input terminal of the inverter 46. The operation of the inverter (clocked inverter) 46 is controlled by the control pulse / Qi. For example, when the control pulse / Qi is “1”, the inverter 46 is activated.
[0257]
The state holding circuit includes a state holding unit 47 and NAND circuits 48 and 49. The NAND circuit 48 receives the output signal FCLi of the preceding delay unit and the inverted internal clock / CLK, and the NAND circuit 49 receives the output signal of the inverter 45 and the internal clock CLK.
[0258]
The output signal of the NAND circuit 48 becomes the set input / S of the state holding unit 47, and the output signal of the NAND circuit 49 becomes the reset input / R of the state holding unit 47. Therefore, when the output signal (set input) / S of the NAND circuit 48 becomes “0”, the state holding unit 47 is set, and the output signal (reset input) / R of the NAND circuit 49 becomes “0”. When this happens, the state holding unit 47 enters a reset state.
[0259]
The state holding unit 47 is also configured to output control pulses Q and / Q. The control pulse Q is “1” when the state holding unit 47 is in the set state, and the control pulse / Q is “1” when the state holding unit 47 is in the reset state.
[0260]
As the state holding unit 47, for example, a configuration as shown in FIG. 4 can be used.
[0261]
In the delay unit Ui through which the forward pulse has passed, the control pulse Qi becomes “H” and / Qi becomes “L”. On the other hand, in the delay unit Ui through which the backward pulse has passed, the control pulse Qi becomes “L” and / Qi becomes “H”.
[0262]
FIG. 36 shows a second example of the configuration of the delay unit of FIG. 34 in detail.
[0263]
The delay unit Ui (i = 1 to n) includes three parts: a forward pulse delay circuit fdi, a state holding circuit sri, and a backward pulse delay circuit bdi.
[0264]
The forward pulse delay circuit fdi is composed of five inverters 91-95. The inverters 91 to 93 are connected in series, the inverter 91 receives the output signal FCLi of the preceding delay unit, and the inverter 92 outputs the output signal FCLi + 1 to the subsequent delay unit. The operation of the inverter (clocked inverter) 91 is controlled by the control pulse / P. For example, when the control pulse / P is “1”, the inverter 91 is activated.
[0265]
The output terminal of the inverter 94 is connected to the output terminal of the inverter 91 and also connected to the input terminals of the inverters 92 and 95. The input terminal of the inverter 94 is always “0”. (For example, ground potential) is applied. The operation of the inverter (clocked inverter) 94 is controlled by the control pulse P. For example, when the control pulse P is “1”, the inverter 94 is activated.
[0266]
The reverse pulse delay circuit bdi is composed of five inverters 96-100. The inverters 96 to 98 are connected in series, and the inverter 96 receives the output signal RCLi + 1 of the subsequent delay unit or the internal clock CLK. The inverter 97 receives the output signal RCLi to the preceding delay unit. Output. The operation of the inverter (clocked inverter) 96 is controlled by the control pulse Qi. For example, the inverter 96 is activated only when the control pulse Qi is “1”.
[0267]
The output terminal of the inverter 99 is connected to the output terminal of the inverter 96 and to the input terminals of the inverters 97 and 100. The input terminal of the inverter 99 is always connected to the internal clock. CLK is input. The operation of the inverter (clocked inverter) 99 is controlled by the control pulse / Qi. For example, when the control pulse / Qi is “1”, the inverter 99 is activated.
[0268]
The state holding circuit sri includes P-channel MOS transistors 101 and 102, N-channel MOS transistors 103 and 104, and an inverter 105.
[0269]
P-channel MOS transistors 101 and 102 are connected in series between the power supply terminal and node Z, and N-channel MOS transistors 103 and 104 are connected in series between the ground terminal and node Z.
[0270]
A clock signal / CLK obtained by inverting the internal clock CLK is input to the gates of the MOS transistors 101 and 104, and an output signal / RCLi-3 of the delay unit Ui-3 is input to the gate of the MOS transistor 102. The output signal FFCLi of the delay unit Ui-1 is input to the gate of the MOS transistor 103.
[0271]
The input terminal of the inverter 105 is connected to the node Z, and the control pulse Qi-2 is output from the output terminal of the inverter 105. From the node Z, a control pulse / Qi-2 is output.
[0272]
37 and 38 show an example of the configuration of k / jBD in FIG.
[0273]
In this example, a case where k is 1 and j is 2, that is, a case where the phase is delayed by T / 2 with respect to the external clock will be described. In this case, k / jBD is HBD (Half Backward Delay).
[0274]
The HBD is composed of m (m is a natural number) delay units bdi (i = 1 to m) connected in series. The configuration of each delay unit bdi is the same as the configuration of the backward pulse delay circuit bdi of the delay unit Ui of SAD (Synchronous Adjustable Delay).
[0275]
Therefore, the ratio of the delay amount of the backward pulse in the BD and the delay amount of the backward pulse in the HBD is the ratio of the number of delay units in the BD to the number of delay units in the HBD, more precisely, the number of delay units of the BD in one block. It becomes equal to the ratio of the number of delay units of HBD.
[0276]
Specifically, in this example, n delay units Ui (i = 1 to n) and m delay units bdi (i = 1 to m) are respectively divided into r (r is a natural number) block B ( 1), B (2),... B (r).
[0277]
For example, the block B (1) is composed of two delay units U1, U2 and one delay unit bd1, and a control pulse Q1, / Q1 for controlling the delay unit U1 and a control pulse Q2, for controlling the delay unit U2. Any one of / Q2 is given to the delay unit bd1.
[0278]
Similarly, the block B (r) is composed of two delay units Un-1 and Un and one delay unit bdm, and the control pulses Qn-1, / Qn-1 and the delay for controlling the delay unit Un-1 One of the control pulses Qn and / Qn for controlling the unit Un is given to the delay unit bdm.
[0279]
That is, in this example, one delay unit of HBD is provided for two delay units of SAD. Therefore, in the BD, the backward pulse is delayed by Δ, whereas in the HBD, the backward pulse is delayed by Δ / 2.
[0280]
In this example, r and m are equal and have a relationship of m = n / 2. In the above description, the relatively prime natural numbers j and k that are frequently used are j = 2 (equal to the number of SAD delay units in one block) and k = 1 (delay of the HBD in one block). Equal to the number of units).
[0281]
The total number n of SAD delay units is j (2 in this example) × r, and the total number m of HBD delay units is k (1 in this example) × r.
[0282]
The HBD delay units bd1 to bdm are preferably arranged equally to the SAD delay units U1 to Un. That is, if one delay unit of HBD is associated with two delay units adjacent to SAD, a delay of Δ / 2 can be generated accurately.
[0283]
FIG. 39 shows an example of the configuration of the delay unit bdi in the HBD.
[0284]
In this example, the delay unit Ui of FIG. 35 is used. That is, since the backward pulse delay circuit of the delay unit Ui is composed of the three inverters 44 to 46, the delay unit bdi in the HBD is also composed of the three inverters 44 'to 46'.
[0285]
The inverters 44 ′ and 45 ′ are connected in series. The output signal HCLi + 1 of the subsequent delay unit or the internal clock CLK is input to the inverter 44 ′. The inverter 45 ′ is connected to the delay unit of the previous stage. Output signal HCLi is output. The operation of the inverter (clocked inverter) 44 'is controlled by the control pulse Qi. For example, the inverter 44' is activated only when the control pulse Qi is "1".
[0286]
The output end of the inverter 46 'is connected to the input end of the inverter 45', and the internal clock CLK is always input to the input end of the inverter 46 '. The operation of the inverter (clocked inverter) 46 ′ is controlled by the control pulse / Qi. For example, when the control pulse / Qi is “1”, the inverter 46 ′ is activated.
[0287]
FIG. 40 shows the delay unit bdi of FIG. 39 as a symbol. Therefore, the circuit of FIG. 39 and the circuit of FIG. 40 are the same.
[0288]
FIG. 41 shows an example of the configuration of k / jBD in FIG.
[0289]
In this example, a case where j is 3 and k is 1, that is, a case where the phase is delayed by T / 3 with respect to the external clock will be described.
[0290]
The 1 / 3BD is composed of m delay units bdi (i = 1 to m) connected in series. The configuration of each delay unit bdi is the same as the configuration of the backward pulse delay circuit bdi of the delay unit Ui of SAD (Synchronous Adjustable Delay).
[0291]
Therefore, the ratio of the delay amount of the backward pulse in the BD and the delay amount of the backward pulse in the 1/3 BD is the ratio of the number of delay units in the BD to the number of delay units in the 1/3 BD, more precisely in one block. This is equal to the ratio of the number of BD delay units to the number of 1/3 BD delay units.
[0292]
Specifically, in this example, n delay units Ui (i = 1 to n) and m delay units bdi (i = 1 to m) are divided into r blocks B (1) and B (2 ),... B (r).
[0293]
For example, the block B (1) is composed of three delay units U1 to U3 and one delay unit bd1, and control pulses Q1 and / Q1 for controlling the delay unit U1 are given to the delay unit bd1. However, instead of the control pulses Q1 and / Q1, a control pulse for controlling the delay unit U2 or the delay unit U3 may be given to the delay unit bd1.
[0294]
In other words, in this example, one delay unit of 1/3 BD is provided for three delay units of SAD. Therefore, in BD, the backward pulse is delayed by Δ, whereas in 1/3 BD, the backward pulse is delayed by Δ / 3.
[0295]
In this example, r and m are equal and have a relationship of m = n / 3. In the above description, the relatively prime natural numbers j and k that are frequently used are j = 3 (equal to the number of SAD delay units in one block) and k = 1 (delay of the HBD in one block). Equal to the number of units).
[0296]
The total number n of SAD delay units is j (3 in this example) × r, and the total number m of HBD delay units is k (1 in this example) × r.
[0297]
Also, the 1/3 BD delay units bd1 to bdm are preferably arranged equally to the SAD delay units U1 to Un. That is, if one delay unit of 1/3 BD is associated with three delay units adjacent to each other in SAD, a delay of Δ / 3 can be generated accurately.
[0298]
FIG. 42 shows an example of the configuration of k / jBD in FIG.
[0299]
In this example, a case where k is 2 and j is 3, that is, a case where the phase is delayed by 2T / 3 with respect to the external clock will be described.
[0300]
The 2 / 3BD is composed of m delay units bdi (i = 1 to m) connected in series. The configuration of each delay unit bdi is the same as the configuration of the backward pulse delay circuit bdi of the delay unit Ui of SAD (Synchronous Adjustable Delay).
[0301]
Therefore, the ratio of the delay amount of the backward pulse in the BD and the delay amount of the backward pulse in the 2/3 BD is the ratio of the number of delay units in the BD to the number of delay units in the 2/3 BD, more precisely, the BD in one block. It becomes equal to the ratio of the number of delay units to the number of delay units of 2/3 BD.
[0302]
Specifically, in this example, n delay units Ui (i = 1 to n) and m delay units bdi (i = 1 to m) are divided into r blocks B (1) and B (2 ),... B (r).
[0303]
For example, the block B (1) is composed of three delay units U1 to U3 and two delay units bd1 and bd2, and gives control pulses Q1 and / Q1 for controlling the delay unit U1 to the delay unit bd1. Control pulses Q3 and / Q3 for controlling U3 are given to the delay unit bd2.
[0304]
However, instead of the control pulses Q1, / Q1, Q3, / Q3, the control pulses Q1, / Q1, Q2, / Q2 may be given to the delay units bd1, bd2, or the control pulses Q2, / Q2, Q3 and / Q3 may be given to the delay units bd1 and bd2.
[0305]
That is, in this example, two delay units of 2/3 BD are provided for three delay units of SAD. Therefore, in BD, the backward pulse is delayed by Δ, whereas in 2 / 3BD, the backward pulse is delayed by 2Δ / 3.
[0306]
In this example, there is a relationship of m = 2n / 3. In the above description, the relatively prime natural numbers j and k that are frequently used are j = 3 (equal to the number of SAD delay units in one block) and k = 2 (delay of the HBD in one block). Equal to the number of units).
[0307]
The total number n of SAD delay units is j (3 in this example) × r, and the total number m of HBD delay units is k (2 in this example) × r. Since m / n = k × r / j × r, there is a relationship of m / n = k / j.
[0308]
Further, it is preferable that the 2 / 3BD delay units bd1 to bdm are equally arranged with respect to the SAD delay units U1 to Un. That is, if two delay units of 2 / 3BD are made to correspond to three delay units adjacent to SAD, a delay of 2Δ / 3 can be generated accurately.
[0309]
FIG. 43 generally shows the configuration of k / jBD in FIG. FIG. 44 shows the configuration of k / jBD in one block B (i) of FIG.
[0310]
The SAD is composed of r blocks B (1) to B (r). In SAD, each block includes j delay units. Similarly, k / jBD is composed of r blocks B (1) to B (r). In k / jBD, each block includes k delay units.
[0311]
j and k are natural numbers that are relatively prime to each other, and it is common to set j> k. Since r blocks exist, the total number n of SAD delay units is r × j, and the total number m of k / jBD delay units is r × k.
[0312]
The number of SAD blocks is equal to the number of k / jBD blocks. For example, the SAD block B (1) corresponds to the k / jBD block (1), the SAD block B (2) corresponds to the k / jBD block (2), and the SAD block B (r ) Corresponds to block (r) of k / jBD.
[0313]
For example, the SAD block (1) is controlled by j sets of control pulses Q1, / Q1, Q2, / Q2,... Qj, / Qj. Therefore, only k (<j) sets of these j sets of control pulses are selected, and these k sets of control pulses are supplied to the block (1) of k / jBD.
[0314]
The k sets of control pulses are regularly and evenly selected from j sets of control pulses Q1, / Q1, Q2, / Q2,... Qj, / Qj.
[0315]
The selected k sets of control pulses are regularly given to k delay units corresponding to k / jBD. For example, when the control pulses Q1, / Q1, Q2, / Q2 are selected, the control pulses Q1, / Q1 are given to the delay unit bd1 of k / jBD (not given to bd2), and the control pulses Q2, / Q2 Is given to the delay unit bd2 of k / jBD (not given to bd1).
[0316]
According to such a configuration, the ratio of the number of delay units of SAD and the number of delay units of k / jBD is always k / j = m / n regardless of the position of the delay unit at which the forward pulse of SAD arrives. To meet. Therefore, it is possible to accurately generate a delay amount of k / jΔ in k / jBD regardless of the position of the delay unit that the forward pulse reaches.
[0317]
Next, the principle of the present invention (in the case of the example of FIG. 31) will be described with reference to FIG.
[0318]
The skew width (delay amount) of the external clock CK and the internal clock CLK is k × D1, and the period of the external clock CK and the internal clock CLK is T.
[0319]
The delay imitation pulse CL is generated when the time A elapses from the time when the first pulse of the internal clock CLK is generated (when it rises). In this case, the time from the time when the delay imitation pulse CL is generated to the time when the second pulse of the internal clock CLK is generated is Δf.
[0320]
In addition, the time Δf is copied to make Δb, and when the time 2 × Δ (where Δf = Δb = Δ) elapses from the time when the delayed imitation pulse CL is generated, the delayed imitation pulse RCL is generated. To. Then, the time when the time A has elapsed from the time when the delayed imitation pulse RCL is generated coincides with the time when the third pulse of the internal clock CLK is generated. However, (A + W) <T. W is the width of the delayed imitation pulses CL and RCL.
[0321]
Assuming that the time from the time when the delayed imitation pulse RCL is generated to the time when the third pulse of the external clock CK is generated is (j−k) × D1 + j × D2, the delay imitation pulse RCL is time (j−k) × D1 + j. If delayed by × D2, a corrected internal clock CK ′ that matches the timing of the external clock CK can be obtained.
[0322]
That is, a delay circuit for generating the delay amount A, (2 × Δ), (j−k) × D1 + j × D2 is formed, and the internal clock CLK is set to the time A + (2 × Δ) + {(j−k) × D1 + j. If delayed by × D2}, a corrected internal clock CK ′ that matches the timing of the external clock CK is obtained.
[0323]
The delay amount (2 × Δ) is generated by SAD, and the delay amount (j−k) × D1 + j × D2 is generated by a delay element. The delay amount A is determined as follows.
[0324]
From the relationship of FIG.
k × D1 + A + Δ = T + k × D1 (1)
k × D1 + A + 2Δ + (j−k) × D1 + j × D2 = 2T (2)
Can guide.
[0325]
From equation (1), T = A + Δ (3) can be derived,
From the equation (2), A + 2Δ + j (D1 + D2) = 2T (4) can be derived.
[0326]
From equations (3) and (4),
A + 2Δ + j (D1 + D2) = 2 (A + Δ)
A = j (D1 + D2) (5)
It becomes.
[0327]
The principle of generating the internal clock CKD delayed by (k / j) × T with respect to the external clock CK is as follows.
[0328]
The time (k / j) × Δ (Δ = Δf = Δb) is created, and the delay pulse k / jCL is generated when the time Δ + (k / j) × Δ elapses from the time when the delay imitation pulse CL is generated. Like that. Further, the internal clock CKD is generated when the time k × D2 has elapsed since the generation of the delay pulse k / jCL.
[0329]
At this time, as apparent from FIG. 45, the internal clock CKD is compared to the external clock CK.
k × D1 + (k / j) × Δ + k × D2 (6)
Will be delayed only.
[0330]
When formula (6) is transformed,
(K / j) × (j × D1 + Δ + j × D2)
= (K / j) × {j (D1 + D2) + Δ} (7)
It becomes.
[0331]
Equation (7) is obtained from the equations (3) and (5) above.
(K / j) × T (8)
It becomes.
[0332]
That is, the internal clock CKD means that the phase is delayed by (k / j) × T with respect to the external clock CK.
[0333]
Therefore, if a delay circuit for generating the delay amounts A, Δ + (k / j) × Δ, k × D2 is formed and the internal clock CLK is delayed by time A + {Δ + (k / j) × Δ} + k × D2. Thus, an internal clock CKD whose phase is delayed by (k / j) × T with respect to the external clock CK is obtained.
[0334]
The delay amount Δ is generated by the FD of the SAD, and the delay amount k × D2 is generated by the delay element. The delay amount A is set to j (D1 + D2) as shown in the equation (5) by the above-described method.
[0335]
Next, the principle of the present invention (in the case of the example of FIG. 32) will be described with reference to FIG.
[0336]
The skew width (delay amount) of the external clock CK and the internal clock CLK is D1, and the period of the external clock CK and the internal clock CLK is T.
[0337]
The delay imitation pulse CL is generated when the time A elapses from the time when the first pulse of the internal clock CLK is generated (when it rises). In this case, the time from the time when the delay imitation pulse CL is generated to the time when the second pulse of the internal clock CLK is generated is Δf.
[0338]
In addition, the time Δf is copied to make Δb, and when the time 2 × Δ (where Δf = Δb = Δ) elapses from the time when the delayed imitation pulse CL is generated, the delayed imitation pulse RCL is generated. To. Then, the time when the time A has elapsed from the time when the delayed imitation pulse RCL is generated coincides with the time when the third pulse of the internal clock CLK is generated. However, (A + W) <T. W is the width of the delayed imitation pulses CL and RCL.
[0339]
Assuming that the time from the generation of the delay imitation pulse RCL to the generation of the third pulse of the external clock CK is (j−1) × D1 + j × D2, the delay imitation pulse RCL is time (j−1) × D1 + j. If delayed by × D2, a corrected internal clock CK ′ that matches the timing of the external clock CK can be obtained.
[0340]
That is, a delay circuit for generating the delay amounts A, (2 × Δ), (j−1) × D1 + j × D2 is formed, and the internal clock CLK is converted to the time A + (2 × Δ) + {(j−1) × D1 + j. If delayed by × D2}, a corrected internal clock CK ′ that matches the timing of the external clock CK is obtained.
[0341]
The delay amount (2 × Δ) is generated by SAD, and the delay amount (j−1) × D1 + j × D2 is generated by a delay element. The delay amount A is determined as follows.
[0342]
From the relationship of FIG.
D1 + A + Δ = T + D1 (9)
D1 + A + 2Δ + (j−1) × D1 + j × D2 = 2T (10)
Can guide.
[0343]
From equation (9), T = A + Δ (11) can be derived,
From equation (10), A + 2Δ + j (D1 + D2) = 2T (12) can be derived.
[0344]
From equations (11) and (12)
A + 2Δ + j (D1 + D2) = 2 (A + Δ)
A = j (D1 + D2) (13)
It becomes.
[0345]
The principle of generating the internal clock CKD delayed by (k / j) × T with respect to the external clock CK is as follows.
[0346]
The time (k / j) × Δ (Δ = Δf = Δb) is created, and the delay pulse k / jCL is generated when the time Δ + (k / j) × Δ elapses from the time when the delay imitation pulse CL is generated. Like that. The internal clock CKD is generated when time (k−1) × D2 + k × D2 elapses from the time when the delay pulse k / jCL is generated.
[0347]
At this time, as is clear from FIG. 46, the internal clock CKD is compared to the external clock CK.
D1 + (k / j) × Δ + (k−1) × D1 + k × D2 (14)
Will be delayed only.
[0348]
When the equation (14) is transformed,
(K / j) × (j × D1 + Δ + j × D2)
= (K / j) × {j (D1 + D2) + Δ} (15)
It becomes.
[0349]
Equation (15) is obtained from the above equations (11) and (12).
(K / j) × T (16)
It becomes.
[0350]
That is, the internal clock CKD means that the phase is delayed by (k / j) × T with respect to the external clock CK.
[0351]
Therefore, if a delay circuit for generating the delay amounts A, Δ + (k / j) × Δ, k × D2 is formed and the internal clock CLK is delayed by time A + {Δ + (k / j) × Δ} + k × D2. Thus, an internal clock CKD whose phase is delayed by (k / j) × T with respect to the external clock CK is obtained.
[0352]
The delay amount Δ is generated by the FD of the SAD, and the delay amount k × D2 is generated by the delay element. The delay amount A is set to j (D1 + D2) by the above-described method as shown in the equation (13).
[0353]
FIG. 47 shows a connection relationship between a controller that generates an external clock and receives data and a memory that outputs data based on an internal clock generated from the external clock.
[0354]
In the above-described example, the technique for clearly determining the phase relationship between the external clock and the internal clock and outputting accurate data from the memory has been described. In this example, a technique will be described in which the controller can accurately receive accurate data read from such a memory.
[0355]
In general, a memory system includes a controller (CPU) and a plurality of memories (ICs). Also, it takes a certain time for the external clock CK to reach the memories 1 and 2 from the controller. Therefore, first, the wiring length of the external clock from the controller to each of the memories 1 and 2 is made equal.
[0356]
Further, the memory 1 or the memory 2 outputs data based on an internal clock having a fixed phase relationship with respect to the external clock CK. The data is guided to the controller via the data bus.
[0357]
The controller receives data from the memory 1 or the memory 2, but the data is output from the memory 1 or the memory 2 and input to the controller depending on the wiring length, wiring capacity, etc. of the data bus. Takes a certain amount of time.
[0358]
That is, in order to capture accurate data, the controller needs to capture data at a timing that takes into account the propagation time of the data bus data.
[0359]
Therefore, a dummy memory (IC) having an external clock input capacity equal to the memories 1 and 2 is prepared. The wiring length of the external clock from the controller to the dummy memory is made equal to the wiring length of the external clock from the controller to each of the memories 1 and 2.
[0360]
Further, the external clock CK input to the dummy IC is further returned to the controller, and this is used as a return clock.
[0361]
The return clock determines the timing at which the controller receives the output data of the memory 1 or memory 2. Therefore, the wiring length of the return clock from the dummy memory to the controller is made equal to the data bus length from the memory 1 or the memory 2 to the controller.
[0362]
As described above, the controller receives data from the memory 1 or the memory 2 based on the return clock. Therefore, erroneous data is not input to the controller.
[0363]
【The invention's effect】
As described above, the clock control circuit of the present invention has the following effects.
[0364]
An internal clock that always has a constant phase relationship with the external clock can be generated stably, and even if the period of the external clock changes, the internal clock is The clock always has a constant phase relationship.
[0365]
Therefore, the present invention is most suitable for controlling a data input / output circuit of a clock synchronous DRAM such as a so-called synchronous memory.
[0366]
In addition, when a plurality of data is output in one cycle of the clock by controlling to divide the clock cycle and output the data, the phase is a predetermined amount with respect to the external clock. Although a plurality of accurately shifted internal clocks are required, according to the present invention, such a plurality of internal clocks can be easily generated without using a complicated system such as a PLL.
[Brief description of the drawings]
FIG. 1 is a diagram showing a main part of a system including a memory having a circuit of the present invention.
FIG. 2 is a diagram showing a configuration of a clock control circuit in the memory of FIG. 1;
3 is a circuit diagram showing in detail a delay unit in the circuit of FIG. 2;
4 is a circuit diagram showing in detail a state holding unit in the delay unit of FIG. 3;
FIG. 5 is a diagram showing in detail a control pulse generation circuit in the circuit of FIG. 2;
FIG. 6 is a diagram showing the principle of the present invention.
FIG. 7 is a timing chart showing the operation of the circuits of FIGS.
FIG. 8 is a diagram showing a state of a in the timing diagram of FIG. 7;
FIG. 9 is a diagram showing a state of b in the timing diagram of FIG. 7;
10 is a diagram showing a state of c in the timing diagram of FIG. 7;
11 is a diagram showing a state d in the timing chart of FIG. 7;
12 is a diagram showing a state “e” in the timing chart of FIG. 7. FIG.
13 is a diagram showing a state f in the timing chart of FIG. 7;
14 is a diagram illustrating a state of g in the timing diagram of FIG. 7;
FIG. 15 is a diagram illustrating a state h in the timing diagram of FIG. 7;
16 is a diagram showing a state i in the timing diagram of FIG. 7;
FIG. 17 is a diagram showing a modification of the circuit of FIG.
18 is a diagram showing a modification of the circuit of FIG.
19 is a diagram showing in detail a delay circuit 34 in the circuit of FIG.
20 is a diagram showing in detail a control pulse generation and extension circuit 61 in the circuit of FIG.
FIG. 21 is a diagram showing a problem in the operation of the circuit of FIG. 2;
FIG. 22 is a timing chart showing the operation of the circuits of FIGS.
FIG. 23 is a diagram showing a layout when a circuit of the present invention is incorporated in a chip;
24 is a diagram showing the operation of the circuit of FIGS. 2 and 18. FIG.
25 is a diagram showing the operation of the circuit of FIGS. 2 and 18. FIG.
FIG. 26 is a diagram showing the operation of the circuit of FIGS. 2 and 18;
FIG. 27 is a diagram showing the operation of the circuit of FIGS. 2 and 18;
FIG. 28 is a diagram showing a schematic configuration of the clock control circuit of FIG. 2;
FIG. 29 is a diagram showing a first example of a clock control circuit according to the present invention.
FIG. 30 is a diagram showing a second example of the clock control circuit according to the present invention.
FIG. 31 is a diagram showing a third example of the clock control circuit according to the present invention;
FIG. 32 is a diagram showing a fourth example of the clock control circuit according to the present invention;
FIG. 33 is a diagram showing a fifth example of the clock control circuit according to the present invention;
34 is a diagram showing in detail the configuration of the clock control circuit of FIG. 1;
FIG. 35 is a diagram showing in detail the configuration of a delay unit Ui in the circuit of FIG.
36 is a diagram showing in detail the configuration of a delay unit Ui in the circuit of FIG. 34. FIG.
FIG. 37 is a diagram showing a first example of a configuration of an HBD.
FIG. 38 is a diagram showing a second example of the configuration of the HBD.
39 is a diagram showing a configuration of a delay unit bdi in FIG. 37 or FIG.
40 is a diagram showing the circuit of FIG. 39 as a symbol.
FIG. 41 is a diagram showing a first example of a 1 / 3BD configuration.
FIG. 42 is a diagram showing a second example of the structure of 1/3 BD.
FIG. 43 is a diagram showing a configuration of m / nBD.
44 is a diagram showing a configuration of a block B (i) in FIG. 43. FIG.
FIG. 45 is a diagram showing the principle of the present invention.
FIG. 46 is a diagram showing the principle of the present invention.
47 is a diagram showing a configuration of a memory system according to the present invention. FIG.
FIG. 48 is a diagram showing a main part of a conventional system.
49 is a circuit diagram showing a skew of an external clock and an internal clock in the system of FIG. 48. FIG.
FIG. 50 is a diagram showing the principle of a synchronization system as the basis of the present invention.
51 is a diagram showing an example of a circuit for achieving the principle of FIG. 50. FIG.
FIG. 52 is a diagram showing how the delay amounts Δf and Δb are determined in the circuit of FIG. 51;
[Explanation of symbols]
11: Memory, 12: CPU, 13: Buffer, 14: Input circuit, 15: Output circuit, 16: Write / read circuit, 17: Memory cell array, 18: Data bus, 21: Input terminal, 22: Input buffer, 23, 25-1 to 25-n, 29-1 to 29-n, 30: delay circuit, 24: forward delay array, 26: mirror control circuit, 27-1 to 27-n: control element, 28: reverse drive Delay array 31: Clock synchronous delay control circuit 32, 33-1-33-n, 34, 57, 62: Delay circuit 41-46, 59, 63, 66-68, 70: Inverter 47: State holding unit 48, 49, 64: NAND circuit 51, 52: P-channel MOS transistor, 53-56: N-channel MOS transistor Star, 58,69,71,72: NOR circuit, 60 and 61: control pulse generation circuit, 73: NAND circuit, 74: delay circuit 75: inverter - motor, 81 to 84: circuit pattern - down.

Claims (1)

A memory that outputs data based on an internal clock generated from an external clock, a dummy memory having an input capacity of the external clock equal to the memory, the external clock, and a return clock from the dummy memory A controller for determining a timing for receiving data output from the memory, and the wiring length of the external clock from the controller to the dummy memory is equal to the wiring length of the external clock from the controller to the memory. The memory system is characterized in that the return clock wiring length from the dummy memory to the controller is equal to the data bus length from the memory to the controller .

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