JP3409937B2 - D flip-flop circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention protects data immediately before turning off the power supply of a D flip-flop circuit even when the power supply is turned off, and then turns on the power supply to enable operation. The present invention relates to a D flip-flop circuit capable of returning the internal state of the D flip-flop circuit to the state immediately before the power is turned off.

[0002]

2. Description of the Related Art FIG. 12 is a circuit diagram showing a general master-slave type CMOS-D flip-flop circuit.

The transfer gates TG2 and TG3 are
The gates are controlled by the first control signal S1, and the transfer gates TG1 and TG4 are the first control signal S1.
Is a gate controlled by the second control signal S2 having a reverse phase.

One terminal of each of the transfer gates TG1 and TG3 is connected to the input terminal of the first CMOS inverter I1, the other terminal of the transfer gate TG3 is connected to the data input terminal 2, and the other terminal of the transfer gate TG1 is connected. The terminal is connected to the output terminal of the second CMOS inverter I2, and the output terminal of the first CMOS inverter I1 is connected to the input terminal of the second CMOS inverter I2. Further, one terminal of each of the transfer gates TG2 and TG4 is the third CM.
The input terminal of the OS inverter I3 is connected, the other terminal of the transfer gate TG3 is connected to the output terminal of the inverter I1, and the other terminal of the transfer gate TG2 is connected to the output terminal of the fourth CMOS inverter I4. The CMOS inverter I3 has a fourth output terminal
Connected to the input terminal of the CMOS inverter I4 of
The output terminal of the CMOS inverter I3 is connected to the data output terminal 3. In addition, 0 is a GND terminal and 1 is a power supply terminal.

Next, the operation of the above conventional circuit will be described.

FIG. 13 is a diagram showing a state of the conventional circuit shown in FIG.

In the conventional circuit shown in FIG. 12, when the first control signal S1 is High, the transfer gates TG2 and TG3 are turned on to transfer the transfer gate TG.
1 and TG4 are turned off and the first control signal S1 is low, the transfer gates TG2 and TG3 are turned off and the transfer gates TG1 and TG4 are turned on.
Further, it is assumed that the input data X is stored in the D flip-flop circuit and the input data Y is applied to the input terminal 2.

In FIG. 13A, the first control signal S1 is lo
In this case, the output data X is latched on the master side (inverters I1 and I2). This information (data X) is the transfer gate T
It is output via G4 and the inverter I3.

In FIG. 13B, the first control signal S1 is Hi.
In this case, the data X is latched on the slave side (inverters I3 and I4), and the inverted data of the input data Y appears at the output terminal of the inverter I1 via the transfer gate TG3.

In the circuit shown in FIG. 12, when the transfer gates TG2 and TG3 are on, the transfer gates TG1 and TG4 are turned off and the data is latched by the inverters I3 and I4, while the transfer gates TG2 and TG3 are turned on. When it is off, the transfer gates TG1 and TG4 are turned on, and the data is latched by the inverters I1 and I2.

That is, in the conventional example shown in FIG.
If the data stored in the flip-flop circuit is the data X and the input data Y is applied to the input terminal 2, the first control signal S1 is High or low.
, The D flip-flop circuit outputs the data X to its output terminal 3.

However, in the circuit shown in FIG. 12, when the power supply voltage such as power save is cut off in order to reduce the power consumption, the inverters I1, I2, I3 and I4 become inoperable and the latched data disappears. Therefore, there is a drawback that the original state (the state before the power save) is not always returned when returning from the power save.

As a means for solving this drawback, Japanese Patent Application No.
A balloon type master-slave D flip-flop circuit is shown in -268245.

FIG. 14 is a diagram showing a basic circuit of a conventional balloon type master-slave D flip-flop circuit.

In the conventional example shown in FIG. 14, the transfer gate TG5 and the transfer gate TG6 controlled by the third control signal S3 in the D flip-flop circuit shown in FIG. 12 are turned off when returning from the power saving.
A transfer gate TG7 controlled by the fourth control signal S4, which is turned on before power saving and turned off during power saving, and a memory circuit m1 are provided. The memory circuit m1 is connected to a power supply of another system so that the memory contents can be retained even when the power of the D flip-flop circuit is cut off. In addition, the transfer gate T
G5 and TG6 are connected in series with the transfer gates TG1 and TG4 of the D flip-flop circuit shown in FIG. 12, and the transfer gate TG7 is connected between the input terminal of the inverter I1 and the memory circuit m1. .

In the conventional example shown in FIG. 14, the transfer gate TG7 is turned on before the power saving and the inverter I
1 is written in the memory circuit m1, the transfer gate TG7 is turned off during power saving, and the memory circuit m1 is turned on.
1 protects the information in 1 and when the power save is restored, the transfer gate TG5 is turned off and the transfer gate TG7 is turned on.
The information of 1 is read to the input of the inverter I1, and the state of the D flip-flop circuit is restored. The memory circuit m
Even if 1 and the transfer gate TG7 are connected to the input terminal of the inverter I3, the same operation as above is executed.

FIG. 15 is a diagram showing a modification of the conventional example shown in FIG.

The conventional example shown in FIG. 15 is different from the conventional example shown in FIG. 14 in that an input terminal of an inverter I3 is connected with a memory circuit m2 similar to the memory circuit m1 and a transfer gate TG8 similar to the transfer gate TG7. It was done. In the conventional example shown in FIG. 15, since two sets of a memory circuit and a transfer gate are provided, it is possible to cope with both cases of latching by the master and latching by the slave. .

Next, the conventional operation shown in FIG. 15 will be described.

FIG. 16 shows a first control signal S1 in the conventional balloon type D flip-flop circuit shown in FIG.
FIG. 8 is an explanatory diagram of a write operation when is low.

When the first control signal S1 is low,
Similar to the case shown in FIG. 13A, the data X is latched on the master side, and at this time, the data X is applied from the memory circuit m1 to the input terminal of the inverter I1, and the data X is inverted by the inverter I1. Therefore, the inverted data of the data X is applied to the input terminal of the inverter I3, and at this time, the transfer gates TG7 and TG8 are transferred.
When is turned on, the data X and the inverted data of the data X are stored in the memory circuits m1 and m2, respectively.

FIG. 17 is an explanatory diagram for executing the read operation after the reading explained in FIG. 16 in the conventional balloon type D flip-flop circuit shown in FIG.

When the write data is read after the write operation described with reference to FIG. 16, the first control signal S1 changes to lo.
If it is w, the transfer gates TG2 and TG3 are turned off and the transfer gates TG1 and TG4 are turned on. Therefore, as shown in FIG.
The data X and the inverted data of the data X are read to the input of 3, respectively, and the data X appears at the output terminal 3,
The state of the original output terminal is restored. On the other hand, the first control signal S1
Is High, transfer gates TG2, TG3
Is turned on and the transfer gates TG1 and TG4 are turned off. Therefore, as shown in FIG. 17B, the inverter I1
The data X is read into the input terminal of the inverter I3
Although the inverted data of the data X is about to be read into the input terminal of, the driving capability of the input terminal 2 side is designed to be larger than the driving capability of the memory circuit m1, and therefore, via the transfer gate TG3. The input data Y is read into the input of the inverter I1, and the inverted data of the data Y is generated at the output terminal of the inverter I1. However, since the transfer gate TG4 is off, the inverted data of the data Y is not read into the input terminal of the inverter I3, the output data X is output to the output terminal 3, and this output data becomes the same as the original output data. Become.

FIG. 18 shows the first control signal S1 in the conventional balloon type D flip-flop circuit shown in FIG.
FIG. 8 is an explanatory diagram of a write operation when is High.

When the first control signal S1 is High,
Similar to FIG. 13B, the data X is latched on the slave side, and at this time, the input data Y of the inverter I1 and the input data of the inverter I3 become the inverted data of the data X. At this time, the transfer gates TG7 and TG8
When is turned on, inverted data of data Y and data X is stored in the storage circuits m1 and m2, respectively.

FIG. 19 is an explanatory diagram for executing the read operation after the reading explained in FIG. 18 in the conventional balloon type D flip-flop circuit shown in FIG.

When the write data is read after the write operation described with reference to FIG. 18, the first control signal S1 becomes Hi.
If it is gh, as shown in FIG.
The inverted data of the data Y and the data X are read to the input terminals of 1 and I3, respectively, and the output data X is output to the output terminal 3.
Occurs, and the output data becomes the same as the original output data.

However, if the first control signal S1 is low, as shown in FIG. 19 (2), the data Y is read to the input of the inverter I1 and the data X is read to the input terminal of the inverter I3. Inverted data is about to be read, but
The drive capability on the output terminal side of the inverter I1 is the memory circuit m2.
Since it is designed to be larger than the driving capacity of the inverter, the inverted data of the data Y is read out to the input terminal of the inverter I3 via the transfer gate TG4. Therefore, the output data of the D flip-flop circuit becomes the data Y, which is different from the original output data.

As described above, in the conventional circuit shown in FIG.
The state of the first control signal S1 before power saving,
Depending on the combination with the state of the first control signal S1 after power saving, there is a problem that the original output data cannot be restored after power saving.

FIG. 20 shows the conventional example shown in FIG.
It is a figure which shows the circuit which unified the memory circuit into one.

The circuit shown in FIG. 20 is different from the circuit shown in FIG. 15 in that the memory circuit m2 is deleted, the transfer gate TG9 is connected between the transfer gate TG7 and the memory circuit m1, and the transfer gate TG8 and the memory circuit m1 are connected. And the transfer gate TG10 is connected between the transfer gate TG9 and the transfer gate TG9.
Controlled by the control signal S2 of the transfer gate TG
Reference numeral 10 is controlled by the first control signal S1 which is in anti-phase with the second control signal S2.

The conventional example shown in FIG. 20 utilizes the fact that the slave latch and the master latch do not occur at the same timing and at the same time, and when the master is latching data, the transfer gate TG7 is used. , The data is written to and read from the memory circuit m1 via the transfer gate TG9, while the data is read from the memory circuit m1 and, when latched by the slave, the transfer gate TG
8. Storage circuit m via transfer gate TG10
The data is written in and read from the data in 2.

Next, the operation of the balloon type D flip-flop circuit shown in FIG. 20 will be described.

FIG. 21 shows the first control signal S1 in the conventional balloon type D flip-flop circuit shown in FIG.
FIG. 8 is an explanatory diagram of a write operation when is low.

When the first control signal S1 is low,
Since the transfer gates TG2 and TG3 are turned off and the transfer gates TG1 and TG4 are turned on, FIG.
As in (1), data X is latched on the master side,
At this time, the input data of the inverter I1 is the data X, and the input data of the inverter I3 is the inverted data of the data X. At this time, the transfer gate TG
7, when TG8 is turned on, transfer gate TG9
If is on, the transfer gate TG10 is turned off, and the data X is written in the memory circuit m1.

FIG. 22 is an explanatory diagram for executing the read operation after the reading explained in FIG. 21 in the conventional balloon type D flip-flop circuit shown in FIG.

When reading the data written in FIG. 21,
If the first control signal S1 is low, as shown in FIG. 22 (1), the data X is read out to the input terminal of the inverter I1, and the transfer gate TG10 is off at the input terminal of the inverter I3. Because of this, the data is not read and the transfer gate TG4 is on, so the output data of the output terminal 3 becomes the data X, and this output data becomes the same as the original output data.

When reading the data written in FIG. 21,
When the first control signal S1 is High, the transfer gates TG2, TG3 and TG10 are turned on and the transfer gates TG1, TG4 and TG9 are turned off.
2 (2), the input data Y is read into the input terminal of the inverter I1 via the transfer gate TG3. However, since the transfer gate TG4 is off, the data Y is not read into the input terminal of the inverter I3. At this time, the data X is read from the memory circuit m1 to the input terminal of the inverter I3 via the transfer gates TG10 and TG8, the output data of the output terminal 3 becomes the inverted data of the data X, and the output data is the original data. Is different from the output data of.

FIG. 23 shows the first control signal S1 in the conventional balloon type D flip-flop circuit shown in FIG.
FIG. 8 is an explanatory diagram of a write operation when is High.

When the first control signal S1 is High,
Since the transfer gates TG2 and TG3 are turned on and the transfer gates TG1, TG4, and TG9 are turned off, the data X is latched on the slave side as shown in FIG. The input data of the inverter I1 is the data Y, and the inverter I3
The input data of is the inverted data of the data X. At this time, when the transfer gates TG7 and TG8 are turned on, the inverted data of the data X output from the slave side is stored in the memory circuit m1 via the transfer gate TG8 and the transfer gate TG10, and the transfer gate TG9 is off. Moreover, the data Y is not stored in the storage circuit m1.

FIG. 24 is an explanatory diagram for executing the read operation after the reading explained in FIG. 23 in the conventional balloon type D flip-flop circuit shown in FIG.

When reading the data written in FIG. 23, if the first control signal S1 is High, the transfer gates TG2, TG3, TG10 are turned on and the transfer gates TG1, TG4, TG9 are turned off.
As shown in FIG. 24 (1), the inverted data of the data X is read out to the input terminal of the inverter I3, and the output terminal 3
The output data in is the data X, which is the same as the original output data. However, when the first control signal S1 is low, the transfer gates TG2, TG3, TG1
0 turns off, transfer gates TG1, TG4, T
Since G9 is turned on, the inverted data of the data X is read to the input terminal of the inverter I1 via the transfer gates TG9 and TG7, and the transfer gate TG10 is turned off, as shown in FIG. Therefore, nothing is read to the input terminal of the inverter I3, and the output data of the inverter I1 is read to the input terminal of the inverter I3 via the transfer gate TG4. Therefore, the output data of the output terminal 3 of the D flip-flop circuit becomes the inverted data of the data X, which is different from the original output data.

As described above, even in the conventional circuit shown in FIG. 20, depending on the combination of the state of the first control signal S1 before power saving and the state of the first control signal S1 after power saving, the original There is a problem that the output data cannot be restored.

[0044]

In the above conventional balloon type D flip-flop circuit, the state of the first control signal S1 before the power saving and the state of the first control signal S1 after the power saving are freely set. When set to
There is a problem that the original output data may not be restored, and in order to solve this problem, the state of the first control signal S1 before power saving and the state of the first control signal S1 after power saving It is necessary to add some circuit that limits and. However, this additional circuit causes another problem that the speed of the control system is deteriorated.

The present invention can always generate the original output data without limiting the state of the first control signal S1 before power saving and the state of the first control signal S1 after power saving. An object of the present invention is to provide a D flip-flop circuit.

[0046]

According to the present invention, a memory circuit having a positive polarity terminal and a negative polarity terminal, to which power is supplied from a different system from a master and a slave, is provided, and a D flip-flop circuit is in a power saving mode. , The path between the negative terminal of the memory circuit and the input terminal of the master is cut off, and the path between the positive terminal of the memory circuit and the input terminal of the slave is cut off, and the master and the slave are cut off. The path between the negative terminal of the memory circuit and the input terminal of the master is shut off during the operation.

[0047]

According to the present invention, a memory circuit having a positive polarity terminal and a negative polarity terminal, to which power is supplied from a system different from that of the master and the slave, is provided, and the memory is stored when the D flip-flop circuit is in the power saving mode. The circuit between the negative terminal of the circuit and the input terminal of the master is cut off, and the path between the positive terminal of the memory circuit and the input terminal of the slave is cut off. Since the path between the negative polarity terminal of and the input terminal of the master is cut off, the state of the first control signal S1 before the power saving and the state of the first control signal S1 after the power saving are not limited, and The original output data can be generated.

[0048]

1 is a diagram showing a first embodiment of the present invention.

In the first embodiment, the transfer gates TG2 and TG3 are gates controlled by the first control signal S1, and the transfer gates TG1 and TG.
G4 and TG9 are gates controlled by the second control signal S2 having a phase opposite to that of the first control signal S1, and transfer gates TG5 and TG6 are gates controlled by the third control signal S3. Gate TG7, TG8
Is a gate controlled by the fourth control signal S4.

One terminal of each of the transfer gates TG1 and TG3 is connected to the input terminal of the first CMOS inverter I1, the other terminal of the transfer gate TG3 is connected to the data input terminal 2, and the other terminal of the transfer gate TG1 is connected. Terminal is transfer gate T
It is connected via G5 to the output terminal of the second CMOS inverter I2, and the output terminal of the first CMOS inverter I1 is connected to the input terminal of the second CMOS inverter I2.

Further, transfer gates TG2, T
One terminal of each G4 is connected to the input terminal of the third CMOS inverter I3, and the transfer gate T
The other terminal of G4 is connected to the output terminal of the inverter I1, the other terminal of the transfer gate TG2 is connected to the output terminal of the fourth CMOS inverter I4 via the transfer gate TG6, and the other terminal of the third CMOS inverter I3 is connected. The output terminal is connected to the input terminal of the fourth CMOS inverter I4, and the output terminal of the third CMOS inverter I3 is connected to the data output terminal 3. In addition,
Reference numeral 0 is a GND terminal, and 1 is a power supply terminal.

Further, one terminal of the transfer gate TG7 controlled by the fourth control signal S4 has an inverter I
1 is connected to the input terminal of the transfer gate T
The other terminal of G7 is connected to one terminal of the transfer gate TG9, the other terminal of the transfer gate TG9 is connected to the negative terminal of the memory circuit m1a, and
Transfer gate TG controlled by control signal S4 of
One terminal of 9 is connected to the input terminal of the inverter I3, and the other terminal of the transfer gate TG9 is connected to the positive terminal of the memory circuit M1.

The memory circuit M1 is different from the power sources of the masters (inverters I1 and I2) and the slaves (inverters I3 and I4) in order to retain the stored contents even when the power of the D flip-flop circuit is cut off. For data written from the positive polarity terminal, the true value is output to the positive polarity terminal and the reverse value of the true value is output to the negative polarity terminal. As for the data written from the negative polarity terminal, the true value is output to the negative polarity terminal and the reverse value of the true value is output to the positive polarity terminal.

That is, in the first embodiment, the master is composed of the first inverter I1 forming the feed-forward path, the second inverter I2 forming the feedback path, and the first transfer gate TG1. The third inverter I3 forming the forward path, the fourth inverter I4 forming the feedback path, and the second transfer gate TG2 form a slave, and the input terminal of the D flip-flop circuit and the first inverter I1. A third transfer gate TG3 is provided between the master and the slave, and a fourth transfer gate TG4 is provided between the master and the slave.
The second and third transfer gates TG2 and TG3 are controlled by the first control signal S1, and the first and fourth transfer gates TG1 and TG4 are controlled by the first control signal S.
In the D flip-flop circuit controlled by the second control signal S2 having a phase opposite to that of 1, the fifth, sixth, seventh,
Eighth and ninth transfer gates TG5, TG6, T
G7, TG8, TG9 and a memory circuit M1 are provided.

The fifth transfer gate TG5 is D
A sixth transfer gate TG6, which is a transfer gate that shuts off the master feedback path when the flip-flop circuit returns from power save.
Is a transfer gate that cuts off the slave feedback path when the D flip-flop circuit returns from power save.

The memory circuit M1 has a positive polarity terminal and a negative polarity terminal. For data written from the positive polarity terminal, the true value is output to the positive polarity terminal and the reverse value of the true value is output to the negative polarity terminal. On the other hand, for the data written from the negative polarity terminal, the true value is output to the negative polarity terminal and the reverse value of the true value is output to the positive polarity terminal, and the master and slave are supplied with different power supply systems. Memory circuit.

In addition, the seventh transfer gate TG7
Is the negative terminal of the memory circuit M1 and the first inverter I when the D flip-flop circuit is in the power saving mode.
The eighth transfer gate TG8 is a transfer gate that cuts off a path from the input terminal of the first inverter I3 and the positive terminal of the memory circuit M1 and the third inverter I3 when the D flip-flop circuit is in the power saving mode. The ninth transfer gate TG9 is a transfer gate that cuts off the path to the input terminal.
When the master and the slave are cut off by the second terminal 2, the negative terminal of the memory circuit M1 and the first inverter I1
Is a transfer gate that cuts off the path from the input terminal of the.

Next, the operation of the first embodiment will be described.

FIG. 2 shows the first embodiment in the first embodiment.
FIG. 9 is a diagram for explaining a write operation when the control signal S1 of FIG.

Here, in the same manner as described with reference to FIG. 13, the data X is stored in the D flip-flop circuit, and the input terminal 2
It is assumed that the input data Y is applied to. Where the first
If the control signal S1 is low, the output data X is latched on the master side (inverters I1 and I2), the data X is input to the inverter I1, and the data X of the data X is transferred via the inverter I1 and the transfer gate TG4. The inverted data is input to the inverter I3. At this time,
When the first control signal S1 is low, the transfer gate TG9 is turned on. At this time, when the transfer gates TG7 and TG8 are turned on, the data X is written in the negative terminal of the memory circuit M1, The inverted data of the data X is written in the sex terminal.

FIG. 3 shows the first embodiment in the first embodiment.
FIG. 6 is a diagram illustrating an operation of reading the written data when the control signal S1 of FIG.

When the written data is read when the first control signal S1 is low, the first control signal S1 is
If it is low, as shown in FIG.
The data X is read out to the input terminal of 1 and the inverter I
The inverted data of the data X is read to the input terminal 3 of
The inverter I3 outputs the data X, that is, the output data of the output terminal 3 is the data X, and this output data becomes the same as the original output data.

On the other hand, when the written data is read when the first control signal S1 is low, if the first control signal S1 is High, the transfer gate TG9 is set as shown in FIG. 3B. Since it is turned off and the transfer gate TG3 is turned on, the input data Y is read into the inverter I1 via the transfer gate TG3,
The inverter I1 outputs inverted data of the data Y. However, since the transfer gate TG4 is off,
The inverted data of the data Y is not read by the inverter I3. At this time, the inverted data of the data X is read from the memory circuit M1 to the input terminal of the inverter I3 via the transfer gate TG8, and the inverter I3 outputs the data X, that is, the output data of the output terminal 3 is the data. X, and this output data is the same as the original output data.

FIG. 4 shows the first embodiment in the first embodiment.
FIG. 6 is a diagram for explaining a write operation when the control signal S1 of FIG.

When the first control signal S1 is High,
The data X is latched on the slave side, and the input data Y is
Inverter I1 via transfer gate TG3
The inverted data of the data X appears at the input terminal of the inverter I3. At this time, when the transfer gates TG7 and TG8 are turned on, the inverted data of the data X stored on the slave side is stored in the memory circuit M1 via the transfer gate TG8, while the transfer gate TG9 is turned off. Therefore, the data Y is not stored in the memory circuit M1.

FIG. 5 shows the first embodiment in the first embodiment.
FIG. 6 is a diagram illustrating an operation of reading the written data when the control signal S1 of FIG.

When the data written when the first control signal S1 is High is read when the first control signal S1 is High, as shown in FIG. 5A, the input terminal of the inverter I3 is used. , The inverted data of the data X is read, and the output data of the inverter I3 becomes the data X,
This output data is the same as the original output data.

On the other hand, when reading when the first control signal S1 is low, as shown in FIG. 5B, the inverter I1 is transferred through the transfer gates TG9 and TG7.
Of the data X is read to the input terminal of the inverter I3, the inverted data of the data X is read to the inverter I3, and the output data X is generated at the output terminal 3 of the D flip-flop circuit. It becomes the same as the data (data before power save).

According to the first embodiment, the state of the first control signal S1 before the power saving and the first control signal S1 after the power saving are performed.
The original output data can be restored regardless of the combination with the state of the control signal S1.

That is, in the conventional circuit shown in FIG. 20, the same terminal of the memory circuit m1 is written and read from both the master side and the slave side, whereas the first circuit shown in FIG. In the embodiment described above, the positive terminal of the memory circuit M1 is assigned to the slave side and the negative terminal of the memory circuit M1 is assigned to the master side.

In the conventional circuit shown in FIG. 20, the original output data is restored depending on the combination of the state of the first control signal S1 before power saving and the state of the first control signal S1 after power saving. Although it was impossible to do so, as in the first embodiment, on the slave side and the master side,
By allocating the positive terminal and the negative terminal of the memory circuit M1 respectively, the original output can be obtained regardless of the combination of the state of the first control signal S1 before power saving and the state of the first control signal S1 after power saving. It becomes possible to return to the data.

FIG. 6 is a diagram showing a more specific circuit example of the first embodiment.

This concrete circuit comprises, as the memory circuit M1, inverters 30 and 31, and a transfer gate TG13 which is turned off by a control signal SE only when data is written in the memory circuit M1.

FIG. 7 is a diagram showing a second embodiment of the present invention.

In the second embodiment, a transfer gate TG10 controlled by the first control signal S1 is connected in series between the memory circuit M1 and the transfer gate TG8 in the first embodiment. .

That is, the second embodiment differs from the first embodiment in that when the transfer gate TG2 is off, the positive terminal of the memory circuit M1 and the third inverter I3.
The tenth transfer gate TG10 for cutting off the path to the input terminal of is provided.

By constructing the second embodiment as described above, reverse writing from the slave side does not occur when reading to the master side.

That is, as described with reference to FIGS. 3 (1) and 5 (2), the transfer gate TG2 is turned off and the transfer gate TG9 is turned on at the time of reading to the master side, and the operation opposite to that of the transfer gate TG9 is performed. The transfer gate TG10 is turned off, and the slave side and the memory circuit M1 are separated from each other, thus eliminating the possibility of reverse writing from the slave side. But,
In the second embodiment, the transfer gate T
Since the G9 and the transfer gate TG10 operate in the opposite directions, either the transfer gate TG9 or the transfer gate TG10 is turned off at the time of writing to the memory circuit M1. Also, the writable memory circuit M1 is used.

FIG. 8 is a diagram showing a modification of the second embodiment.

In this modification, a memory circuit M2 is used instead of the memory circuit M1, and this memory circuit M2 uses inverters 30s and 31s.
The size of the s and 31s transistors is made sufficiently small, and by doing so, writing becomes possible.

That is, since the transistors of the inverters 30s and 31s are sufficiently small in size, the value of the current flowing through the inverters 30s and 31s is small, and in the end,
The impedances of the inverters 30s and 31s are equivalently increased, and the driving force of the inverters 30s and 31s is decreased (the driving force of the memory circuit M2 is decreased). Therefore, when writing to the memory circuit M2, the inverter 30s
The write data can be written in the memory circuit M2 regardless of the states of s and 31s.

FIG. 9 is a diagram showing a third embodiment of the present invention.

This third embodiment differs from the second embodiment shown in FIG. 7 in that the transfer gate TG11 controlled by the third control signal S3 and the transfer gate TG12 controlled by the fourth control signal S4. And a series circuit with
The transfer gates TG8 and TG10 are connected in parallel with a series circuit. The memory circuit M1 is a memory circuit which can be written only from the positive terminal.

That is, the third embodiment is similar to the second embodiment shown in FIG.
In the embodiment, the eleventh transfer gate TG11 is turned off when the memory circuit M1 is read and is turned on when the memory circuit M1 is written by the third control signal S3.
And a twelfth transfer gate TG12 which is turned on when writing to the memory circuit M1 by the fourth control signal S4.
And an eleventh transfer gate TG11 and a twelfth transfer gate TG12 are connected in series, and this series circuit is connected to the eighth transfer gate TG.
8 and the tenth transfer gate TG10 are connected in parallel with a series circuit.

In the third embodiment, at the time of reading, the transfer gate TG1 is controlled by the third control signal S3.
Since 1 is turned off, the configuration is similar to that of the second embodiment shown in FIG. 7, and therefore the possibility of reverse writing from the slave side is eliminated.

Further, regardless of the state of the first control signal S1, during writing, the transfer gate TG11 is turned on by the third control signal S3, and the transfer gate TG12 is turned on by the fourth control signal S4. Therefore, writing can be performed from the slave side, and the memory circuit M1 can be a memory circuit capable of writing only from the positive terminal.

FIG. 10 is a diagram showing a more specific circuit example of the third embodiment.

In the third embodiment, the transfer gate TG11 is turned off at the time of reading the memory circuit M1, so that there is no possibility of reverse writing from the slave side, and the eleventh transfer gate TG11 and the twelfth transfer gate are eliminated. The gate TG12 and the memory circuit M
Since it is turned on when writing 1, the writing from the slave side becomes possible. Also, the eleventh transfer gate T
The series circuit of G11 and the twelfth transfer gate TG12 corresponds to the eighth transfer gate TG8 and the tenth transfer gate TG8.
Since it is connected in parallel with the series circuit of the transfer gate TG10, the memory circuit M1 may be a memory circuit capable of writing only from the positive terminal.

FIG. 11 is a diagram showing a fourth embodiment of the present invention.

The fourth embodiment is a combination of the transfer gates TG8 and TG12 in the third embodiment, and the connection point between the transfer gate TG8 and the transfer gate TG10 in the third embodiment. And a transfer gate TG11 is connected between the positive terminal of the memory circuit M1 and the positive terminal. Even in this case, the same effect as that of the third embodiment can be obtained.

[0091]

According to the present invention, the state of the first control signal S1 before the power saving of the D flip-flop circuit and the state of the first control signal S1 after the power saving are not restricted and the original state is always maintained. Therefore, the D flip-flop circuit capable of storing the data at the time of power saving can be speeded up and downsized.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 shows a first control signal S1 in the first embodiment.
It is a figure explaining a write-in operation at the time of being low.

FIG. 3 shows the first control signal S1 in the first embodiment.
It is a figure explaining the operation which reads the written data, when it is low.

FIG. 4 shows a first control signal S1 in the first embodiment.
It is a figure explaining a write-in operation when it is High.

FIG. 5 shows the first control signal S1 in the first embodiment.
It is a figure explaining the operation which reads the written data, when it is High.

FIG. 6 is a diagram showing a more specific circuit example of the first embodiment.

FIG. 7 is a diagram showing a second embodiment of the present invention.

FIG. 8 is a diagram showing a modification of the second embodiment.

FIG. 9 is a diagram showing a third embodiment of the present invention.

FIG. 10 is a diagram showing a more specific circuit example of the third embodiment.

FIG. 11 is a diagram showing a fourth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a general master-slave type CMOS-D flip-flop circuit.

13 is a diagram showing a state of the conventional circuit shown in FIG.

FIG. 14 is a diagram showing a basic circuit of a conventional balloon type master-slave D flip-flop circuit.

15 is a diagram showing a modification of the conventional example shown in FIG.

16 is an explanatory diagram of a write operation when the first control signal S1 is low in the conventional balloon type D flip-flop circuit shown in FIG.

FIG. 17 is an explanatory diagram of executing a read operation after the read described in FIG. 16 in the conventional balloon type D flip-flop circuit shown in FIG.

18 is an explanatory diagram of a write operation when the first control signal S1 is High in the conventional balloon type D flip-flop circuit shown in FIG.

FIG. 19 is an explanatory diagram for executing the read operation after the read described in FIG. 18 in the conventional balloon type D flip-flop circuit shown in FIG. 15.

20 is a schematic circuit diagram of the conventional example shown in FIG.
It is a figure which shows the circuit made common to two.

21 is an explanatory diagram of a write operation when the first control signal S1 is low in the conventional balloon type D flip-flop circuit shown in FIG.

22 is a diagram showing the conventional balloon type D flip-flop circuit shown in FIG.
It is explanatory drawing which performs a read-out operation.

23 is an explanatory diagram of a write operation when the first control signal S1 is High in the conventional balloon type D flip-flop circuit shown in FIG.

24 is a diagram showing the conventional balloon type D flip-flop circuit shown in FIG.
It is explanatory drawing which performs a read-out operation.

[Explanation of symbols]

TR1 to TR13 ... Transfer gate, I1 to I4, 30, 30s, 31, 31s ... Inverter, S1 to S4, SE ... Control signal, M1, M2 ... Memory circuit, Y ... Input signal, X ... Output signal.

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 3/037 H03K 3/3562

Claims (4)

(57) [Claims] 1. A first constructing a feedforward path
Of the inverter (I1), the second inverter (I2) that forms the feedback path, and the first transfer gate (TG1), and the third inverter (I3) that forms the feed-forward path.
And a fourth inverter (I4) and a second transfer gate (TG2) that form a feedback path form a slave, and a slave is formed between the input terminal of the D flip-flop circuit and the first inverter (I1). Third
Transfer gate (TG3) is provided, a fourth transfer gate (TG4) is provided between the master and the slave, and the second and third transfer gates (TG2, TG3) are the first control units. Signal (S
1) and the first and fourth transfer gates (TG1, TG4) are controlled by a second control signal (S2) having a phase opposite to that of the first control signal (S1). A fifth transfer gate (TG5) for interrupting the feedback path of the master when the D flip-flop circuit returns from power save; and the slave when the D flip-flop circuit returns from power save. A transfer gate (TG6) for blocking the feedback path of the positive polarity terminal and the negative polarity terminal, and outputs the true value to the positive polarity terminal for the data written from the positive polarity terminal. The reverse of the true value is output to the negative terminal, and the data written from the negative terminal is A storage circuit (M1) that outputs a true value to the negative polarity terminal, outputs a reverse value of the true value to the positive polarity terminal, and is supplied with power from a different system from the master and the slave; and the D flip-flop. A seventh transfer gate (TG7) for blocking the path between the negative terminal of the memory circuit (M1) and the input terminal of the first inverter (I1) when the circuit is in the power saving mode; An eighth transfer gate (TG8) for blocking the path between the positive terminal of the memory circuit (M1) and the input terminal of the third inverter (I3) when the flip-flop circuit is in the power saving mode; When the master and the slave are cut off by the second control signal (S2), the negative terminal of the memory circuit (M1) and the input terminal of the first inverter (I1). Ninth transfer gate for blocking the path of the (TG9);
And a D flip-flop circuit. 2. The positive terminal of the memory circuit (M1) and the input terminal of the third inverter (I3) according to claim 1, when the second transfer gate (TG2) is off. A D flip-flop circuit having a tenth transfer gate (TG10) for shutting off the path. 3. An eleventh transfer gate (TG11) according to claim 2, which is turned off when the memory circuit (M1) is read out and is turned on when the memory circuit (M1) is written by the third control signal. ,
A twelfth transfer gate (TG1) which is turned on when the memory circuit (M1) is written by the fourth control signal.
2) and the eleventh transfer gate (T
G11) and the twelfth transfer gate (TG1)
2) is connected in series, and this series circuit is connected in parallel with a series circuit of the eighth transfer gate (TG8) and the tenth transfer gate (TG10). circuit. 4. The eleventh transfer gate (TG11) according to claim 2, which is turned off when reading the memory circuit (M1) and is turned on when writing.
Is connected in parallel with the tenth transfer gate (TG10).