JPH0442760B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a write signal generation circuit for a memory having a function of decompressing a write signal supplied from the outside within the memory.

Prior Art and Problems As the speed of memory increases, it is necessary to increase the speed of the write cycle, and for this purpose, the minimum write width (time) t _w of the memory must be reduced. However, there is a limit to simply increasing the speed of the writing system, and it is difficult to increase the speed beyond a certain level. To write information to memory, a write signal (Write Enable) called WE is supplied from the outside with the address fixed and the memory cell selected. However, if this pulse width is made too narrow, Writing becomes impossible.

OBJECTS OF THE INVENTION The present invention attempts to solve the above problem by stretching the pulse width of an externally applied write signal to a certain value when the pulse width is narrow.

Configuration of the Invention The present invention includes a first inverter that receives a trigger signal corresponding to an external write signal at its input end;
A second inverter is connected in series, an output end of the second inverter and an input end of the first inverter are connected by a feedback path, and a latch means is brought into a predetermined state by the trigger signal, and the input end is connected to the second inverter in series. , the first
is connected to the input end of the second inverter, the output end is connected to the input end of the second inverter via a switching element connected to the low potential side power supply, and the output end is connected to the input end of the first inverter. an internal write signal having a pulse width equal to or longer than the predetermined time; and a delay-type inverter that controls the switching element by delaying the trigger signal for a predetermined time and puts the latching means in a state different from the predetermined state. is output from the output end of the second inverter, which will be described in detail below with reference to the illustrated embodiment.

Embodiment of the Invention FIG. 1 is a block diagram showing an embodiment of the present invention, in which I ₁ and I ₂ are normal inverters and DI delay type inverters constituting a flip-flop (latch) FF. Q ₁ is an input stage MOS transistor driven by a write signal V _IN such as WE supplied from the outside, and a potential change at its drain (node A ₁ ) becomes an internal write signal. One of the loads on transistor _Q1 is flip-flop FF, which is connected to node
Quickly respond (latches) to potential changes in _A1 .
In contrast, other loads such as delayed inverters
DI is L, H corresponding to H, L change of node _A1
A predetermined delay time td is required to produce an inverted output at node _A2 . This delay time td is the width of the input V _IN
If t _w is short, it serves to internally extend it to td.

The output _A2 of the inverter DI is a flip-flop
Part of the FF loop, in this example, the path (node) from the output of inverter I ₁ to the input of inverter I ₂
MOS transistor _Q6 connected between _A3 ) and ground air
is controlled as follows. That is, while the node _A2 is at the L (low) level, the transistor _Q6 is turned off so as not to interfere with the H (high) level at the node _A3 .
This keeps the output of inverter I ₂ and therefore node A ₁ at L during td. Input V _IN is the third
As shown in the figure or FIG. 4, since the pulse is at the H level during the period _tw , the node _A1 is at the L level at least during the period _tw . This is due to transistor _Q1 being turned on. In the example of FIG. 3, t _w is narrow, so this is a column that extends it. like this example
When V _IN changes to L after _tw , node A ₁ also tries to change to H, but the potential of node A ₁ at this time is dominated by the output of inverter I ₂ because transistor Q ₁ is turned off. Since the output of this inverter _I2 is kept at L level because its input _A3 is at H level, it remains at the L level until the delay time td elapses. When the delay time td elapses, the node _A2 becomes high enough to turn on the transistor _Q6 , and the node _A3 becomes low, so that the output of the inverter _I2 and hence the level of the node _A1 becomes high. thus
In the case of t _w <td, the width t ws of the internal write signal obtained at node A ₁ is extended to td. As shown in Figure 4, when t _w > td, V _IN =H.
A ₁ is L, A ₃ is H, and the output of inverter I ₂ is L, so that A ₁ =L is maintained. Also, when A ₁ = L, the level of node A ₂ becomes sufficiently H after a delay time td, transistor Q ₆ turns on, and node A ₃ becomes L.
As a result, the output of the inverter _I2 , and hence the node _A1, tries to change from L to H, but due to V _IN , t _w
Since the transistor Q ₁ is on during the period t w , the node A ₁ is forcibly kept at L during the period t _w . Therefore, in this case, t ws = t _w (>td), that is, the output pulse width is the same as the input pulse width.

Figure 2 is a specific example of Figure 1 using C-MOS.
Q ₂ , Q ₄ , and Q ₇ are p-channel MOS transistors, and the others are n-channel MOS transistors. Transistors Q ₂ and Q ₃ constitute a delay type inverter DI.
To delay the operation of this inverter DI, it is sufficient to reduce gm of transistor _Q2 or add a capacitor to node _A2 , and the extension time of tws can be set by the delay time td (slope of node _A2 ). . Transistors Q ₄ and Q ₅ constitute inverter I ₁ , and transistors Q ₇ and Q ₈ constitute inverter I ₂ . These inverters I ₁ and I ₂ are of high-speed type in order to make the flip-flop operation steep. In this example, it is the transistor _Q7 that charges up the node _A1 to H, and conversely, it is the transistor _Q1 or _Q8 that charges up the node _A1 to L. Transistor Q ₁
is turned on for a period _tw when V _IN =H, and transistor Q ₈ is turned on for a period td when A ₃ =H. and,
Since these transistors Q ₁ and Q ₈ are connected in parallel between the node A ₁ and the ground, in the example of FIG.
ws=td>t _w , and in the example of Fig. 4, t ws
= t _w > td.

Effects of the Invention As described above, according to the present invention, when the pulse width of the write signal supplied from the outside is narrow, it is expanded internally, and when it is wide, the pulse width remains unchanged, so that the memory can operate quickly. It has the advantage of being able to handle both writing to and slow-acting memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a circuit diagram showing a specific example thereof, and FIGS. 3 and 4 are signal waveform diagrams of each part. In the figure, I ₁ and I ₂ are inverters, DI is a delay inverter, FF is a flip-flop, Q ₁ is an input stage transistor, and Q ₆ is a transistor for preventing flip-flop inversion.

Claims (1)

[Claims] 1. An input transistor whose gate receives an external write signal, whose source is connected to a low-potential power supply, and whose drain outputs a trigger signal corresponding to the write signal; a first inverter that receives a trigger signal from the drain of the input transistor; and a second inverter whose input end is connected to the output end of the first inverter, the output end of which is connected to the input end of the first inverter. and a latch means which is brought into a predetermined state by the trigger signal, and whose input end is connected to the input end of the first inverter and whose output end is connected to the low potential side power supply. and the input end of the second inverter, the trigger signal entering the input end of the first inverter is delayed for a predetermined period of time to activate the switching element. a delay-type inverter that controls the latch means to set the latch means in a state different from the predetermined state, and when the pulse width of the trigger signal is less than the predetermined time, an internal write signal having a pulse width of the predetermined time; and, when the pulse width of the trigger signal is longer than the predetermined time, an internal write signal having the same pulse width is output from the output terminal of the second inverter. generation circuit.