JPS6070592A - Writing circuit of memory - Google Patents

Abstract

PURPOSE:To expand the pulse width of a writing signal applied from the external up to a fixed value when the pulse width is narrow to write the writing signal by using potential change obtained from an output of a transistor (TR) on an input stage as an internal writing signal. CONSTITUTION:A delay type inverter DI requires a prescribed delay time td at the generation of L and H inverted outputs corresponding to H and L change of a node A1 in a node A2. The delay time td is required for the internal expansion of the width tw of an input VIN up to td when the width tw is short. When the VIN is changed to L after tw, the node A1 also tries to be changed to H. However, the potential of the node A1 is controlled by the output of an inverter I2 because a TRQ1 is turned off, so that the L level is kept until the delay time td has passed. In case of tw<td, the width tws of an internal writing signal obtained from the node A1 is expanded up to td.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a write circuit having a function of decompressing a write signal supplied from the outside within a memory.

Prior Art and Problems As memory speeds increase, it is necessary to speed up the write cycle, and to do so, the minimum write width (
time) tw must be made small. However, there is a limit to simply increasing the writing speed.
It is difficult to increase the speed beyond a certain point.

To write information to a memory, a write signal called WE (WE) is sent when the address is determined and the memory cell is selected.
Wr-4te Enable) is supplied externally,
If this pulse width is made too narrow, writing becomes impossible.

Purpose of the Invention The present invention provides a method for stretching the pulse width of a write signal applied from the outside to a certain value when the pulse width is narrow.
bing) to solve the above problem.

Structure of the Invention The present invention provides a flip-flop and a delay type inverter which are formed by connecting an input-stage transistor driven by an external write signal and two inverters controlled by the transistor in series and performing feedback. and a transistor connected between the series connection point and ground and turned on and off by the output of the delay type inverter, and a potential change obtained at the output of the transistor in the input stage is used as an internal write signal. However, this will be explained in detail below with reference to the illustrated embodiment.

Embodiment of the Invention FIG. 1 is a block diagram showing an embodiment of the invention.
I2 is a normal impark that constitutes a flip-flop (launch) FF, and DI is a delay type inverter. Ql
is an input stage MOS transistor driven by a write signal VIN such as WE supplied from the outside, and its drain (
The potential change at node A + ) becomes an internal write signal. One of the loads of transistor Q1 is flip-flop FF, which quickly responds (latches) to potential changes at node A1. On the other hand, the delay type inverter DI, which is another load, responds to H and L changes of node A1, and
A predetermined delay time td is required to generate an inverted output at node A2.
It takes. This delay time td serves to internally extend the width tw of the input VIN to td when it is short.

The output A2 of the inverter DI is a part of the loop of the flip-flop FF, in this example, the path from the output of the inverter 11 to the input of the inverter 2 (node A3) and the ground is connected to the Mo5t to transistor Q6. Control like this. That is, while the node A2 is at the L (low) level, the transistor Q6 is turned off so as not to interfere with the H (high) level at the node A3. As a result, the output of the inverter 2, and therefore the node A1, is kept at L during td.

The input vru has a period tw as shown in FIG. 3 or 4.
Since the pulse is 11 levels during the tw period, the node A1 is at the L level at least during the tw period. This is 1-
Due to turning on of transistor Q1. For example, tw in FIG. 3 is narrow, so this is an example of expanding it. As in this example VIN
When changes to L after twO, node AI also tries to change to H, but since transistor Q1 is off, the potential of node A+ at this time is dominated by the output of inverter I2, and the output of inverter I2 is Since the human power A3 is kept at the L level because it is at the H level, the L level is maintained until the delay time td elapses.

When the delay time td elapses, the node A2 becomes high enough to turn on the transistor Q8, and the node A3 becomes low, so the output of the inverter 2 and therefore the level of the node A+ becomes high.
become. In this way, in the case of tw<td, the width tws of the internal write signal obtained at node A1 is extended to td. If tw>td as shown in Fig. 4, Vr
When N=H, A1 becomes high, A3 becomes H, and the output of inverter I2 becomes L, so that A+=L is maintained. Also, when A+=L, the level of node A2 becomes high enough after the delay time td, transistor Q6 turns on and node A3 becomes low, and as a result, the output of inverter 12, and therefore node A1, changes from low to high. However, since transistor Q1 is on during twO due to VIN, node A1 is at t
The period w is forcibly kept at L. Therefore, in this case, tws=tw (>td), that is, the output pulse width is the same as the input pulse width.

FIG. 2 is a specific example of FIG. 1 using C-MOS, and Q2. Q
a, Ql are p-channel Mos transistors, and the others are n-channel MO3) transistors.

(The transistors Q2 and Q3 constitute a delay type inverter DI. To delay the operation of this inverter D1, the gm of the transistor Q2 is made small, but it is sufficient to add a capacitor to the node A2, and the delay time td (node A2 The extension time of ttvs can be set by the slope of .Transistors Q4 and Q5 connect the inverter 11 and the transistor Q?
, Q[l constitute inverter 2. These inverters I+.

I2 is a high-speed type in order to speed up the flip-flop operation. In this example, it is the transistor that charges up the node A1 to 11. 7, and conversely node A+
The transistor makes it L. 1 or QB. The transistor Ql is turned on only during the period tw when V IN = H, and is also a transistor. 8 is the period td of A 3 = H
Only turn on. And these transistors Q+, Qθ
is connected in parallel between node A1 and the earth, so the third
In the example shown in the figure, ttvs=td>tw, and in the example shown in FIG. 4, tWS-tw>td.

Achievements of the Invention As described above, according to the present invention, the width of an externally applied write signal can be expanded internally. There is an advantage that even if the width becomes narrow, a situation where writing is not possible can be avoided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example thereof, and FIGS. 3 and 4 are signal waveform diagrams of various parts. In the figure, I+ and r2 are inverters, DI is a delay type inverter, FF is a flip-flop, Ql is an input stage transistor, and A6 is a transistor for preventing flip-flop inversion. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi @ 1st day T Baboon 3rd day 1 tw A3 '1---- 2nd To I INO Figure 4, tw. = A3-"]-

Claims (1)

[Claims] an input stage transistor driven by an external write signal; a flip-flop and delay type inverter formed by connecting two inverters in series and providing feedback; and the series connection point, which is controlled by the transistor. A memory write circuit, comprising a transistor connected between the ground and turned on and off by the output of the delay type inverter, and using a potential change obtained at the output of the input stage transistor as an internal write signal. .