JPH01155590A - Dynamic random access memory - Google Patents

Abstract

PURPOSE:To simplify the connection to a sense circuit by shifting a sense circuit activating signal from a level to make the sense circuit into a non-activated state through at least three kinds of intermediate levels to a level to make the sense circuit into an activated state. CONSTITUTION:First and second conductive type MOSFETs (Q3-Q8), (Q10-Q13, Q15-Q19) to generate a sense circuit activating signal phiS1, which shifts from the level to make a sense circuit SC into the non-activated state through at least three kinds of the intermediate levels to the level to make the circuit SC into the activated state in order to shift the sense circuit SC from the non- activated state to the activated state, are provided for the title device. The sense circuit SC gradually shifts from the non-activated state to the activated state by gradually shifting the sense circuit activating signal phiS1 from the level to make the sense circuit SC into the non-activated state to the level to make the sense circuit SC into the activated state, and the wiring of the sense circuit activating signal phiS1 can be made into one. Thus, the connection to the sense circuit can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic random access memory, and particularly to a sense circuit activation signal and its generation circuit.

[Conventional technology]

FIG. 6(a) is a diagram showing a sense circuit of a conventional dynamic random access memory;
FIG. 3 is a diagram showing the timing of a sense circuit activation signal inputted thereto. Sense circuit activation signals φ, 1. shown in FIG. 6<b). φ, 2 are respectively input to transistors Q, , Q, of the sense circuit SC shown in FIG. 6(a). When the signal φ,1 moves from the low level to the old level at the timing of T+, the transistor Q is turned on, the sense amplifier is activated, and a sensing operation is started. Immediately after the start of the sensing operation, the sensed potential difference is small, so the sensing operation must proceed gradually. When the sensed potential difference becomes sufficiently large, transistor Q? Turn on to make the sense operation proceed faster. The timing at which the transistor Q2 is turned on at this time is T2.

FIG. 7(a) is a diagram showing a sense circuit activation signal generation circuit of a conventional dynamic random access memory.

Input signals SS and S S + for generating a sense circuit activation signal are provided by transistors Q, respectively. , Q6's gate electrode and transistor Q,. .

Qt, is connected to the gate electrode of Qt. A first node of transistor Q3° is connected to VCC, and transistor Q,. The 20th node of transistor Q16 is connected to the first node of transistor Q16, and the second node of transistor QIo is connected to the first node of transistor Qh and the first node of transistor Qt. Transistor Q6, Qt. The second nodes of both are connected to a reference potential. transistor Q
,. the second node of and transistors Qb, Qz.

The signal appearing at the connection point with the first node of is input to an inverting circuit, and the output of the inverting circuit is connected as the first sense circuit activation signal φs1 and as the input of a delay circuit, and the output of the delay circuit is connected as the first sense circuit activation signal φs1. is the second sense circuit activation signal φ
, 2. FIG. 7(b) shows the sense circuit activation signal φ.
, I, φ, and t are generated by the sense circuit activation signal generation signal SS. Before timing TI, sense circuit activation signal generation signal SS.

Since S S + is at Low level, the transistor Q. , Q3° are turned on, the second node of transistor Q10 becomes the old level, and sense circuit activation signal φ55. Both φ and 2 are Lo% lebel. When the sense circuit activation signal generation signal SS becomes the old level at timing T, the transistor QIO is turned off and the transistor Q is turned on.
,. The second node of is at Low level. This transistor Q. The low level of the second node of φ8. is immediately set to the old level by the inverting circuit, and the first sense circuit activation signal φ8. Output. Further, the output of the inversion circuit is inputted to a delay circuit, and outputs a second sense circuit activation signal φ,2 which becomes Hi level at timing Tt.

[Problem that the invention seeks to solve]

Since the conventional dynamic random access memory is configured as described above, the sense circuit activation signal performs the sensing operation twice, so two timings are required. There is a problem in that the connection of the signal to the sense circuit becomes complicated.

This invention was made in order to solve the above-mentioned problems, and by setting the timing of the sense circuit activation signal to one, it simplifies the connection to the sense circuit and reduces the wiring required for the connection. The purpose is to obtain a dynamic random access memory that can reduce the area.

[Means for solving problems]

In the dynamic random access memory according to the present invention, the sense circuit activation signal is made to shift from a level that deactivates the sense circuit to a level that activates the sense circuit through at least three intermediate levels.

[Effect]

In this invention, the sense circuit is gradually moved from an inactive state to an active state by the sense circuit activation signal gradually moving from a level that deactivates the sense circuit to a level that activates the sense circuit. , the number of wirings for the sense circuit activation signal can be reduced to one.

〔Example〕

An embodiment of this invention will be explained using FIG. 1.

In FIG. 1(b), φ3. is a sense circuit activation signal. The signal φ31 starts transitioning from the Low level to the old level at timing T, and reaches the old level at timing T6. 1 (al indicates a sense circuit to which this signal φ8. is input. When the signal φsI is at the low level, the transistor Q9 is off and no sensing operation is performed. When the transition from the level to the old level begins, the transistor Q9 is gradually turned on, the sense circuit SC is gradually activated, and the sensing operation progresses.
When the sensed potential difference becomes sufficient, the signal φ8. Timing T6 is programmed so that the current level is the old level.

An example of the circuit configuration for generating the timing shown in FIG. 1(b) is shown in FIG. 2(al). In this figure, the signal SS for generating the sense circuit activation signal is connected to the transistor Q,
, ,Q, are connected to each gate electrode. A first node of transistor Q16 is connected to VCC, and a second node connects the signal CLK1 to the first node of transistor Q3, which has its gate electrode connected, and to the first node of transistor Q, U. be done. The gate electrode of transistor Q13 is the second node of transistor Q13, transistor Q.

, a second node of transistor Q4 whose gate electrode is connected to signal CLK2, and a first node of transistor Q4.

The gate electrode of transistor Q4 is connected to transistor Q1.
a second node of transistor Q4, a second node of transistor Q4;
Transistor Q whose gate electrode is connected to signal CLK3
s and a first node of transistor QI5. Transistor Q1. The second node of transistor Q and the second node of transistor Q
6 first node. A second node of transistor Qh is connected to a reference potential. The second node of transistor QIo is connected to transistor Q8. The gate electrode of the transistor Q is connected to the gate electrode of the transistor Q. The first node of transistor Q, “7 is VC
C, and the second node is connected to the first node of transistor Q7.
0 node and output as sense circuit activation signals φ, I. Transistor Q? A second node of is connected to a reference potential.

FIG. 2 (bl is a timing diagram of the circuit shown in FIG. 2 (al). In this figure, SS is a sense circuit activation signal generation signal, CLKI, CLK2° CLK3 are sense circuit activation signals φ, This is a signal for specifying the timing to gradually raise the level of CLK1 from the Lo- level to the old level.Signal SS, CLK1.CLK2.CLK3
When is at Low level, signals φ and I are at Low level. When SS becomes the old level at timing T, transistor Q1 is turned off, and transistors Qb and Q
Iz, Q10. QIz turns on, transistor Ql
? , the gate potential of Qt is l Vto+*+ VTM+4
+Vt, l+s l becomes. Cocoa VT)lIff
+ ”TH14+ V't)I+s are transistors Q I 2 , Q Ia , Q t respectively
is the threshold voltage of s. At timing T, signal CL
K1 goes to the old level, transistor Q3 turns on, and transistors Ql, , Q.

The gate potential of the transistor Ql? becomes lVtH+4+VTR15l, the signal CLK2 turns on at timing T4, and the transistor Ql? , Q? The gate potential of is l Vtnts l.

Furthermore, at timing T5, the signal CLK3 becomes the old level, the transistor Qs is turned on, and the transistor QI71
The gate potential of Q7 becomes zero. The signal φS is the transistor Ql? , Q? Because it changes depending on the gate potential of
During the period from timing T to T6, three types of intermediate levels are exhibited in the process of transitioning from the Low level to the Hi level. Furthermore, by selecting the timings of T31, T41, and T5, the time from T+ to T6 can be changed.

FIG. 3 is a diagram showing another example of a circuit that generates the timing shown in FIG. 1. When the storage capacity of a dynamic random access memory increases, the power supply current flowing during reading and writing increases, and the noise generated thereby is added to the power supply voltage, narrowing the operating margin. Furthermore, power consumption and heat generation also increase. One way to solve this problem is to divide the sense circuit. This method divides a memory area into a plurality of parts by a combination of internal signals generated by address signals applied to the dynamic random access memory from the outside, and at the same time divides a memory area into a plurality of parts by a combination of internal signals. It has a circuit that generates a selection signal that does not select one area. If not divided,
The sense circuits in all memory areas operate, but in the case of a divided operation, there are memory areas that are not selected, and the sense circuits existing in those areas do not operate. Therefore, the power supply current and power consumption can be reduced by the amount of sense circuits that do not operate. FIG. 3 (al indicates the circuit configuration of the sense circuit activation signal generation circuit in the case of such a divided operation of the sense circuit, and FIG. 3 (1)) is similar to that shown in FIG.
The timing of each clock in the circuit a) is shown. Here, the stone is a selection signal for a sense circuit that performs divided operation.

Further, FIGS. 4 and 5 are diagrams showing still other examples of the sense circuit activation signal generating circuit, respectively.

The circuit of FIG. 4 is based on the transistor Q1 shown in FIG. 3(a).
A capacitor C is provided at the gate of signal φ, 1 to make the waveform of signal φ, 1 smoother.

〔Effect of the invention〕

As described above, according to the dynamic random access memory of the present invention, the sense circuit activation signal for transitioning the sense circuit 11 from active to active has at least three intermediate levels. Only one type of signal is required, and the connection to the sense circuit can be simplified, and the area required for the wiring can be reduced.

[Brief explanation of the drawing]

FIG. 1(a) is a diagram showing a sense circuit of a dynamic random access memory according to an embodiment of the present invention, FIG. 1('b) is a timing diagram of a sense circuit activation signal according to an embodiment of the present invention, and FIG. Figure 2 (a) is a diagram showing an example of a circuit for realizing the sense circuit activation signal, Figure 2 (b) is a timing diagram of each clock, and Figure 3 (al.
is a diagram showing an example of a circuit for realizing the sense circuit activation signal of FIG. 1(b) when performing a sense circuit division operation, FIG. 3(b) is a timing diagram of each clock, and FIG.
5 and 5 are diagrams showing other examples for realizing the sense circuit activation signal shown in FIG. FIG. 6(b) is a timing diagram of a conventional sense circuit activation signal, FIG. 7(a) is a diagram showing a conventional generation circuit of a sense circuit activation signal, and FIG. 7(b) is a timing diagram thereof. be. Q3 to Q are first conductivity type MOS FETs, Q,
, Q, , Q, s, Q, 7 to Ql are second conductivity type MOSFETs, SS is a signal for generating a sense circuit activation signal, φ31 is a sense circuit activation signal,
B is the sense circuit selection signal, CLKl. CLK2. CLK3 is a control signal for a sense circuit activation signal, T is a sensing start time, and T3. T, , T, are signals CLKI, CLK2 . When CLK3 becomes the old level, Tb is the time when the sense activation signal becomes the old level. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (7)

[Claims] (1) A sense circuit activation signal that generates a sense circuit activation signal that transitions from an inactive level to an active level through at least three intermediate levels in order to transition the sense circuit from inactive to active. A dynamic random access memory characterized by comprising a generation circuit. (2) The dynamic random access memory according to claim 1, further comprising a circuit that controls the transition time of the level of the sense circuit activation signal based on timing. (3) The sense circuit activation signal generation circuit includes first and second MOSFETs of first and second conductivity types whose sources are respectively connected to second and first potentials and whose gates receive the first control signal.
ET and third, fourth, and fifth MOSFETs of the first conductivity type that are connected in series between the drains of the first and second MOSFETs and receive second, third, and fourth control signals at their gates, respectively.
and sixth, seventh, and eighth MOSFETs of the second conductivity type, which are connected in series between the drains of the first and second MOSFETs and whose gates and drains are connected, and the second and first potentials are connected in series between the second and first potentials. 9th and 10th MMOSFETs of the first and second conductivity types connected to each other and whose gates are connected to the drain of the second MOSFET;
OSFET, and the ninth and tenth MOSFETs mentioned above.
3. The dynamic random access memory according to claim 2, wherein the output is the connection point of the dynamic random access memory. (4) The sense circuit activation signal generation circuit has a memory array divided into a plurality of parts, and the sense circuit activation signal generation circuit performs a memory array division operation of activating only a part of the divided memory array during one memory cycle. 3. The dynamic random access memory according to claim 2, characterized in that the dynamic random access memory is equipped with a circuit that enables the dynamic random access memory. (5) The sense circuit activation signal generation circuit includes first and second MOSFETs of first and second conductivity types whose sources are respectively connected to second and first potentials and whose gates receive the first control signal.
ET and third, fourth, and fifth MOSFETs of the first conductivity type that are connected in series between the drains of the first and second MOSFETs and receive second, third, and fourth control signals at their gates, respectively.
and sixth, seventh, and eighth MOSFETs of the second conductivity type, which are connected in series between the drains of the first and second MOSFETs, and whose gates and drains are connected, and whose sources are at the second and first potentials, respectively. a ninth one of first and second conductivity types connected to the gate and receiving the first control signal via an inverting circuit;
a first MOSFET whose source is connected to the second potential and the drain of the tenth MOSFET, and whose gate receives the fifth control signal for the division operation;
, the eleventh and twelfth M〇SFETs of the second conductivity type, the drains of the ninth and eleventh MOSFETs, and the twelfth MOS
The gate is connected between the drains of the FETs and the second MOS
13th MO of the second conductivity type connected to the drain of the FET
5. The dynamic random access memory according to claim 4, wherein the dynamic random access memory is composed of a SFET and has an output at a connection point between the ninth and tenth MOSFETs and the thirteenth MOSFET. (6) The dynamic random access memory according to claim 5, characterized in that a capacitor is added to the drain of the second MOSFET. (7) The sense circuit activation signal generating circuit has first and second conductivity type first circuits having sources connected to second and first potentials respectively and receiving a first control signal through an inverting circuit at gates. , third and fourth MOSFETs of a second conductivity type connected in series between the second MOSFET and the drains of the first and second MOSFETs and receiving second, third and fourth control signals at their gates via inverting circuits, respectively. , a fifth MOSFET, and the first and second MOSFETs.
6th, 7th, and 8th MOSFETs of the first conductivity type connected in series between the drains of the MOSFETs and having their gates and drains connected;
SFET, and ninth and tenth MOSFETs of first and second conductivity types whose sources are connected to the second and first potentials, respectively, and whose gates receive the first control signal via an inversion circuit.
and the source is at the second potential and the tenth MO
first and second conductivity type first transistors connected to the drains of the SFETs and having gates receiving a fifth control signal for the dividing operation;
1. The 12th MOSFET, and the 9th and 11th MOSFET
a 13th MOSFET of a first conductivity type connected between the drain of the ET and the drain of the 12th MOSFET, the gate of which is connected to the drain of the 1st MOSFET;
5. The dynamic random access memory according to claim 4, wherein the connection point with the dynamic random access memory is an output.