JP3211692B2 - Amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, that is, a semiconductor integrated circuit in which memory cells are integrated. More specifically, the present invention relates to a method for transmitting a pair of complementary signals having a small potential difference read from a memory cell at a high speed and a large amplification factor. The present invention relates to a sense amplifier circuit technology for amplifying.

[0002]

2. Description of the Related Art An example of a conventional sense circuit for amplifying a read signal from a memory cell is disclosed in Japanese Unexamined Patent Publication No.
No. 8734, as shown in FIG. 3, the complementary pair input signals d and .DELTA.d are connected to the gates and drains of the two drive MOS transistors Q13 and Q14 of the sense amplifier circuit, and the two drive signals are connected. MOSQ13,
The drains of Q14 are complementary pair output signals D,.
It has become.

US Pat. No. 4,335,449 discloses two load MOS transistors Q2 as shown in FIG.
1 and Q22 are connected to each other, and the driving transistor Q
Bipolar transistors are used for 23 and Q24, and complementary paired input signals d and ￣d are connected to bases of two driving bipolar transistors Q23 and Q24.

[0004] Other conventional sense circuits include Japanese Patent Application Laid-Open No. 62-46489 and US Pat.
No. 7,791 and the like.

[0005]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No. 52-87.
No. 34 (see FIG. 3) is that the complementary pair input signals d and .DELTA.d are connected to both the gates and drains of the driving MOSs Q13 and Q14 in the sense amplifier circuit, and the input signal lines d and .DELTA.d Since the signal lines D and ￣D are directly connected, when the load capacitance of the output signal lines D and ￣D is very large, amplification cannot be performed at high speed, and because of the positive feedback operation, there is a complementarity. It has been clarified by the study of the present inventor that it has a disadvantage that the inversion of the paired input and output signals is slow.

US Pat. No. 4,335,449 (see FIG. 4) discloses bipolar transistors Q23 and Q2.
4 is used to drive the load capacitance of the output signal line.
When the potential difference between the complementary pair input signals d and ￣d is small, the bipolar transistor Q23,
The operating current of Q24 is cross-connected, and the operating current of load MOS transistors Q23, Q24 responds to a weak and weak input signal with respect to the positive feedback holding current flowing through the cross-connected load MOS transistors Q21, Q22. Bipolar transistors Q23 and Q24 and load MO
It has been clarified by the study of the present inventor that the S-transistors Q21 and Q22 cannot be inverted and have a disadvantage that high-speed sensing operation for a minute input signal is difficult.

Accordingly, it is an object of the present invention to provide a sense amplifier circuit capable of operating at high speed, overcoming the above-mentioned disadvantages of the prior art.

[0008]

As described above, in order to enable a high-speed sensing operation for a minute input signal read from a memory cell, a gate and a drain are connected to a load MOS transistor having a cross-coupled connection. Connecting the first switching means between the complementary outputs of the paired transistors, and turning on the first switching means by the first control signal when the pair of transistors is inverted in response to the read signal; The first switching means is controlled to be in a non-conductive state.

On the other hand, as described above, in order to drive the output signal line of the sense amplifier having a very large load capacitance at high speed, the preamplifier has a circuit type in which the input signal line and the output signal line are directly connected. The preamplifier and the sense amplifier are controlled to an active state in order to start signal reading from the memory cell, the complementary signal read from the memory cell is amplified by the preamplifier, and the complementary amplified output signal of the preamplifier is further amplified. Amplify by the subsequent sense amplifier, and configure a multi-stage amplifier circuit configuration to drive the heavy load capacitance of the output signal line of the sense amplifier by the complementary output signal of this sense amplifier, and at the time when the amplification operation of the subsequent sense amplifier is almost completed (After a lapse of a predetermined time from the start of signal reading from the memory cell), the preamplifier in the preceding stage is controlled to the inactive state, and the sense in the subsequent stage is controlled. It is to maintain the width unit active.

[0010]

When the first switching means is turned on by the first control signal, the cross-coupled load MOS is connected.
Since the positive feedback holding operation of the transistor is eliminated, the pair of transistors can perform a high-speed inversion operation in response to a minute input signal.

On the other hand, since the preamplifier in the preceding stage is controlled to be inactive at the time when the amplification operation of the subsequent sense amplifier is almost completed, the potential difference between the complementary input / output of the preamplifier, that is, the complementary input of the sense amplifier, becomes larger than necessary. And the next inverted reading can be executed at high speed. Further, even when the preamplifier is controlled to be inactive, the signal read from the memory cell is controlled to be active via a direct connection path between the input signal line and the output signal line of the inactive preamplifier. Since the signal is transmitted to and amplified by the input of the sense amplifier, the loss of the amplified output of the sense amplifier can be avoided.

[0012]

An embodiment of the present invention will be described below with reference to FIG. Q1, Q2, Q6 and Q8 are p-channel MOS transistors (hereinafter referred to as pMOS), Q3, Q4 and Q5.
Q7 and Q9 are n-channel MOS transistors (hereinafter referred to as nM
OS, and d and ￣d are a pair of complementary signals input to the sense circuit of the present embodiment, a complementary read signal from the memory cell is transmitted, and D and D￣ are a pair of complementary signals output from the sense circuit.相 補 φ1, φ1, ￣φ2, φ2
Is a pulse signal for driving the transistors Q6, Q7, Q8 and Q9, respectively, and SAC applied to the gate terminal of the NMOS Q5 is an activation signal of the present sense amplifier. The timing of these signals is shown in FIG. , PMOS
Q1 and Q2 are cross-coupled load MOSs, N
MOS Q3 and Q4 operate as differential transistors, and PMOS Q8 and NMOS Q9 operate as first switching means.
The pulse signals φ2 and Δφ2 are first control signals.

The operating transistors Q3 and Q4 are npn
It can be replaced by a bipolar transistor. In addition, only one of the transistors Q6 and Q7 may be used, and only one of the transistors Q8 and Q9 can operate.

D and .DELTA.d are a pair of complementary input signals of a sense amplifier having a small potential difference read out from the static memory cell.
The complementary input signal potential difference reducing MOS transistors Q6 and Q7 are turned on by φ1, and d and ￣d are set to the same potential, so that inversion reading is speeded up. Subsequently, the pulse signal ￣φ
2 and φ2, the complementary output signal potential difference reducing MOS transistors Q8 and Q9 are turned on, the complementary output signals D and .DELTA.D are set to the same potential, and the positive feedback of the cross-coupled load MOS transistors Q1 and Q2 is maintained. Since the operation is weakened, the speed of the inversion reading is increased. Next, at the same time when a pair of complementary signals starts to be read out from the memory cell to d and ￣d, Q6 and Q7 are turned off, and d and ￣d are turned off.
The potential difference between d spreads. Subsequently, Q8 and Q9 are also turned off.

Now, let us consider a time point when the transition from time t1 to t2 is made on the time axis of the timing chart of FIG. At this time, the potential of d decreases and the potential of Δd increases, but the nodes N1 and N2 are still at the same potential. Therefore, the drain current of Q3 decreases, the drain current of Q4 increases,
Thereafter, the potential of the node N1 rises and the potential of the node N2 starts to fall. Therefore, the drain current of Q1 increases and Q1
2, the potential of the node N1 rises and the potential of the node N2 falls. This is Q
1 increases the drain current of Q2, decreases the drain current of Q2, and acts in the direction of increasing the potential of node N1 and decreasing the potential of node N2. That is, positive feedback is applied to the nodes N1 and N2 of the present sense amplifier, which has the effect of rapidly expanding the potential difference, and an extremely high-speed sense amplifier can be realized.

That is, the differential transistors Q3 and Q4 respond to the complementary input signals d and .SIGMA.d, and the load MOS
The transistors Q1 and Q2 are connected to the differential transistors Q3 and Q3.
In response to Q4, the complementary output complementary outputs D and ΔD having a large load capacity can be charged or discharged at high speed.

In this sense amplifier, Q6, Q7, Q
8. Q9 plays a very important role. That is, between complementary input signals d and ￣d and complementary output signals D and ￣D
Is short-circuited during the signal transition period, and serves to promptly perform the signal transition. The timings of d, お よ び d and D, ￣D when Q6, Q7, Q8, and Q9 are not used are shown by broken lines in FIG. At this time, the positive feedback circuit of the load MOS transistors Q1 and Q2 prevents the transition of the complementary output signals D and ￣D, and the transition of D and 生 じ る D occurs only at time t3 when the complementary input signal potential difference increases. That is, the sensing speed is significantly reduced. Alternatively, when the maximum potential difference between the complementary input signals d and .DELTA.d is small, the transition of the complementary output signals D and .DELTA.D may not occur, that is, correct data may not be read.

As described above, according to this embodiment, there is an effect that a pair of complementary input signals having a minute potential difference are amplified at a very high speed and a large amplification factor.

FIG. 5 shows another embodiment of the present invention. The embodiment of FIG. 5 has a configuration in which the roles of the pMOS and the nMOS are switched in the first embodiment (FIG. 1).
In the same manner as described above, there is an effect of amplifying at a very high speed and a large amplification rate.

In this embodiment, the MOS transistor Q
36 and Q37 may be either one, and Q38 and Q39
A desired operation can be performed in either one of them.

FIG. 6 is another embodiment of the present invention.
FIG. 6 shows a configuration in which the circuit of FIG. 1 is cascaded in two stages. By cascading the circuits in two stages, the amplification factor can be further increased, and the potential difference between the complementary output signals D and ΔD is expanded to the full power supply voltage. Can be. In the circuit of FIG. 6, the size of the transistors Q46 to Q50 in the second stage sense amplifier section is increased to cooperate the load driving capability. When a large load capacitance is connected to D and ΔD, the load capacitance is reduced. It can be driven at high speed.

FIG. 7 shows another embodiment of the present invention. The circuit shown in FIG. 7 employs well-known NMOS differential Q43 and Q43.
In this configuration, the first stage is a sense amplifier composed of 44, Q43 ', Q44' and PMOS current mirrors Q41, Q42, Q41 ', Q42', and the circuit of FIG. 1 is cascaded as a second stage sense amplifier.

The present invention relates to a so-called double-ended sense amplifier which outputs complementary outputs D and ΔD. When a current mirror load is used, two current mirror load circuits are required to obtain a complementary output. Although the first-stage current mirror load circuit type sense amplifier of FIG. 7 is fast, it is not as fast as the second-stage cross-coupled load circuit type sense amplifier of FIG. In addition, there is a disadvantage that the number of transistors in the first stage is nine while the number of transistors in the second stage is five.

However, in FIG. 7, the following advantages are obtained by using a current mirror load circuit type sense amplifier in the first stage.

That is, in order to increase the speed of the memory device, it is necessary to reduce the delay TD from the time when the word line drive signal for selecting the word line of the memory device is applied to the time when the signal is output from the sense amplifier. is important. on the other hand,
The MOS transistors Q51, Q52, Q53, Q54, Q55, Q5
6, there is a delay TE up to the end of the operation of reducing the potential difference between the complementary signal lines due to non-conduction.

The horizontal axis of FIG. 21 shows the latter delay TE, and the vertical axis shows the former delay TD. In FIG. 21, the practice shows the characteristics of the embodiment of FIG. 7, and the broken line shows the implementation of FIG. The characteristics of the example are shown.

In any of the characteristics, if the delay TE from the application of the word line drive signal to the end of the operation of reducing the potential difference between the complementary signal lines is too short, the differential transistor or the load transistor in the sense amplifier is not provided. While the amplitude of the complementary input signal of the first stage of the sense amplifier is small due to the difference in electrical characteristics such as the threshold voltage of the paired transistors, the differential transistor of the first stage of the sense amplifier Erroneous information is temporarily output from the complementary output of the first stage, and a delay occurs in obtaining correct information from the complementary output of the first-stage differential transistor. This delay predominantly determines the delay TD from the application of the word line drive signal to the output from the sense amplifier.

Since the amplification factor of the positive feedback load of the first stage of the sense amplifier of the embodiment of FIG. 6 is large, erroneous information is output from the output of the first stage with a large amplitude. On the other hand, since the amplification factor of the first stage current mirror load of the sense amplifier of the embodiment of FIG. 7 is smaller than the amplification factor of the positive feedback load of FIG. 6, the first stage of the sense amplifier of the embodiment of FIG. The amplitude of the erroneous information resulting from the output of the stage becomes small,
The delay TD in FIG. 7 is small.

As described above, in comparison with the embodiment of FIG.
In this embodiment, since the amplification factor of the load circuit is small, the delay TD related to the output of the sense amplifier does not increase so much even if the delay TE related to the end of the potential difference reducing operation is reduced.

Therefore, according to the embodiment of FIG. 7, the minimum value of the delay TE related to the end of the potential difference reducing operation can be reduced by 1.3 ns as compared with the embodiment of FIG.
The timing margin for the delay time TE can be increased.

FIG. 8 shows another embodiment of the present invention. The circuit of FIG. 8 has a configuration in which a differential amplifier having PMOSs Q41 and Q42 whose gates are applied with a fixed voltage such as a ground voltage as a load is the first stage, and the circuit of FIG. 1 is cascaded as a second stage sense amplifier. I have.

7 and 8, the large load capacitance of the data buses D and .DELTA.D can be driven at high speed by the second stage positive feedback type sense amplifier.

The circuit shown in FIG. 9 is a known sense circuit.
Two amplifiers with two current mirror type amplifiers connected in parallel
It is configured to be connected vertically.

FIG. 10 is a graph showing the delay time of the sense circuit of FIG. 6 as an embodiment of the present invention and the sense circuit of FIG. 9 as a conventional example with respect to the average current of the sense amplifier.
From FIG. 10, the sense circuit of FIG. 6, which is an embodiment of the present invention, is a conventional example. It is clear that the sense circuit has twice or more the speed of the sense circuit of FIG.

FIG. 11 shows another embodiment of the present invention, in which a static random access memory (SRA) is used.
M). In FIG. 11, the sense amplifier circuit of FIG. 6 is used as SA for amplifying a read signal from the SRAM cell, and as MA, tri-state output control PMOS transistors Q71 and Q72 are added to the sense amplifier circuit of FIG. It is an amplifier circuit.

FIG. 12 shows an example of an integrated circuit which was examined by the present inventors before filing the application. In the embodiment shown in FIG. 11, the number of transistors is greatly reduced as compared with FIG. The area is almost half.

In addition, the use of the circuit of FIG. 11 makes it possible to greatly increase the speed, and the time required for the memory cell information to reach Dout is reduced to about half that of the case of using the circuit of FIG. Has been confirmed by circuit analysis.

This is because in the circuit of FIG.
While the S-transistor is connected in a current mirror, the gain of the load MOS is small. On the other hand, in the circuit of FIG. 11, the load PMOS transistor is connected in a positive feedback cross-coupling, so that the gain of the load MOS is large. ing.

FIG. 13 shows operation waveforms by circuit analysis when the sense circuit of FIG. 11 is applied to a 1-Mbit SRAM. In FIG. 13, the minute potential difference between the common data lines d and #d is amplified at high speed by the first and second stage sense amplifiers (SA in FIG. 11), and the CMOS level signals S2 and S2 are amplified.
￣S2 is obtained. Signals S2 and .DELTA.S2 propagate through a data bus having a large wiring capacitance, and then propagate to main amplifier (FIG.
1A) (FIG. 13D,
￣D), but as soon as a small potential difference is generated between D and で D, the signals are amplified by the main amplifier to obtain high-speed main amplifier output signals D1 and ￣D1.
Output transistors Q75 and Q76 are driven via INV2. As described above, according to the circuit configuration of FIG. 11, the operations of the first and second stages of the sense amplifier and the operation of the main amplifier are one step.
This can be performed with a delay of about ns, and the output Dout can be obtained at a very high speed. In the example of FIG. 13, an output Dout is obtained for about 3 ns after a potential difference starts to be generated between the common data lines d and Δd.

Further, in FIG. 12, the output terminal Dou is provided after the main amplifier MA in response to the data output control signal DOC.
In contrast to the output control circuit DB for determining the high impedance state of t, in the embodiment of FIG. 11, the NMO controlled by the data output control signal DOC is used.
While the active state or the inactive state of the main amplifier MA is controlled by the S transistor Q70, the output terminal Dout
12 are connected in parallel to the output of the main amplifier MA and controlled by DOC, a circuit corresponding to the output control circuit DB in FIG. Signal transmission time can be reduced.

FIG. 14 shows another embodiment of the present invention, in which the sense amplifier SA of the first and second stages is constituted by using the sense circuit shown in FIG.

FIG. 15 shows another embodiment of the present invention, in which the sense amplifier SA of the first and second stages is constituted by using the sense circuit shown in FIG.

FIG. 16 shows another embodiment (sense circuit of a static RAM) of the present invention. In the embodiment of FIG. 11, a CMOS positive feedback preamplifier circuit PFB1 (Q204, Q205, Q205) is connected to the common data lines d and #d. Q225-
Q228) is added. FIG. 17 shows FIG.
FIG. 17 is a waveform chart showing the operation of the sixth embodiment, and FIG. 16 will be described below with reference to FIG. The potential difference read from the static RAM memory cell and transmitted to the common data lines d and ￣d is usually about 0.1 to 0.2 V, and how to amplify this minute potential difference at high speed is the key to speeding up. . d, ￣
A pulse is applied to φCDQ and ΔφCDQ for the signal transition feedback of d, and the MOS transistors Q202 and Q203 are temporarily made conductive, so that the signal transition of d and Δd is performed promptly. Next, the signal potential difference due to the newly selected memory cell starts to occur at d and Δd, and at the same time, the pulse φCDA,
The MOS transistors Q204, Q20
5 is turned on to operate the CMOS positive feedback preamplifier circuit PFB1 in which the input signal line and the output signal line are directly connected. PFB1 positively amplifies the potential difference between d and ￣d,
A maximum potential difference of about 0.5 V is obtained (ΔV1). PFB1
The effect of (1) is to quickly and stably operate the next-stage sense circuit by rapidly increasing the potential difference between d and Δd. After the end of the sensing operation in the subsequent stages, Q204 and Q
205 is made nonconductive by φCDA and ￣φCDA,
FB1 does not operate, and the signal read from the SRAM memory cell via the Y-direction switch MOS transistor is C
Without being amplified by the MOS positive feedback preamplifier circuit PFB1, the signal is transmitted to the common data lines d and ￣d via a direct connection between the input signal and the output signal line of the preamplifier circuit PFB1. Thus, d, ￣
The potential difference of d gradually changes to a steady state potential difference ΔV2 (0.1 to 0.2 V) without becoming unnecessarily large.
In other words, the potential difference between the common data lines d and ￣d is not too large, so that reading of the next memory cell information is not delayed. Sense amplifier first stage (SA1) output S1, ￣S1
Causes MOS transistors Q206 and Q207 to pulse φS
From EQ1 and ￣φSEQ1, the second stage of the sense amplifier (SA
2) Outputs S2 and .DELTA.S2 are MOS transistors Q208,
The signal Q209 is made to conduct signal transition feedback by the pulses φSEQ2 and ΔφSEQ2, and the signal transition is also quickly performed. Thereafter, a potential difference is generated between the common data lines d and ￣d, and at the same time Q206, Q207, Q208 and Q209 are generated.
Are turned off, the sense amplifiers SA1 and SA2 are operated by the control signal Y · SAC, and the PMOS
The signal S1, amplified at a very high speed by the positive feedback operation
￣S1 and S2, ￣S2 are obtained.

MOS transistors Q212, Q213 and Q21 forming a transfer gate connecting the outputs S2 and # S2 of the second stage of the sense amplifier to the data buses D and #D.
4, Q215 are turned on before a signal is output to S2, .DELTA.S2.
Q211, Q216 and Q217 are pulsed φSEQ2, ￣
Signal transition feedback is made conductive by φSEQ2, φBEQ, ￣φBEQ, causing a potential difference between S2, ￣S2 and Q
210, Q211, Q216, and Q217 are turned off. The signal S2 amplified by the second-stage sense amplifier SA2,
￣S2 becomes a waveform (FIG. 17D, ￣D) that becomes gentle while propagating through the data bus having a large load capacitance.

During the signal transition period, the main amplifier outputs M and .DELTA.M cause the MOS transistor Q218 to become non-conductive, the Q219 and Q220 to become conductive by the control signal DOC, and the MOS transistors Q219 and Q220 to become conductive according to the .phi.MAEQ and .phi..phi.MAEQ signals.
By turning on the transistors Q221 and Q222, the potentials of M and ΔM are temporarily set to the power supply voltage VCC potential. Therefore, during this period, both the output NMOS transistors Q223 and Q224 are turned off, and the output signal Dout changes from "0" to "1" or from "1" to "0".
Output transistors Q223 and Q224 during the transition to
There is no current flowing therethrough, and low power consumption and low noise operation can be performed. Next, before the potential difference occurs between D and ΔD, Q218 is turned on by the DOC signal,
19, Q220 are made non-conductive, and subsequently, a potential difference is generated between D and と 同時 に D, and at the same time Q221 and Q222 are made non-conductive, the signal waveforms M and ￣M which are amplified at high speed by the main amplifier MA1 are obtained. These signals are output from inverter I
Output transistors Q223 and Q3 via NV1 and INV2
224 is driven to obtain an output Dout.

As described above, the output waveform Dout can be obtained at a very high speed by sequentially amplifying the minute potential difference between the common data lines d and Δd at a high speed.

As another embodiment of the present invention, a circuit configuration using FIG. 7, FIG. 8, or FIG. 9 as the first-stage and second-stage sense circuit portions SA in FIG. 16 is also conceivable. An output can be obtained at a higher speed than the same operation as described above.

FIG. 18 shows another embodiment of the present invention. FIG.
8 has a configuration in which a PMOS positive feedback circuit PFB2 is added to the embodiment of FIG. The effect of the PFB2 is that the potential difference between the pair of bit lines b and Δb is increased at a high speed, the potential difference between the common data lines d and Δd is increased more rapidly than in the embodiment of FIG. 16, and the operation of the sense amplifier SA is further accelerated. Thus, it has made possible even faster amplification.

As another embodiment of the present invention, a circuit configuration using FIG. 7, FIG. 8, or FIG. 9 as the first-stage and second-stage sense circuit portions SA in FIG. 18 is also conceivable. As in the case of 18, high-speed sense amplification can be realized.

FIG. 19 shows another embodiment of the present invention, in which Q301, Q308, Q310, Q311, Q31
Reference numeral 5 denotes a P-channel MOS transistor.
Q303, Q304, Q305, Q306, Q307,
Q309, Q312, Q313, Q314, and Q316 represent N-channel MOS transistors.

In the circuit of FIG. 19, two types of sense amplifiers are cascaded, and the first-stage sense amplifiers are Q303, Q304, Q305, Q306, and Q3.
07, all of which are constituted by N-channel MOS transistors, Q310, Q311, Q312, Q313, Q3
The sense amplifier of FIG.
Used as a stage sense amplifier.

MOS transistors Q301 and Q302 are connected between complementary lines d and.
308 and Q309 are connected between complementary lines D1 and $ D1, and MOS transistors Q315 and Q316 are connected between complementary lines D and $ D.

In response to the input signals of the complementary lines d and .DELTA.d, the complementary signals D1 and .DELTA.D1 form a pair of the source follower operation N
After being obtained by channel MOS transistors Q303 and Q304, N-channel MOS transistors Q305 and Q305 whose gate and drain are cross-coupled are further connected.
It is amplified at high speed by Q306.

The complementary signals D1,... D1 increase the size of the transistors Q310, Q311, Q312, Q313, and Q314 to strengthen the load driving capability.
Even when a large load capacitance is connected to D, this load capacitance can be driven at high speed.

FIG. 20 also shows another embodiment of the present invention, in which Q401, Q403, Q404, Q405, Q40
6, Q407, Q408, Q410, Q411, Q41
Reference numeral 5 denotes a P-channel MOS transistor;
Q409, Q412, Q413, Q414 and Q416 represent N-channel MOS transistors.

In the circuit of FIG. 20, two types of sense amplifiers are cascaded, and the first-stage sense amplifiers are Q403, Q404, Q405, Q406, and Q4.
07, all of which are P-channel MOS transistors, and Q410, Q411, Q412, Q413, Q4
The sense amplifier of FIG.
Used as a stage sense amplifier. MOS transistors Q401 and Q402 are connected between complementary lines d and #d, MOS transistors Q408 and Q409 are connected between complementary lines D1 and # D1, and MOS transistor Q
415 and Q416 are connected between the complementary lines D and #D.

In response to the input signals of the complementary lines d and #d, the complementary signals D1 and # D1 form a pair in the source follower operation P
After being obtained by channel MOS transistors Q403 and Q404, P-channel MOS transistors Q405 and Q405 whose gates and drains are cross-coupled are further connected.
It is amplified at high speed by Q406.

The complementary signals D1,... D1 increase the size of transistors Q410, Q411, Q412, Q413, and Q414 to cooperate with the load driving capability.
Even when a large load capacitance is connected to D, this load capacitance can be driven at high speed.

As described above, the first-stage N-channel MOS transistors Q303 and Q304 of the sense amplifier in the embodiment of FIG. 19 and the first-stage P-channel of the sense amplifier in the embodiment of FIG. MOS transistors Q403 and Q404 each operate as a source follower having a voltage gain of 1 or less, and N-channel MOS transistors Q305 and Q305 in which the gate and drain of the first stage of the sense amplifier in the embodiment of FIG. 19 are cross-coupled.
P-channel MOS transistors Q405 and Q406 in which the gate and the drain of the first stage of the sense amplifier in the embodiment of FIG. 306 and FIG. 20 are cross-coupled operate as a source load circuit of the source follower. The voltage gain of the circuit is much greater than one.

In the embodiment shown in FIGS. 19 and 20,
As in the previous embodiment, the MOS transistors Q308, Q309, Q408,
The conduction of Q409 causes the cross-coupled load MOS transistors Q305, Q306, Q
The positive feedback operation of 405 and Q406 is eliminated.

The present invention is not limited to SRAMs, but can be applied to all types of memory devices such as DRAMs, PROMs, and EPROMs.

Further, the present invention is not limited to the above-described specific embodiments, and it goes without saying that various modifications can be made in accordance with the basic technical concept.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart suitable for operating the circuit of FIG. 1;

FIG. 3 is a circuit diagram showing a conventional technique.

FIG. 4 is a circuit diagram showing a conventional technique.

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

FIG. 6 is a circuit diagram showing another embodiment of the present invention.

FIG. 7 is a circuit diagram showing another embodiment of the present invention.

FIG. 8 is a circuit diagram showing another embodiment of the present invention.

FIG. 9 is a circuit diagram showing a conventional sense circuit.

FIG. 10 is a characteristic diagram showing the average current dependence of the delay time required for the sense amplification of the embodiment of the present invention (FIG. 6) and the conventional sense circuit example (FIG. 9).

FIG. 11 is a circuit diagram showing another embodiment of the present invention.

FIG. 12 is a circuit diagram showing a circuit examined by the present inventors before filing the application.

FIG. 13 is an operation waveform diagram of the embodiment in FIG. 11;

FIG. 14 is a circuit diagram showing another embodiment of the present invention.

FIG. 15 is a circuit diagram showing another embodiment of the present invention.

FIG. 16 is a circuit diagram showing another embodiment of the present invention.

FIG. 17 is an operation waveform diagram for explaining the operation of the embodiment in FIG. 16;

FIG. 18 is a circuit diagram showing another embodiment of the present invention.

FIG. 19 is a circuit diagram showing another embodiment of the present invention.

FIG. 20 is a circuit diagram showing another embodiment of the present invention.

FIG. 21 is a diagram showing a difference in characteristics between the embodiment of FIG. 6 and the embodiment of FIG. 7;

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Shoji Hanamura 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-1-290191 (JP, A) JP-A-64 −67795 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 11/419

Claims (59)

(57) [Claims] A first and a second input line, a first and a second output line, and a first and a second current line, each having the first and the second input line connected to its two inputs. A mirror load type sense amplifier, a first intermediate line connected to the output of the first current mirror load type sense amplifier, and a second intermediate line connected to the output of the second current mirror load type sense amplifier. A first MOS transistor whose gate is connected to the first intermediate line; a second MOS transistor whose gate is connected to the second intermediate line and whose source is connected to the source of the first MOS transistor; A third MOS transistor having a drain connected to the first output line and a source / drain path connected in series to a source / drain path of the first MOS transistor; Its drain is connected to the second output line and the gate of the third MOS transistor, its source / drain path is connected in series to the source / drain path of the second MOS transistor, and its gate is connected to the drain of the third MOS transistor. An amplifier circuit comprising: a connected fourth MOS transistor. 2. The amplifier circuit according to claim 1, further comprising a first switch circuit connected between a source of said first MOS transistor and a first operating potential point. 3. The amplifier circuit according to claim 2, further comprising a second switch circuit connected between said first output line and said second output line. 4. The amplifier circuit according to claim 3, wherein a period during which said first switch circuit is conductive and a period during which said second switch circuit is conductive overlap. 5. The method according to claim 3, wherein the second switch circuit is changed from the conductive state to the non-conductive state after the first switch circuit is changed from the non-conductive state to the conductive state.
Or the amplifier circuit according to any one of 4. 6. The semiconductor device according to claim 5, wherein said second switch circuit is changed from a non-conductive state to a conductive state after said first switch circuit is changed from a non-conductive state to a conductive state.
An amplifier circuit as described. 7. A semiconductor device further comprising a third switch circuit connected between the first intermediate line and the second intermediate line, wherein the first switch circuit is switched from a non-conductive state to a conductive state. 7. The amplifier circuit according to claim 3, wherein said third switch circuit is changed from a conductive state to a non-conductive state. 8. The method according to claim 7, wherein the third switch circuit is changed from the non-conductive state to the conductive state after the first switch circuit is changed from the non-conductive state to the conductive state.
An amplifier circuit as described. 9. The amplifier circuit according to claim 7, wherein said third switch circuit includes at least one of an N-channel fifth MOS transistor and a P-channel sixth MOS transistor. . 10. The amplifier circuit according to claim 1, wherein said first and second MOS transistors are N-channel type, and said third and fourth MOS transistors are P-channel type. . 11. The amplifier circuit according to claim 2, wherein said first switch circuit comprises an N-channel seventh MOS transistor. 12. The amplifier circuit according to claim 1, wherein said first and second MOS transistors are of a P-channel type, and said third and fourth MOS transistors are of an N-channel type. . 13. The amplifying circuit according to claim 2, wherein said first switch circuit comprises a P-channel type seventh MOS transistor. 14. The second switch circuit comprises an N-channel type eighth MOS transistor and a P-channel type ninth MOS transistor.
10. The amplifier circuit according to claim 3, comprising at least one of transistors. 15. The source of said third MOS transistor.
The drain path is connected in series to the source / drain path of the first MOS transistor between a first operating potential point and a second operating potential point, and the source / drain path of the fourth MOS transistor is connected to the first operating potential point. 15. The amplifier circuit according to claim 1, wherein the amplifier circuit is connected in series to a source / drain path of the second MOS transistor between the second MOS transistor and the second operating potential point. 16. A first current mirror load type sense amplifier, comprising: a tenth MOS transistor having a gate connected to the first input line.
A transistor; an eleventh MOS transistor having a gate connected to the second input line and a source connected to the source of the tenth MOS transistor; a drain connected to the first intermediate line; A twelfth MOS transistor having a path connected in series to the source / drain path of the tenth MOS transistor; a source / drain path connected in series to a source / drain path of the eleventh MOS transistor; A thirteenth MOS transistor connected to a gate of a twelfth MOS transistor, wherein the second current mirror load type sense amplifier comprises a fourteenth MOS transistor having a gate connected to the second input line.
A transistor, a fifteenth MOS transistor having a gate connected to the first input line and a source connected to the source of the fourteenth MOS transistor, a drain connected to the second intermediate line, a source / drain A sixteenth MOS transistor having a path connected in series to the source / drain path of the fourteenth MOS transistor; a source / drain path connected in series to a source / drain path of the fifteenth MOS transistor; 16. The amplifier circuit according to claim 1, further comprising a seventeenth MOS transistor connected to a gate of the sixteenth MOS transistor. 17. The semiconductor device according to claim 1, further comprising a fourth switch circuit connected between the sources of the tenth and fourteenth MOS transistors and a first operating potential point.
7. The amplifier circuit according to 6. 18. The semiconductor device according to claim 18, wherein said fourth switch circuit is an eighteenth MOS transistor.
The amplifier circuit according to claim 17, comprising a transistor. 19. The amplifier circuit according to claim 1, further comprising a fifth switch circuit connected between said first input line and said second input line. . 20. The fifth switch circuit includes an N-channel type nineteenth MOS transistor and a P-channel type twenty-first MOS transistor.
20. The amplifier circuit according to claim 19, comprising at least one of OS transistors. 21. First and second current lines having first and second input lines, first and second output lines, and the first and second input lines connected to the two inputs, respectively. A mirror load type sense amplifier, a first intermediate line connected to the output of the first current mirror load type sense amplifier, and a second intermediate line connected to the output of the second current mirror load type sense amplifier. A first MOS transistor having a gate connected to the first intermediate line and a drain connected to the first output line; a gate connected to the second intermediate line and a drain connected to the second output line; And a gate connected to the second output line and a source
The drain path is connected to the source of the first MOS transistor.
A third MOS transistor connected in series to the drain path; a gate connected to the first output line;
The drain path is connected to the source of the second MOS transistor.
An amplifier circuit comprising: a fourth MOS transistor connected in series to a drain path. 22. The source of said first MOS transistor
22. The amplifier circuit according to claim 21, further comprising a first switch circuit connected between a drain path and a source / drain path of the second MOS transistor and a first operating potential point. 23. The amplifier circuit according to claim 22, further comprising a second switch circuit connected between said first output line and said second output line. 24. The amplifier circuit according to claim 23, wherein a period during which said first switch circuit is conductive and a period during which said second switch circuit is conductive overlap. 25. The method according to claim 23, wherein the second switch circuit is changed from the conductive state to the non-conductive state after the first switch circuit is changed from the non-conductive state to the conductive state. An amplifier circuit according to any one of the above. 26. The amplifier according to claim 25, wherein said second switch circuit is turned on from said non-conductive state after said first switch circuit is turned on from said non-conductive state. circuit. 27. A semiconductor device further comprising a third switch circuit connected between the first intermediate line and the second intermediate line, after the first switch circuit is turned from a non-conductive state to a conductive state. 27. The amplifier circuit according to claim 23, wherein said third switch circuit is changed from a conductive state to a non-conductive state. 28. The amplifier according to claim 27, wherein the third switch circuit is changed from the non-conductive state to the conductive state after the first switch circuit is changed from the non-conductive state to the conductive state. circuit. 29. The third switch circuit comprises an N-channel fifth MOS transistor and a P-channel sixth MOS transistor.
29. The amplifier circuit according to claim 27, comprising at least one of transistors. 30. The semiconductor device according to claim 21, wherein said first and second MOS transistors are N-channel type, and said third and fourth MOS transistors are P-channel type.
30. The amplifier circuit according to any one of claims to 29. 31. The amplifier circuit according to claim 22, wherein said first switch circuit comprises an N-channel seventh MOS transistor. 32. The MOS transistor according to claim 21, wherein said first and second MOS transistors are P-channel type, and said third and fourth MOS transistors are N-channel type.
30. The amplifier circuit according to any one of claims to 29. 33. The amplifier circuit according to claim 22, wherein said first switch circuit comprises a P-channel seventh MOS transistor. 34. The second switch circuit comprises an N-channel type eighth MOS transistor and a P-channel type ninth MOS transistor.
30. The amplifier circuit according to claim 23, comprising at least one of a transistor. 35. The source of said third MOS transistor.
The drain path is connected in series to the source / drain path of the first MOS transistor between a first operating potential point and a second operating potential point, and the source / drain path of the fourth MOS transistor is connected to the first operating potential point. 35. The amplifier circuit according to claim 21, wherein a source and a drain path of the second MOS transistor are connected in series between the second MOS transistor and the second operating potential point. 36. The first current mirror load type sense amplifier, further comprising: a tenth MOS transistor having a gate connected to the first input line.
A transistor; an eleventh MOS transistor having a gate connected to the second input line and a source connected to the source of the tenth MOS transistor; a drain connected to the first intermediate line; A twelfth MOS transistor having a path connected in series to the source / drain path of the tenth MOS transistor; a source / drain path connected in series to a source / drain path of the eleventh MOS transistor; A thirteenth MOS transistor connected to a gate of a twelfth MOS transistor, wherein the second current mirror load type sense amplifier comprises a fourteenth MOS transistor having a gate connected to the second input line.
A transistor, a fifteenth MOS transistor having a gate connected to the first input line and a source connected to the source of the fourteenth MOS transistor, a drain connected to the second intermediate line, a source / drain A sixteenth MOS transistor having a path connected in series to the source / drain path of the fourteenth MOS transistor; a source / drain path connected in series to a source / drain path of the fifteenth MOS transistor; 36. The amplifier circuit according to claim 21, further comprising a seventeenth MOS transistor connected to a gate of the sixteenth MOS transistor. 37. The semiconductor device according to claim 3, further comprising a fourth switch circuit connected between the sources of the tenth and fourteenth MOS transistors and a first operating potential point.
7. The amplifier circuit according to 6. 38. The fourth switch circuit is an eighteenth MOS transistor.
The amplifier circuit according to claim 37, comprising a transistor. 39. The amplifier circuit according to claim 21, further comprising a fifth switch circuit connected between said first input line and said second input line. . 40. The fifth switch circuit comprises an N-channel 19th MOS transistor and a P-channel 20Mth transistor.
The amplifier circuit according to claim 39, comprising at least one of an OS transistor. 41. A first MOS transistor having first and second input lines, first and second intermediate lines, first and second output lines, and a gate connected to the first input line. A second MOS transistor having a gate connected to the second input line and a source connected to the source of the first MOS transistor; a drain connected to the first intermediate line; A third MOS transistor connected in series to the source / drain path of the one MOS transistor, a drain connected to the second intermediate line, and a source / drain path connected in series to the source / drain path of the second MOS transistor A fourth MOS transistor having a gate connected to the gate of the third MOS transistor and a fixed potential; A first switch circuit connected between the source of the first MOS transistor and a first operating potential point; a fifth MOS transistor having a gate connected to the first intermediate line; and a gate connected to the second intermediate line. A sixth MOS transistor whose source is connected to the source of the fifth MOS transistor, whose drain is connected to the first output line, and whose source / drain path is the source / drain of the fifth MOS transistor. A seventh MOS transistor connected in series to the path, a drain connected to the second output line and the gate of the seventh MOS transistor, and a source / drain path connected in series to a source / drain path of the sixth MOS transistor And its gate is connected to the drain of the seventh MOS transistor. And an eighth MOS transistor. 42. The amplifier circuit according to claim 41, further comprising a second switch circuit connected between a source of said fifth MOS transistor and said first operating potential point. 43. The amplifier circuit according to claim 42, further comprising a third switch circuit connected between said first output line and said second output line. 44. The amplifier circuit according to claim 43, wherein a period in which said first and second switch circuits are conducting overlaps a period in which said third switch circuit is conducting. 45. The method according to claim 43, wherein the third switch circuit is changed from the conductive state to the non-conductive state after the first and second switch circuits are changed from the non-conductive state to the conductive state. 44. The amplifier circuit according to any one of the above items. 46. The semiconductor device according to claim 45, wherein said third switch circuit is turned on from said non-conductive state after said first and second switch circuits are turned on from said non-conductive state. An amplifier circuit as described. 47. A semiconductor device further comprising a fourth switch circuit connected between the first intermediate line and the second intermediate line, after the first switch circuit is turned from a non-conductive state to a conductive state. 47. The amplifier circuit according to claim 43, wherein the fourth switch circuit is changed from a conductive state to a non-conductive state. 48. The amplifier according to claim 47, wherein said fourth switch circuit is changed from a non-conductive state to a conductive state after said first switch circuit is changed from a non-conductive state to a conductive state. circuit. 49. The fourth switch circuit includes an N-channel ninth MOS transistor and a P-channel type tenth MOS transistor.
49. The amplifier circuit according to claim 47, comprising at least one of S transistors. 50. The transistor according to claim 41, wherein said fifth and sixth MOS transistors are N-channel type, and said seventh and eighth MOS transistors are P-channel type.
50. The amplifier circuit according to any one of claims to 49. 51. The amplifier circuit according to claim 42, wherein said second switch circuit comprises an N-channel eleventh MOS transistor. 52. The MOS transistor according to claim 41, wherein said fifth and sixth MOS transistors are P-channel type, and said seventh and eighth MOS transistors are N-channel type.
50. The amplifier circuit according to any one of claims to 49. 53. The amplifier circuit according to claim 42, wherein said second switch circuit comprises a P-channel eleventh MOS transistor. 54. The third switch circuit comprises an N-channel type twelfth MOS transistor and a P-channel type thirteenth MOS transistor.
50. The amplifier circuit according to claim 43, comprising at least one of OS transistors. 55. The source of the seventh MOS transistor
The drain path is connected in series to the source / drain path of the fifth MOS transistor between a first operating potential point and a second operating potential point, and the source / drain path of the eighth MOS transistor is connected to the first operating potential point. 55. The amplifier circuit according to claim 41, wherein the amplifier circuit is connected in series to a source / drain path of the sixth MOS transistor between the second operating potential point and the second operating potential point. 56. The first switch circuit is a fourteenth MOS transistor.
The amplifier circuit according to any one of claims 41 to 55, comprising a transistor. 57. The amplifier circuit according to claim 41, further comprising a fifth switch circuit connected between said first input line and said second input line. . 58. The fifth switch circuit includes a fifteenth N-channel MOS transistor and a sixteenth P-channel MOS transistor.
The amplifier circuit according to claim 57, comprising at least one of OS transistors. 59. An amplifier circuit according to claim 1, wherein said first and second output lines are insulated from said first and second intermediate lines.