JPH09171694A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make outputting information from an SRAM onto a data line at high speed possible by providing a PMOS latch on a pair of data line of an SRAM cell. SOLUTION: An SA is the circuit cascade-connecting two stages of amplifiers consisting of a NMOS differential circuit and a PMOS latch, and an MA is the circuit adding a tri-state controlling transistor to the amplifier consisting of the NMOS differential circuit and the PMOS latch. In addition to that, a CMOS positive feedback preamplifier circuit PFB1 is added between common data lines d, d-bar. Then, further, the CMOS positive feedback preamplifier circuit PFB2 is added between bit lines b, b-bar, and the potential difference between the bit line pair b, b-bar is enlarged further at high speed. Then, the operation of the SA is accelerated further.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, that is, a semiconductor integrated circuit in which memory cells are integrated, and more particularly to a pair of complementary signals having a minute potential difference read from a memory cell at high speed and with a large amplification factor. The present invention relates to sense amplifier circuit technology for amplification.

[0002]

2. Description of the Related Art As an example of a conventional sense circuit for amplifying a read signal from a memory cell, Japanese Patent Laid-Open No. Sho 52-52 is known.
No. 8734, as shown in FIG. 3, has complementary pair input signals d and −d connected to the gates and drains of the two drive MOS transistors Q13 and Q14 of the sense amplifier circuit in a stride. MOSQ13,
The drains of Q14 are complementary pair output signals D and ￣D, respectively.
It has become.

Further, US Pat. No. 4,335,449 discloses two load MOS transistors Q2 as shown in FIG.
1, Q22 are connected to each other, and drive transistor Q
Bipolar transistors are used for 23 and Q24, and complementary pair input signals d and −d are connected to the bases of the two driving bipolar transistors Q23 and Q24.

Other conventional sense circuits include JP-A-62-46489 and US Pat. No. 4,24.
There is also a description in No. 7,791.

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention JP-A-52-87
No. 34 (see FIG. 3) has complementary pair input signals d and _d connected to both the gates and drains of the driving MOS Q13 and Q14 in the sense amplifier circuit, and outputs the input signal lines d and _d. Since the signal lines D and ￣D are directly connected, if the output signal lines D and ￣D have a very large load capacitance, they cannot be amplified at high speed, and due to the positive feedback operation, they are complementary. It has been clarified by the study of the inventors of the present application that the inversion of the input and output signals is slow.

Further, the above-mentioned US Pat. No. 4,335,449 (see FIG. 4) discloses bipolar transistors Q23 and Q2.
4 is used to drive the load capacitance of the output signal line,
When the potential difference between the complementary pair input signals d and _d is small, the bipolar transistor Q23, which responds to this input potential difference,
The operating current of Q24 is weakly connected to the positive feedback holding current flowing in the load MOS transistors Q21 and Q22 to which the operating currents of the load MOS transistors Q23 and Q24 to which it is cross-connected are responsive to a minute input signal. And bipolar transistors Q23 and Q24 and load MO
It was also made clear by the study of the inventors of the present application that the S transistors Q21 and Q22 cannot be inverted and the high speed sensing operation for a minute input signal is difficult.

Therefore, an object of the present invention is to provide a sense amplifier circuit capable of operating at high speed by overcoming the above-mentioned drawbacks of the prior art.

[0008]

As described above, in order to enable a high-speed sensing operation for a minute input signal read from a memory cell, the gate and drain are connected to a cross-coupled load MOS transistor. A first switching means is connected between the complementary outputs of the pair of transistors, and when the pair of transistors is inverted in response to the read signal, the first switching means is made conductive by the first control signal, and then the above-mentioned. The first switching means is controlled to be in a non-conducting state.

On the other hand, as described above, the preamplifier has a circuit form in which its input signal line and its output signal line are directly connected in order to drive the output signal line of the sense amplifier having a very large load capacitance at high speed. In order to start the signal reading from the memory cell, the preamplifier and the sense amplifier are controlled to the active state, the complementary signal read from the memory cell is amplified by the preamplifier, and the complementary amplified output signal of this preamplifier is further Amplification by the sense amplifier in the subsequent stage, and a multi-stage amplifier circuit configuration that drives the heavy load capacitance of the output signal line of the sense amplifier by the complementary output signal of this sense amplifier, and when the amplification operation of the sense amplifier in the subsequent stage is almost completed The preamplifier in the previous stage is controlled to the inactive state (after the lapse of a predetermined time from the start of reading the signal from the memory cell), and It is to maintain the width unit active.

[0010]

When the first switching means is turned on by the first control signal, the load MOS is cross-coupled.
Since the positive feedback holding operation of the transistors is canceled, the pair of transistors can perform a high-speed inversion operation in response to a minute input signal.

On the other hand, since the preamplifier in the preceding stage is controlled to be inactive when the amplifying operation of the sense amplifier in the latter stage is almost completed, the potential difference between the complementary input / output of the preamplifier, that is, the complementary input of the sense amplifier is expanded more than necessary. Then, the next inversion reading can be executed at high speed. Even if the preamplifier is controlled to the inactive state, the signal read from the memory cell is controlled to the active state via the direct connection path between the input signal line and the output signal line of the preamplifier in the inactive state. Since it is transmitted to the input of the sense amplifier and amplified, the loss of the amplified output of the sense amplifier can be avoided.

[0012]

An embodiment of the present invention will be described below with reference to FIG. Q1, Q2, Q6 and Q8 are p-channel MOS transistors (hereinafter referred to as pMOS), Q3, Q4, Q5.
Q7 and Q9 are n-channel MOS transistors (hereinafter nM
OS)), d and −d are a pair of complementary signals input to the sense circuit of this embodiment, the complementary read signals from the memory cells are transmitted, and D and D− are a pair output from this sense circuit. Complementary signals of ￣φ1, φ1, ￣φ2, φ2
Are pulse signals for driving the transistors Q6, Q7, Q8, Q9, and SAC applied to the gate terminal of the NMOS Q5 is an activation signal for the sense amplifier. The timings of these signals are shown in FIG. , PMOS
Q1 and Q2 are cross-coupled load MOS, N
MOSQ3 and Q4 operate as differential transistors, and PMOSQ8 and NMOSQ9 operate as first switching means,
The pulse signals φ2 and φ2 are the first control signals.

The operating transistors Q3 and Q4 are npn.
It can also be replaced by a bipolar transistor. Further, only one of the transistors Q6 and Q7 may be used, and only one of the transistors Q8 and Q9 can operate.

D and _d are a pair of complementary input signals of the sense amplifier having a minute potential difference read from the static memory cell, and the pulse signal _φ1, during the signal transition period.
With φ1, the complementary input signal potential difference reducing MOS transistors Q6 and Q7 are rendered conductive, and d and −d are set to the same potential, so that the inversion reading speed is increased. Then, pulse signal ￣φ
The complementary output signal potential difference reducing MOS transistors Q8 and Q9 are made conductive by 2 and φ2, the complementary output signals D and _D are set to the same potential, and the positive feedback of the cross-coupled load MOS transistors Q1 and Q2 is held. Since the operation is weakened, the inversion read speed is increased. Next, Q6 and Q7 are made non-conductive at the same time that a pair of complementary signals starts to be read out from the memory cell to d and ￣ d, and d and ￣
The potential difference between d spreads. Then, Q8 and Q9 are also made non-conductive.

Now, consider a time point at which the time t1 transits to t2 on the time axis of the timing chart of FIG. At this time, the potential of d drops and the potential of −d rises, but the nodes N1 and N2 are still at the same potential. Therefore, the drain current of Q3 decreases and the drain current of Q4 increases,
After that, the potential of the node N1 rises and the potential of the node N2 starts to fall. Therefore, the drain current of Q1 increases and Q
The drain current of 2 decreases, and the potential of the node N1 rises and the potential of the node N2 falls. This is Q
The drain current of 1 increases, the drain current of Q2 decreases, the potential of the node N1 increases, and the potential of the node N2 decreases. That is, positive feedback acts on the nodes N1 and N2 of the present sense amplifier, which has the effect of rapidly expanding the potential difference, and an extremely high-speed sense amplifier can be realized.

That is, the differential transistors Q3 and Q4 respond to the complementary input signals d and d, and the load MOS
The transistors Q1 and Q2 are the differential transistors Q3 and
Since it responds to Q4, it is possible to charge or discharge the complementary outputs D and D with a large load capacity at high speed.

In this sense amplifier, Q6, Q7, Q
8, Q9 plays a very important role. That is, between complementary input signals d and _d and complementary output signals D and _D
The gaps are short-circuited during the signal transition period, and function to promptly perform the signal transition. The timings of d, _d and D, _D when Q6, Q7, Q8 and Q9 are not used are shown by broken lines in FIG. At this time, the action of the positive feedback circuit of the load MOS transistors Q1 and Q2 prevents the transition of the complementary output signals D and _D, and finally the transition of D and _D occurs at time t3 when the potential difference of the complementary input signals becomes large. That is, the sense speed is significantly reduced. Alternatively, when the maximum potential difference between the complementary input signals d and _d is small, the transition of the complementary output signals D and _D may not occur, that is, correct data may not be read.

As described above, the present embodiment has the effect of amplifying a pair of complementary input signals having a minute potential difference at an extremely high speed and with a large amplification factor.

Another embodiment of the present invention is shown in FIG. The embodiment of FIG. 5 has a configuration in which the roles of pMOS and nMOS are interchanged with each other in the first embodiment (FIG. 1).
Similar to, it has the effect of amplifying at an extremely high speed and a large amplification factor.

Also in this embodiment, the MOS transistor Q
36 or Q37 may be either one, Q38 and Q39
Either one of them can perform the desired operation.

FIG. 6 is also another embodiment of the present invention.
FIG. 6 shows a configuration in which the circuit of FIG. 1 is cascade-connected in two stages, and the amplification factor can be further increased by cascade-connecting two stages, and the potential difference between the complementary output signals D and ￣D can be expanded to the full power supply voltage. You can Further, in the circuit of FIG. 6, the size of the transistors Q46 to Q50 of the second stage sense amplifier section is increased to cooperate with the load driving capability, and when a large load capacitance is connected to D and ￣D, this load capacitance is It can be driven at high speed.

FIG. 7 is also another embodiment of the present invention. The circuit shown in FIG. 7 is a well-known NMOS differential Q43, Q.
A sense amplifier composed of 44, Q43 ', Q44' and PMOS current mirrors Q41, Q42, Q41 ', Q42' is used as the first stage, and the circuit of FIG. 1 is cascade-connected as the second stage sense amplifier.

The present invention relates to a so-called double-ended sense amplifier which outputs complementary outputs D and D. When using a current mirror load, two current mirror load circuits are required to obtain complementary outputs. Although the first stage current mirror load circuit type sense amplifier of FIG. 7 is fast, it is not as fast as the second stage cross-coupled load circuit type sense amplifier of FIG. Further, there is a drawback that the number of transistors in the first stage is nine, whereas the number of transistors in the second stage is five.

However, in FIG. 7, the following advantages are brought about by using the current mirror load circuit type sense amplifier in the first stage.

That is, in order to increase the speed of the memory device, the delay TD from the time point of applying the word line drive signal for selecting the word line of the memory device to the time point of outputting from the sense amplifier is made small. is important. on the other hand,
The MOS transistors Q51, Q52, Q53, Q54, Q55, Q5 are applied from the time of applying the word line drive signal.
There is a delay TE until the end of the potential difference reduction operation between complementary signal lines due to the non-conduction of 6.

The horizontal axis of FIG. 21 shows the latter delay TE, and the vertical axis thereof shows the former delay TD. In FIG. 21, the practice shows the characteristics of the embodiment of FIG. 7, and the broken line shows the implementation of FIG. The characteristics of the example are shown.

In any of the characteristics, if the delay TE from the time of applying the word line drive signal to the time of ending the operation of reducing the potential difference between the complementary signal lines is too short, the differential transistor or the load transistor in the sense amplifier will be affected. While the amplitude of the complementary input signal of the first stage of the sense amplifier is very small due to the difference in electrical characteristics of the paired transistors, the differential transistor of the first stage of the sense amplifier The erroneous information is temporarily output from the complementary output of, and a delay occurs to obtain correct information from the complementary output of the first stage differential transistor. This delay will predominantly determine the delay TD from the time of application of the word line drive signal to the time of output from the sense amplifier.

Since the amplification factor of the positive feedback load in the first stage of the sense amplifier of the embodiment of FIG. 6 is large, erroneous information is output from the output of the first stage with a large amplitude. On the other hand, since the amplification factor of the first stage current mirror load of the sense amplifier of the embodiment of FIG. 7 is smaller than that of the positive feedback load of FIG. 6, the first amplification of the sense amplifier of the embodiment of FIG. The amplitude of the false information generated from the output of the stage becomes small,
The delay TD in FIG. 7 is small.

As described above, FIG. 7 is compared with the embodiment of FIG.
In this embodiment, since the amplification factor of the load circuit is small, even if the delay TE related to the end of the potential difference reduction operation is shortened, the delay TD related to the output of the sense amplifier is not so large.

Therefore, according to the embodiment of FIG. 7, the minimum value of the delay TE related to the end of the potential difference reducing operation can be reduced by 1.3 nS as compared with the embodiment of FIG.
The timing margin regarding the delay time TE can be increased.

FIG. 8 shows another embodiment of the present invention. The circuit of FIG. 8 has a configuration in which a differential amplifier having PMOS Q41 and Q42 whose gate is applied with a fixed voltage such as a ground voltage as a load is used as a first stage, and the circuit of FIG. 1 is cascade-connected as a second stage sense amplifier. There is.

Also in the configurations of FIGS. 7 and 8, the large load capacitances of the data buses D and _D can be driven at high speed by the positive feedback sense amplifier in the second stage.

The circuit of FIG. 9 is a known sense circuit,
Two current mirror type amplifiers connected in parallel
It has a structure of vertically connected stages.

FIG. 10 is a graph showing the delay times of the sense circuit of FIG. 6 which is an embodiment of the present invention and the sense circuit of FIG. 9 which is a conventional example, with respect to the sense amplifier average current.
From FIG. 10, the sense circuit of FIG. 6 which is an embodiment of the present invention is a conventional example. It is apparent that it has twice as high speed as the sense circuit of FIG.

FIG. 11 shows another embodiment of the present invention, which is a static random access memory (SRA).
M). In FIG. 11, the sense amplifier circuit of FIG. 6 is used as the SA for amplifying the read signal from the SRAM cell, and as the MA, the sense amplifier circuit of FIG. 1 is added with PMOS transistors Q71 and Q72 for controlling tristate output. It is an amplifier circuit.

FIG. 12 shows an example of an integrated circuit examined by the inventors of the present application before application. In the embodiment shown in FIG. 11, the number of transistors is significantly reduced as compared with FIG. The area is almost half.

In addition, the use of the circuit of FIG. 11 makes it possible to significantly speed up the operation, and the time required for the memory cell information to reach Dout is reduced to about half that in the case of using the circuit of FIG. Is confirmed by circuit analysis.

This is the load PMO in the circuit of FIG.
The gain of the load MOS is small because the S transistor is connected in the current mirror, whereas the gain of the load MOS is large because the load PMOS transistor is connected in the positive feedback cross-coupled manner in the circuit of FIG. ing.

FIG. 13 shows operation waveforms by circuit analysis when the sense circuit of FIG. 11 is applied to a 1 Mbit SRAM. In FIG. 13, the minute potential difference between the common data lines d and −d is amplified at high speed by the first-stage and second-stage sense amplifiers (SA in FIG. 11), and the CMOS level signal S2.
￣ S2 is obtained. The signals S2 and S2 propagate through the data bus having a large wiring capacitance, and then are transferred to the main amplifier (see FIG. 1).
Waveforms blunted at the input end of MA (Fig. 13D,
However, as soon as a minute potential difference occurs between D and ￣D, high-speed main amplifier output signals D1 and ￣D1 are obtained by amplifying with the main amplifier, and the inverter INV
The output transistors Q75 and Q76 are driven via 1 and INV2. Thus, according to the circuit configuration of FIG. 11, the operations of the first stage, the second stage, and the main amplifier of the sense amplifier are
It can be performed with a delay of about ns, and the output Dout can be obtained at an extremely high speed. In the example of FIG. 13, the output Dout is obtained for about 3 ns after the potential difference starts to occur on the common data lines d and −d.

Further, in FIG. 12, in response to the data output control signal DOC, the output terminal Dou is provided after the main amplifier MA.
While the output control circuit DB for determining the high impedance state of t is used, in the embodiment of FIG. 11, the NMO controlled by the data output control signal DOC is used.
The active state or inactive state of the main amplifier MA is controlled by the S transistor Q70, while the output terminal Dout is output.
By connecting in parallel the PMOS transistors Q71 and Q72 for setting the high impedance state to the output of the main amplifier MA and controlling by the DOC, the circuit corresponding to the output control circuit DB in FIG. 12 can be omitted, and the output buffer circuit in the output buffer can be omitted. The signal transmission time can be shortened.

FIG. 14 also shows another embodiment of the present invention, in which the sense circuit shown in FIG. 7 is used for the first-stage and second-stage sense amplifiers SA.

FIG. 15 is also another embodiment of the present invention, in which the sense circuit shown in FIG. 8 is used for the first-stage and second-stage sense amplifiers SA.

FIG. 16 is also another embodiment of the present invention (sense circuit for static RAM). In the embodiment of FIG. 11, CMOS positive feedback preamplifier circuit PFB1 (Q204, Q205, Q225
Q228) is added. FIG. 17 shows FIG.
16 is a waveform chart showing the operation of the sixth embodiment, and FIG. 16 will be described below with reference to FIG. The potential difference read from the static RAM memory cell and transmitted to the common data lines d and d is normally about 0.1 to 0.2 V, and how to amplify this minute potential difference at high speed is the key to speeding up. . d, ￣
A pulse is applied to φCDQ and ￣φCDQ for the signal transition feedback of d to make the MOS transistors Q202 and Q203 temporarily conductive, and the signal transition of d and ￣d is promptly performed. Next, the signal potential difference due to the newly selected memory cell starts to occur at d and −d, and at the same time, the pulse φCDA,
With φCDA, MOS transistors Q204, Q20
5 is made conductive, and the CMOS positive feedback preamplifier circuit PFB1 in which the input signal line and the output signal line are directly connected is operated. PFB1 positively amplifies the potential difference between d and ￣d,
A maximum potential difference of about 0.5 V is obtained (ΔV1). PFB1
The effect of is to increase the potential difference between d and −d rapidly so that the sense circuit at the next stage can be operated quickly and stably. After the sense operation in the next stage and after is completed, Q204, Q
205 is made nonconductive by φCDA and φCDA, and P
The FB1 does not operate, and the signal read from the SRAM memory cell via the Y-direction switch MOS transistor is C
The signal is not amplified by the MOS positive feedback preamplifier circuit PFB1 but is transmitted to the common data lines d and −d through the direct connection between the input signal and the output signal line of the preamplifier circuit PFB1. Thus, d, ￣
The potential difference of d does not increase more than necessary and gradually changes to the steady-state potential difference ΔV2 (0.1 to 0.2 V).
That is, the potential difference between the common data lines d and d does not open too much and the next reading of the memory cell information is not delayed. Sense amplifier first stage (SA1) output S1, ￣ S1
Pulse MOS transistors Q206 and Q207
From EQ1, ￣φSEQ1, the second stage of the sense amplifier (SA
2) Outputs S2 and S2 are MOS transistors Q208,
Q209 is made to conduct signal transition feedback by pulses φSEQ2 and φSEQ2, and also promptly makes signal transition. After that, a potential difference occurs on the common data lines d and −d, and at the same time, Q206, Q207, Q208, and Q209.
Is made non-conductive, and the sense amplifiers SA1 and SA2 are operated by the control signal Y.SAC.
Signal S1, amplified at a very high speed by the positive feedback operation
S1 and S2, S2 are obtained.

MOS transistors Q212, Q213, Q21 forming a transfer gate connecting the outputs S2, S2 of the second stage of the sense amplifier and the data buses D, D.
4, Q215 are made conductive before a signal is output to S2, S2, and MOS transistors Q210,
Q211, Q216, Q217 pulse φSEQ2,
ΦSEQ2, ΦBEQ and ￣ ΦBEQ are used to make signal transition feedback conductive so that a potential difference occurs at S2 and ￣S2 and at the same time Q
210, Q211, Q216, Q217 are made non-conductive. The signal S2 amplified by the second stage SA2 of the sense amplifier
-S2 has a smooth waveform (FIG. 17D, -D) while propagating through a data bus having a large load capacity.

The main amplifier outputs M and ￣M make the MOS transistor Q218 non-conductive by the control signal DOC and make Q219 and Q220 conductive during the signal transition period, and the φMAEQ and ￣φMAEQ signals make the MOS output.
By making the transistors Q221 and Q222 conductive, the potentials of M and −M are temporarily set to the power supply voltage VCC potential. Therefore, during this period, the output NMOS transistors Q223 and Q224 are both non-conductive, and the output signal Dout is "0" to "1" or "1" to "0".
To the output transistors Q223 and Q224 during the transition to
Since there is no current flowing through, the operation with low power consumption and low noise can be performed. Next, before the potential difference occurs between D and D, Q218 is turned on by the DOC signal and Q2 is turned on.
When N, Q220 is made non-conductive, and a potential difference is subsequently generated at D, D at the same time as Q221, Q222 are made non-conductive, signal waveforms M, M are amplified at high speed by the main amplifier MA1. These signals are
Output transistors Q223 and Q via NV1 and INV2
224 is driven to obtain the output Dout.

In this way, the output waveform Dout can be obtained at an extremely high speed by sequentially amplifying the minute potential difference between the common data lines d and −d at a high speed.

As another embodiment of the present invention, a circuit configuration using FIG. 7, FIG. 8 or FIG. 9 as the first stage and second stage sense circuit portions SA of FIG. 16 is also conceivable, and any of these embodiments has already been performed. The output can be obtained at a higher speed than the operation similar to that described.

FIG. 18 also shows another embodiment of the present invention. FIG.
8 has a configuration in which a PMOS positive feedback circuit PFB2 is added to the embodiment of FIG. The effect of PFB2 is to increase the potential difference between the bit line pair b and ￣b at a high speed, to increase the potential difference between the common data lines d and ￣d more quickly than in the embodiment of FIG. 16, and to speed up the operation of the sense amplifier SA. In addition, it enables even higher speed amplification.

As another embodiment of the present invention, a circuit configuration using FIG. 7, FIG. 8 or FIG. 9 as the sense circuit section SA of the first stage and the second stage of FIG. 18 is also conceivable. Similar to 18, high-speed sense amplification can be realized.

FIG. 19 shows another embodiment of the present invention, which is Q301, Q308, Q310, Q311, Q31.
5 is a P-channel MOS transistor, Q302,
Q303, Q304, Q305, Q306, Q307,
Q309, Q312, Q313, Q314 and Q316 represent N-channel MOS transistors.

In the circuit of FIG. 19, two types of sense amplifiers are connected in cascade, and the first-stage sense amplifiers are Q303, Q304, Q305, Q306, Q3.
07 and all N-channel MOS transistors, Q310, Q311, Q312, Q313, Q3
The sense amplifier of FIG.
It is used as the stage sense amplifier.

The MOS transistors Q301 and Q302 are connected between the complementary lines d and −d, and the MOS transistor Q301
308 and Q309 are connected between the complementary lines D1 and _D1, and the MOS transistors Q315 and Q316 are connected between the complementary lines D and _D.

Source follower operation N in which complementary signals D1 and D1 form a pair in response to input signals of complementary lines d and d.
After being obtained by the channel MOS transistors Q303 and Q304, the N-channel MOS transistor Q305 whose gate and drain are cross-coupled,
It is amplified at high speed by Q306.

The complementary signals D1 and D1 increase the size of the transistors Q310, Q311, Q312, Q313 and Q314 to enhance the load driving capability, and D and D
Even if a large load capacitance is connected to D, this load capacitance can be driven at high speed.

FIG. 20 also shows another embodiment of the present invention, which is Q401, Q403, Q404, Q405, Q40.
6, Q407, Q408, Q410, Q411, Q41
Reference numeral 5 denotes a P-channel MOS transistor, Q402,
Q409, Q412, Q413, Q414, and Q416 represent N-channel MOS transistors.

In the circuit of FIG. 20, two types of sense amplifiers are connected in cascade, and the first-stage sense amplifiers are Q403, Q404, Q405, Q406, Q4.
07 and all P-channel MOS transistors, Q410, Q411, Q412, Q413, Q4
The sense amplifier of FIG.
It is used as the stage sense amplifier. The MOS transistors Q401 and Q402 are connected between the complementary lines d and _d, the MOS transistors Q408 and Q409 are connected between the complementary lines D1 and _D1, and the MOS transistor Q is connected.
415 and Q416 are connected between complementary lines D and D.

A source follower operation P in which complementary signals D1 and D1 form a pair in response to input signals of complementary lines d and d
After being obtained by the channel MOS transistors Q403 and Q404, the P-channel MOS transistor Q405 whose gate and drain are further cross-coupled is connected.
It is amplified at high speed by Q406.

The complementary signals D1 and D1 increase the size of the transistors Q410, Q411, Q412, Q413 and Q414 to cooperate with the load driving capability, and
Even if a large load capacitance is connected to D, this load capacitance can be driven at high speed.

As described above, the N-channel MOS transistors Q303 and Q304 of the first stage of the sense amplifier in the embodiment of FIG. 19 and the P-channel of the first stage of the sense amplifier of the embodiment of FIG. Each of the MOS transistors Q403 and Q404 operates as a source follower having a voltage gain of 1 or less, and the N-channel MOS transistors Q305 and Q305 in which the gate and drain of the first stage of the sense amplifier in the embodiment of FIG. 19 are cross-coupled to each other.
306 and the P-channel MOS transistors Q405 and Q406 in which the gate and drain of the first stage of the sense amplifier in the embodiment of FIG. 20 are cross-coupled, operate as a source load circuit of the source follower, and this cross-coupled load The voltage gain of the circuit is much greater than unity.

In the embodiment of FIGS. 19 and 20,
As in the previous embodiment, in response to the pulse signals φ2 and φ2, the MOS transistors Q308, Q309, Q408,
When Q409 conducts, load MOS transistors Q305, Q306, Q are cross-coupled.
The positive feedback operation of 405 and Q406 is eliminated.

The present invention is not limited to SRAM, but can be applied to all memory devices such as DRAM, PROM and EPROM.

Further, it is needless to say that the present invention is not limited to the above-mentioned specific embodiments, and various modifications can be made according to the basic technical idea thereof.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a timing diagram suitable for operating the circuit of FIG.

FIG. 3 is a circuit diagram showing a conventional technique.

FIG. 4 is a circuit diagram showing a conventional technique.

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

FIG. 6 is a circuit diagram showing another embodiment of the present invention.

FIG. 7 is a circuit diagram showing another embodiment of the present invention.

FIG. 8 is a circuit diagram showing another embodiment of the present invention.

FIG. 9 is a circuit diagram showing a conventional sense circuit.

FIG. 10 is a characteristic diagram showing the sense amplifier average current dependency of the delay time required for sense amplification in one embodiment of the present invention (FIG. 6) and a conventional sense circuit example (FIG. 9).

FIG. 11 is a circuit diagram showing another embodiment of the present invention.

FIG. 12 is a circuit diagram showing a circuit examined by the present inventors before application.

13 is an operation waveform diagram of the embodiment of FIG.

FIG. 14 is a circuit diagram showing another embodiment of the present invention.

FIG. 15 is a circuit diagram showing another embodiment of the present invention.

FIG. 16 is a circuit diagram showing another embodiment of the present invention.

FIG. 17 is an operation waveform chart for explaining the operation of the embodiment of FIG.

FIG. 18 is a circuit diagram showing another embodiment of the present invention.

FIG. 19 is a circuit diagram showing another embodiment of the present invention.

FIG. 20 is a circuit diagram showing another embodiment of the present invention.

21 is a diagram showing a difference in characteristics between the embodiment of FIG. 6 and the embodiment of FIG.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shoji Hanamura 1-280, Higashi Koigokubo, Kokubunji, Tokyo Metropolitan company Central Research Laboratory

Claims (2)

[Claims] 1. A plurality of SRAM cells, a plurality of data line pairs connected to the plurality of SRAM cells, a switch circuit connected to each data line pair of the plurality of data line pairs, and the switch circuit. A common data line pair commonly connected to the plurality of data line pairs, an amplifier circuit connected to the common data line pair, and a gate of one of the data line pairs of the plurality of data line pairs. A first MOS transistor connected to the data line and having its drain connected to the other data line; and a second M transistor having its gate connected to the other data line and its drain connected to the one data line.
A semiconductor integrated circuit comprising an OS transistor. 2. The semiconductor integrated circuit according to claim 1, wherein the amplifier circuit includes a CMOS positive feedback preamplifier.