JP3406988B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundancy circuit.

[0002]

2. Description of the Related Art A conventional semiconductor memory device generally has a defective sense amplifier, a broken bit line, a short circuit between bit lines,
A redundancy circuit is provided to relieve shorts between bit lines, defective bits, and the like. For example, since one redundant column is provided for the memory cell array of n columns and this redundant column is replaced for one defective column, the column defect is relieved. Only one can be relieved. However, in such a semiconductor memory device, miniaturization and higher integration have been required more and more in recent years. Therefore, the pitch between bit lines becomes narrower, and a short circuit between bit lines becomes a serious problem. Has become.

In a semiconductor memory device having a multi-bit configuration such as x4 or x8, the above short circuit between bit lines is IO.
The pair becomes defective. Therefore, in order to remedy this IO pair failure, in the conventional semiconductor memory device, for example, the IO selection circuit having the configuration shown in the circuit diagram of FIG. 8 is used to select the IO by the selector of the redundancy circuit. In the figure, four 3's to which the enable signal ENA is commonly input.
Of the input NAND circuit ₄₃ 1 ~ 43 _4, NAND circuit 43 ₁ are fuse signal FIO0 and FIO1 are inputted, the NAND circuit 43 ₂ FIO1 inverted by the fuse signal FIO0 and an inverter 42 are input, NAN
D circuit 43 ₃ fuse signal FIO0 and fuse signal FIO1 which has been inverted is inputted by the inverter 41 and further, NAND circuit 43 ₄ is fuse signal FIO1 input inverted by the fuse signal FIO0 and an inverter 42 which is inverted by the inverter 41 To be done.

Of the _four 3-input NAND circuits 47 _{1 to} 474 to which the enable signal ENA is commonly input, the NAND circuit 47 ₁ is the fuse signals FIO2 and FIO.
IO3 is input, NAND circuit 47 ₂ FIO3 inverted by the fuse signal FIO2 and the inverter 46 are input, NAND circuit 47 ₃ fuse signal FIO2 and fuse signal FIO3 which has been inverted is inputted by the inverter 45, and further, NAND circuit 47 ₄ inverter 45
Fuse signal FIO2 and inverter 46 inverted by
The fuse signal FIO3 inverted by is input. The NAND circuits 43 ₁ to 43 ₄ and the NAND circuit 47 ₁ described above.
Each output signal of the to 47 _4, inverters ₄₄ 1 _{to 44} 4,
It is output through 48 _{1 to} 48 ₄ .

In the conventional semiconductor memory device of this x8 configuration, in order to save the pair defects of all combinations, I
It is necessary to divide the O bus into two groups, an even number and an odd number, and select one IO bus from each group, which requires four fuse signals FIO0 to FIO3 in total.
However, the fuse circuit required for the enable signal ENA is excluded.

[0006]

In the above-mentioned conventional semiconductor memory device, the IO buses are divided into two groups, an even number and an odd number, and one IO bus is selected from each group. Is N, the required number of fuse circuits is {2 × (log ₂ N) −2}, and thus the larger N, the larger the circuit scale.
Further, since the fuse needs to be blown by a laser or the like, it is difficult to miniaturize it as compared with a logic circuit. For this reason,
The layout of the column redundancy circuit is large, and as a result, the conventional semiconductor memory device has a problem of increasing the chip area.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a semiconductor memory device that can improve the defect relief efficiency with a small number of fuses.

Another object of the present invention is to provide a semiconductor memory device which can reduce the chip size.

[0009]

In order to achieve the above object, the present invention provides a defective IO of a memory having a plurality of IO lines.
A semiconductor memory device having a redundancy circuit for repairing a line pair, wherein one defective IO of a defective IO line pair is provided.
Fuse for generating a first fuse signal corresponding to the line and a second fuse signal indicating whether the other defective IO line of the defective IO line pair is the upper IO line or the lower IO line of the one defective IO line Generating a first IO selection signal corresponding to one defective IO line based on the circuit and the first fuse signal,
A second IO selection signal corresponding to the other defective IO line based on the second fuse signal and supplied to the selector of the redundancy circuit to repair the defective IO line pair; It was done.

Here, the IO selection circuit in the present invention is
2n defective (n is a natural number) based on the first fuse signal
Output a first IO selection signal for selecting the column IO of
Based on the logic value of the second fuse signal, the column IO of (2n + 1) adjacent to the upper side or the column IO of the lower side (2n) is adjacent.
A second IO selection signal for selecting the column IO of -1) is output.

The IO selection circuit of the present invention outputs a first IO selection signal based on (log ₂ N) -1 first fuse signals, where N is the number of IO lines in the memory. , A second IO based on one of the second fuse signals
It is characterized by outputting a selection signal.

In the present invention, attention is paid to the fact that a defect in an adjacent IO line pair or a defect in an adjacent word line pair causes a serious problem, and the repair is limited to these cases. In the case of the number of lines N (xN configuration), one of the pair defective IOs can be identified by the (log ₂ N) -1 first fuse signal, and the other defective IO is the identified defective IO or the upper part of the defective word line. Second indicating side or lower
Since it can be specified by the fuse signal of, the number of fuses required for repairing all the pair defects can be log ₂ N. However, the number of fuses required for the enable signal ENA is excluded.

In order to achieve the above object, the present invention provides a first spare word driver and a second spare word driver for repairing a defective word line pair of a memory having a plurality of IO lines.
And a redundancy circuit for selecting one spare word line by the spare word driver, and a first spare word line selection signal corresponding to one defective word line of the defective word line pair. It is supplied to the first spare word driver occurs, the even-th or
First to select one of odd-numbered spare word lines
Selection circuit, a fuse circuit for generating a fuse signal indicating whether the other defective word line of the defective word line pair is an upper word line or a lower word line of one defective word line, and a first spare word line selection circuit. based on the signal and the fuse signal, generates a second spare word line selection signal corresponding to the other defective word line is supplied to the second spare word driver, among the odd-numbered or even-th spare word line It is configured to have a second selection circuit for selecting one.

In the present invention, by using the concept of upper pair and lower pair, in the case of M spare word lines and word address K bits, the first selection circuit is M / 2 circuit,
The fuse circuit can be composed of (M / 2) -1 circuit and one second selection circuit.

Among conventional semiconductor memory devices, there is also known a semiconductor device in which a defective column and a column adjacent thereto can be replaced with two redundant columns (Japanese Patent Laid-Open No. 7- Japanese Patent Laid-Open No. 57495) discloses that two redundant columns are provided for each memory cell array, and one of the fuses in the odd column or the even column is detected, and one of the two redundant columns is detected based on the detected output. The number of fuses cannot be reduced because it is configured to select.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of a main part of a semiconductor memory device according to the present invention, and FIG. 2 is an overall schematic configuration diagram of an embodiment of a semiconductor memory device according to the present invention. The semiconductor memory device shown in FIG. 2 includes an IO selection circuit 10,
a column redundancy circuit 20 in a dynamic random access memory (DRAM) of x8 configuration,
And a fuse circuit 30.

In this embodiment, when the power is turned on, the PON signal which is temporarily activated is input to the fuse circuit 30, where the fuse signals FIO0, FIO1 and PA are supplied.
Generate IR. The fuse signals FIO0, FIO1 and PAIR output from the fuse circuit 30 are supplied to the IO selection circuit 10 having the configuration of FIG.
After being converted to SEL0 to IOSEL7, it is supplied to the selector 28 of the column redundancy circuit 20 to repair the pair failure.

This embodiment is characterized in that the IO selection circuit 10 is provided with a logic of an upper pair (or a lower pair). As a result, in this embodiment, N = 8, that is, the number of IOs is 8 (x8 configuration), so the number of fuses required for repairing all the pair defects is 3 (= log ₂
8) and can be reduced compared to the conventional four. However, the number of fuses required for the enable signal ENA is excluded.

FIG. 3 is a circuit diagram of a main part of an example of the fuse circuit 30. The fuse circuit 30 is a circuit that outputs one fuse signal, and has a P-channel transistor 31 and an N-channel transistor 32 that form a CMOS, the input signal PON of which is input to the gate, a source of the transistor 31, and a high potential side. A fuse 33 connected to a power supply terminal and inverters 35 and 36 connected in cascade to a common drain connection terminal of the transistors 31 and 32
And an N-channel transistor 34 whose drain is connected to the common drain connection terminal of the transistors 31 and 32 and the input terminal of the inverter 35, and whose gate is connected to the output terminal of the inverter 35.

One of the fuse signals FIO0, FIO1 and PAIR is output to the output terminal of the inverter 36. In other words, the fuse circuit 30 has a total of three circuits in FIG. 3 corresponding to the three fuses, and separately detects whether or not each of the three fuses is blown to detect the fuse signal FIO0, It is configured to output FIO1 or PAIR separately.

The input signal PON is a signal which is temporarily activated when the power is turned on. Fuse signals FIO0 and FIO1 generated by the fuse circuit 30 are signals for selecting two defective IOs from eight IOs. The remaining fuse signal P generated by the fuse circuit 30
The AIR is a signal for selecting whether the inter-IO defect is between the high-order IO or the low-order IO.

The operation of FIG. 3 will be described. The input signal PON becomes the high level for a moment only when the power of the DRAM is turned on, and the fuse information is latched. The input signal PON is always at the low level during the operation of the DRAM. That is, when the fuse 33 is not blown (when the fuse is on), the transistor 32 turns on when the input signal PON goes high, the output signal of the inverter 35 goes high, and the transistor 34 turns on. ,
The output fuse signal of the inverter 36 is held at low level. After that, since the input signal becomes low level, the transistor 32 is turned off, the transistor 31 is turned on, and the output fuse signal of the inverter 36 becomes high level.

On the other hand, when the fuse 33 is blown (when the fuse is off), the source terminal of the transistor 31 is disconnected from the high-potential-side power supply terminal, so that the transistor 32 is turned on when the input signal PON becomes high level. Is turned on, the output signal of the inverter 35 becomes high level, the transistor 34 is turned on, and the inverter 36
The output fuse signal of is held at a low level. After that, even if the input signal goes low, the transistor 3
Since the source terminal of 1 is disconnected from the power supply terminal on the high potential side, the output fuse signal of the inverter 36 is held at a low level.

Returning to FIG. 2, the word line WL will be described.
The white circles at the intersections of 0, WL1 and the bit lines BLT / N0 to 7 indicate memory cells. Bit line BLT / N0-7
Are connected to the sense amplifier array (SA) 22. This sense amplifier array (SA) 22 is a Y decoder array (YD).
23 is connected to the sense amplifier array (S
A) 22 128 units, Y decoder row (YD) 23 16 units
A stand is provided. The Y decoder array (YD) 23 is connected to the data amplifier (DA) 26. The data amplifier 26 is from the first bit DA0 to the eighth bit DA7.
There are 8 units. DA0 to DA7 are IO buses IO0 to I
It is connected corresponding to O7. Further, the IO bus is connected to the input / output buffer 29.

On the other hand, a redundant sense amplifier (SSA) 24, a redundant Y decoder (SYD) 25 connected thereto, and a redundant data amplifier (SDA) 27 for repairing the IO pair.
A selector 28 for selecting data from the redundant data amplifier (SDA) 27, a fuse circuit 30, and an IO selection circuit 10 are provided. The selector 28 is connected to the input / output buffer 29 via the IO bus (IO0 to IO7).

The word line WLO is activated and the word line W
The data of all the memory cells on L0 are read out to the bit line, and detected and amplified by the sense amplifier row 22. In the x8 configuration, of the 128 bits of the sense amplifier array 22,
8 bits (BLT selected by the Y decoder row 23)
/ N0 to 7) are transferred to the data amplifier 26 (DA0 to DA7), amplified here, and then output through the IO bus and the data input / output buffer 29.

In the DRAM having this structure, the bit line B
When there is a pair failure due to a short circuit between LT / N6 and BLT / N7, IO0 to 7 are assigned to the bit line pairs BLT / N0 to 7, respectively, so that a pair failure between the IO buses 6 and 7 is caused. Occur. Therefore, column redundancy repairs the IO pair failure. The data of the redundant memory cell is the redundant sense amplifier 24 and the redundant data amplifier 2.
Amplified by 7.

An IO selection circuit 1 to be described later in this embodiment
When a pair failure occurs between the IO buses 6 and 7 due to 0, the IO selection signals IOSEL6 and IOSEL7 are activated, and the data to be output to the IO buses 6 and 7 is amplified by the two redundant data amplifiers 27. Is selected by the selector 28 and output to the IO bus. At this time, DA6 and DA7 of the normal data amplifier 26 are separated from the IO buses 6 and 7 (IO6, 7) by a stop signal to prevent data racing (not shown).

Next, the configuration and operation of the IO selection circuit 10 will be described in more detail with reference to FIG. In FIG. 1, it is assumed that the memory has eight IO lines. As shown in the figure, two-input NAND circuits 13 ₁ and 13 _{2 to} which the fuse signal FIO0 is input to one input terminal, and a signal obtained by inverting the fuse signal FIO0 by the inverter 11 are input to one input terminal 2 Input NAND circuits 13 ₃ and 1
3 and ₄ . The fuse signal FIO1 is input to the other input terminals of the two-input NAND circuits 13 ₁ and 13 ₃ , and the signal obtained by inverting the fuse signal FIO1 by the inverter 12 is input to the other input terminals of the NAND circuits 13 ₂ and 13 _4. It

Further, the 2-input NOR circuits 16 ₂ , 16 ₄ and 1 to which the fuse signal PAIR is inputted to one of the input terminals.
6 ₆ and 16 _8, and 2-input NOR circuit _{16 1,} 16 3, 16 ₅ and 16 ₇ inverted signal is input to one input terminal is provided a fuse signal PAIR inverter 15. The 2-input NOR circuit 17 ₁ is the NOR circuit 1
6 ₁ and 16 ₂ of the output signal is input, two-input NOR circuit 17 ₂ is the output signal of the NOR circuit 16 ₃ and 16 ₄ are input, the 2-input NOR circuit 17 ₃ NOR circuit 16 ₅
And 16 ₆ output signal is input, two-input NOR circuit 1
The output signals of the NOR circuits 16 ₇ and 16 ₈ are input to 7 ₄ .

Further, the signals obtained by the enable signal ENA through the inverter 18 are supplied to the two-input NOR circuits 19 _{1 to} 19 ₈ which are respectively input to one input terminal. The output signal of NAND circuit 13 ₁ is input to the other input terminal of the NOR circuit ₁₆ 1, 16 ₈ and 19 _1, the output signal of NAND circuit 13 _2, NOR circuit 16
Input to the other input terminal of ₂ , 16 ₃ and 19 ₃ and N
The output signals of the AND circuit 13 ₃ are NOR circuits 16 ₄ and 1
6 is inputted to the ₅ and 19 ₅ other input terminal of, NAND
The output signal of the circuit 13 ₄ is inputted to the other input terminal of the NOR circuit ₁₆ 6, 16 ₇ and 19 _7. NOR circuit 1
Fuse signal PAIR is input to the 6 ₈ the other input terminal of the. Furthermore, the output signal of the NOR circuit _{17 1,} 17 2, 17 ₃ and 17 _4, 2-input NOR circuit ₁₉ 2, 19
_4, 19 is input to the ₆ and 19 ₈ other input terminal of the.

Next, the operation of this embodiment will be described. In this embodiment, two adjacent sets of columns are always replaced. When repairing a pair defect between IO6 and IO7, a predetermined fuse is turned on or off corresponding to the defective pair IO6 and IO7. In this case, the output fuse signals FIO0 and FIO1 of the fuse circuit 30 are both set to the low level. Then, among the NAND circuits 13 _{1 to} 13 ₄ in the IO selection circuit 10 of FIG.
Only the output signal of ₄ becomes the low level, and the NAND circuit 1
Each of the output signals 3 _{1 to} 13 ₃ becomes high level.

Therefore, when the enable signal ENA is activated, the NOR circuits 19 ₁ , 19 ₃ and 19 ₅ to which the output signals of the NAND circuits 13 ₁ , 13 ₂ and 13 ₃ are input.
Output signals IOSEL0, IOSEL2 and IOSE of
L4 respectively a low level, NAND circuit 13 ₄
The output signal I of the NOR circuit 19 ₇ the output signal of the input
OSEL6 becomes high level. That is, IO6 is selected from four even IO lines (IO0, IO2, IO4, IO6).
Is selected.

Since IO7 is a higher IO than IO6, a predetermined fuse is turned on, and the fuse signal PA
IR is set to high level. As a result, the NOR circuit 1
Of the 7 _{1 to} 17 ₄ , only the output signal of the NOR circuit 17 ₄ becomes high level, so that when the enable signal ENA is activated, the output signals of the NOR circuits 17 ₁ , 17 ₂ and 17 ₃ are input. NOR circuits 19 ₂ , 19 ₄ and 19
₆ output signals IOSEL1, IOSEL3 and IOS
EL5 Each goes low, NOR circuit 17 ₄
The output signal I of the NOR circuit 19 ₈ the output signal of the input
OSEL7 becomes high level. That is, the IO7 of the upper pair of the above selection IO6 is selected.

In this way, the IO selection signals IOSEL6 and IOSEL7 are set to the high level from the IO selection circuit 10 and transferred to the selector 28 of FIG. As a result, the selector 28 selects the output signal of the two redundant data amplifiers 27 that amplifies the data to be output to the IO buses 6 and 7 and outputs it to the IO bus. At this time, the DA6 and DA7 of the normal data amplifier 26 are inactive (not shown).

In the case of a failure between the IO buses 5 and 6,
Output fuse signals FIO0 and FI of the fuse circuit 30
Both O1 are set to the low level, and as described above, IO
6 (set IOSEL6 to high level), and
The remaining fuses are also turned off and the fuse signal PAIR is set to the low level, whereby the IO selection signal IOSEL5
Can be activated.

As described above, when the fuse signal PAIR is at the high level, the upper I for one IO selection signal IOSEL6 activated by the fuse signals FIO0 and FIO1.
The IO selection signal IOSEL7 that selects the O-pair IO7 can be activated, and when the fuse signal PAIR is low level, I
The IO selection signal IOSEL5 that selects the lower IO pair IO5 for the O selection signal IOSEL6 can be activated.

When the fuse signal FIO0 is low level and the fuse signal FIO1 is high level, the IO selection signal IOSEL4 is activated and the fuse signal FIO is
When 0 is a high level and the fuse signal FIO1 is a low level, the IO selection signal IOSEL2 is activated, and when both the fuse signals FIO0 and FIO1 are a high level, the IO selection signal IOSEL0 is activated. And
When the fuse signal PAIR is at the high level, the IO selection signal of the upper pair is at the low level, and when it is at the low level, the IO pair of the lower pair is
The selection signal is activated. Also, enable signal ENA
Is activated when the address of the Y switch to be replaced is input.

Next, another embodiment of the present invention will be described. In the above embodiment, the column redundancy circuit is applied to the IO selection circuit, but this embodiment is applied to the row redundancy circuit for repairing a pair defect (short circuit or the like) of word lines. FIG. 4 shows a schematic overall configuration diagram of another embodiment of the device of the present invention.

In FIG. 4, the row redundancy circuit 6
Reference numeral 0 is a circuit that replaces two consecutive word line defects (word line short circuit defects) with two spare word lines (SWL). In the figure, in the memory cell portion of the white circles, the spare word driver for row redundancy through an even number-th spare word lines (0,2,4,6) (SW
Is connected to the D) 61, the odd-numbered spare word lines (1,
3, 5, and 7) are connected to a spare redundancy word driver (SWD) 62 for row redundancy.

The word line is selected by the word drivers 63 and 64, and the data from the memory cell on the selected word line is detected by the sense amplifier 65 via the bit line.
It is amplified and output. Here, when a short circuit between word lines occurs at the position indicated by X in FIG. 4, the short circuit between word lines is relieved by replacing with two spare word lines in the row redundancy circuit 60.

Here, the address for selecting the word line is 7 bits X0 to X6, and the least significant X0 among them is the address for selecting the even (EVEN) spare word line or the odd (ODD) spare word line. To do. In this embodiment, the total number of spare word lines is eight. First
The spare word line (SWL) selection circuit 51 of the
Signals SWLSEL0, SWLSEL for selecting one spare word line out of four spare word lines
2, SWLSEL4, SWLSEL6
SEL0, 2, 4, 6)) is output.

The second spare word line (SWL) selection circuit 52 has fuse signals FSEL0, FSEL2, FSEL4, FSEL6 output from the SWL selection circuit 51.
(This will be referred to as FSEL 0, 2, 4, 6)
And a PAIR signal and a PAIRB signal, which are fuse signals output from the FPAIR circuit 53, as inputs, and one of four odd (ODD) spare word lines
Signals SWLSEL1, S for selecting a spare word line of a book
WLSEL3, SWLSEL5, and SWLSEL7 (which will be referred to as SWLSEL1, 3, 5, and 7) are output.

FIG. 5 is a circuit diagram of a main part of an example of the SWL selection circuit 51 shown in FIG. In the case of eight spare word lines, the SWL selection circuit 51 of FIG. 4 has a configuration in which four circuits shown in FIG. 5 are provided in parallel. In FIG. 5, twelve N-channel field effect transistors Q1 to
Each of the drains of Q12 has one fuse F01 to F0.
6, the drain of the P-channel field effect transistor Q0 and the input terminal of the inverter I1 are commonly connected via F11 to F16.

The block selection signal BLKSEL is applied to the gate of the transistor Q0. The block selection signal BLKSEL is a signal for selecting a word line block and is low active. That is, since the transistor Q0 is off when the block selection signal BLKSEL is at high level, all the transistors Q1 to Q12 are off, and the SWL selection circuit 51 is inactive.

On the other hand, since the transistor Q0 is turned on when the block selection signal BLKSEL is at low level,
The transistors Q1 to Q12 are turned on or off depending on the logic values of the gate input word line addresses X1 to X6 and X1B to X6B and whether or not the fuses F01 to F06 and F11 to F16 connected to the drains thereof are blown. (That is, the SWL selection circuit 51 enters the operating state). F01 to F06 and F11 to F16 are six sets of complementary fuses. Also, X1 to X6 and X1B to X6B
Are the six complementary word line addresses. The complementary structure is provided to prevent malfunctions when word addresses are all 0's.

For example, a 6-bit word line address X1
When replacing one word line whose X6 is "000101", fuses F01, F02, F03, F0
4, F05, and F06 are turned on, on, on, off, on, and off, respectively, and among the fuses F11 to F16, F
14 and F16 are turned on. That is, the fuse F0
4, F06, F11, F12, F13 and F15 are blown out.

On the other hand, the above word line addresses X1 to X6
= 000101, the transistors Q1 to Q1
Of Q12, the fused fuses are connected to the drains of transistors Q4, Q6 to Q9, and Q11.
Even if a high-level address signal is applied to their gates, no current flows through them, and the remaining unblown fuses are connected to the drain of the transistor Q.
1-Q3, Q5, Q10, and Q12 are turned off by applying a low-level address signal to their gates, so that no current flows through these transistors, so that the input signal of the inverter I1 becomes high level. .

On the other hand, when a word address which is not replaced is input, a current flows through any one or more of the transistors Q1 to Q12, so that the input signal of the inverter I1 becomes low level. That is, the input signal of the inverter I1 becomes high level only when the word address to be replaced is input,
At this time, a high-level signal is applied to one input terminal of the 2-input NAND circuit NA1 via the inverter I2, and high-level fuse signals FSEL0, 2, 4, 6 indicating a selection signal are output. .

The address signal X0B input to the other input terminal of the 2-input NAND circuit NA1 is a signal having a phase opposite to that of the address signal X0 for selecting the word driver 61 (63) or 62 (64) to which the word line belongs. Therefore, when X0 is at low level (thus, when the address signal X0B is at high level), the word driver 61 (63) is selected. When the word address to be replaced is input and when the address signal X0B is at high level, the NAND circuit NA1 outputs the high-level selection signals SWLSEL0, 2, 4, 6 through the inverter I3.

FIG. 6 is a circuit diagram showing an example of a part of the FPAIR circuit 53 shown in FIG. In the case of eight spare word lines, the FPAIR circuit 53 of FIG. 4 has a configuration in which three circuits shown in FIG. 6 are provided in parallel. The circuit shown in FIG. 6 has an input signal P
A P-channel transistor 72 and an N-channel transistor 73 forming a CMOS, whose ONA is respectively input to the gate, a fuse 71 connected to the source of the transistor 72 and a high potential side power supply terminal, and a transistor 72.
Inverters 74 and 75 connected in series to the common drain connection terminals of the inverters 73 and 73, drains connected to the common drain connection terminals of the transistors 72 and 73 and the input terminal of the inverter 74, and gates connected to the output terminals of the inverter 74. An N-channel transistor 76 and an inverter 7 having an input terminal connected to the output terminal of the inverter 75.
It is composed of 7 and 7.

One of the upper pair fuse signals PAIR1, PAIR3 and PAIR5 is output to the output terminal of the inverter 75, and the lower pair fuse signals PAIRB1 and PAIR are output to the output terminal of the inverter 76.
One fuse signal of B3 and PAIRB5 is output.

The input signal PONA is a signal which is temporarily activated when the power is turned on. When the upper pair fuse signals PAIR1, PAIR3, and PAIR5 output from the FPAIR circuit 53 including three circuits of FIG. 6 are active (here, high level), one word selected by the SWL selection circuit 51 One word line adjacent to the upper side of the line is selected by the SWL selection circuit 52,
When the lower pair fuse signals PAIRB1, PAIRB3, and PAIRB5 are active (here, high level), one word line adjacent to the lower side of one word line selected by the SWL selection circuit 51 is connected to the SWL selection circuit 5.
Select by 2.

Since the circuit of FIG. 6 is a fuse circuit having substantially the same structure as that of the fuse circuit shown in FIG. 3, its detailed operation will be omitted, but the input signal PONA is DRAM.
The signal is high level for a moment only when the power is turned on, and is always low level thereafter. At this time, the fuse 71
Is not blown (when the fuse is on),
Output of inverter 75 Upper pair fuse signal PAIR
1, PAIR3 or PAIR5 is held at a high level, and the output lower pair fuse signal PAI of the inverter 77 is output.
RB1, PAIRB3 or PAIRB5 is held at a low level. When the fuse 71 is blown (when the fuse is off), the upper pair fuse signal PAIR1, PAIR3, or PAIR5 is held at the low level, which is opposite to the above, and the output lower pair fuse signal PAIRB1, PAIRB3 or the output of the inverter 77 is held. PAIRB5 is held at high level.

FIG. 7 shows a circuit diagram of an example of the SEL selection circuit 52 shown in FIG. This SEL selection circuit 52 has a 2-input N
AND circuits 81 _{1 to} 81 ₆ , inverters 82 _{1 to} 82 ₆ , 2
Input NOR circuits 83 _{1 to} 83 ₃ , NOR circuits 83 _{1 to} 83 ₃
Two-input NAND circuits 85 _{1 to} 85 ₄ that take the logical product of the output signal of the above and the word address signal X0, and the NAND circuit 8
The polarities of the output signals of 5 _{1 to} 85 ₄ are separately inverted, and the odd side spare word line selection signals SWLSEL1, SWLSEL3,
It is composed of inverters 86 ₁ to 86 ₄ which output SWLSEL5 and SWLSEL7.

The SWL selection circuit 52 outputs spare word line selection signals SWLSEL1, SWLSEL3, SWLSEL5 and SWLSEL7 indicating an upper pair or a lower pair with respect to the output fuse signals FSEL0, 2, 4, 6 of the SWL selection circuit 51. In this circuit, for example, the spare word line 2 is selected, the fuse signal FSEL2 is at a high level, and the upper pair signal PAIR1 from the FPAIR circuit 53 is at a high level (at this time, the lower pair signals PAIRB3 and PAIRB5 are high). Level and all other signals are low), the inverter 86
Since only the output selection signal SWLSEL3 of ₂ is high level and the other selection signals SWLSEL1, 5, 7 are low level, the adjacent spare word line 3 on the upper side of the spare word line 2 is
Is selected.

Similarly, the spare word line 4 is selected, the fuse signal FSEL4 is at a high level, and the lower pair signal PAIRB3 from the FPAIR circuit 53 is at a high level (at this time, the lower pair signals PAIRB1 and PAIRB).
When AIRB5 is high level and all other signals are low level), the output selection signal SW of the inverter 86 ₂
Only LSEL3 is high level and other selection signal SWLSEL
Since 1, 5, 7 are low bells, the adjacent spare word line 3 on the lower side of the spare word line 4 is selected.

In a row redundancy circuit having eight spare word lines, the conventional circuit requires four SWL selection circuits in FIG. 5, four on the even side and four on the odd side, so that the number of fuses is 96 (= 12 x 8) will be required. Alternatively, if only four SWL selection circuits shown in FIG. 5 are used and word lines are replaced by two lines (0-1, 2-3, 4-5, 6-7), the words shown in FIG. If the line is defective, S
Since it is necessary to use two pairs of WL0-1 and SWL2-3, the replacement efficiency becomes poor.

On the other hand, in the row redundancy circuit 60 having eight spare word lines of this embodiment, the concept of the upper pair and the lower pair is used, and the SW of FIG.
Four L selection circuits on the even side and the FPAIR circuit 5 shown in FIG.
The number of fuses is 51 (= 12 × 4 +) because the number 3 is three and the SWL selection circuit 52 shown in FIG. 7 is one.
3) is sufficient, and the replacement efficiency can be improved with a significantly smaller number of fuses than the conventional 96 circuits. When the number of spare word lines is M and the word address is K bits, the number of fuses is M (K-1) in this embodiment.
It can be represented by + (M / 2) -1.

Note that the present invention is not limited to DRAM, but IO
It can be applied to all semiconductor memory devices that replace a line or a word line.

[0061]

As described above, according to the present invention,
Since the logic of the upper pair (or lower pair) signal is added so that the failure occurrence of two consecutive IO lines or word lines can be remedied, it is possible to improve the failure remedy efficiency with a small number of fuses. A semiconductor memory device having a larger number of lines or word lines can improve the efficiency of repairing defects as compared with the conventional case. Therefore, a semiconductor memory device having a larger number of IO lines or word lines can have a smaller chip size than the conventional one.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a main part of the present invention.

FIG. 2 is a schematic overall configuration diagram of an embodiment of the device of the present invention.

FIG. 3 is a circuit diagram of a main part of an example of a fuse circuit in FIG.

FIG. 4 is a schematic overall configuration diagram of another embodiment of the device of the present invention.

5 is a main part circuit diagram of an example of a first SWL selection circuit in FIG. 4. FIG.

6 is a main part circuit diagram of an example of an FPAIR circuit in FIG.

7 is a circuit diagram of an example of a second SWL selection circuit in FIG.

FIG. 8 is a circuit diagram of an example of a conventional main part.

[Explanation of symbols]

10 IO selection circuit 13 _{1 to} 13 ₄ 2 input NAND circuit 16 _{1 to} 16 ₈ 19 _{1 to} 19 ₈ 2 input NOR circuit 20 Column redundancy circuit 22 Sense amplifier row (SA) 23 Y decoder row (YD) 24 Redundant sense amplifier (SSA) 25 Redundant Y decoder (SYD) 26 Data amplifier (DA) 27 Redundant data amplifier (SDA) 28 Selector 30 Fuse circuits 33, 71, F01 to F06, F11 to F16 Fuses 50, 51, 52 SWL selection circuit 52 FPAIR Circuit 60 Row redundancy circuit 61, 62 Spare word driver (SWD) FIO1, FIO2, PAIR Fuse signal ENA Enable signal IOSEL0 to IOSEL7 IO select signal SWLSEL0 to SWLSEL7 Spare word line select signal

Claims (6)

(57) [Claims] 1. A defective I of a memory having a plurality of IO lines.
A semiconductor memory device having a redundancy circuit for repairing an O line pair, the first memory device corresponding to one defective IO line of the defective IO line pair.
Fuse signal and the other defective I of the defective IO line pair
The O line is the upper IO line or the lower I line of the one defective IO line.
A fuse circuit for generating a second fuse signal indicating whether it is an O line, and the one defect I based on the first fuse signal.
Generating a first IO selection signal corresponding to the O line,
An IO selection circuit for generating a second IO selection signal corresponding to the other defective IO line based on the fuse signal and supplying the second IO selection signal to the selector of the redundancy circuit to repair the defective IO line pair. A semiconductor memory device characterized by: 2. The IO selection circuit is configured to perform a defective 2n (n is a natural number) column IO based on the first fuse signal.
To output the first IO selection signal for selecting
Adjacent to the upper side based on the logical value of the fuse signal of (2
(n + 1) adjacent to the column IO or lower side (2n-
2. The semiconductor memory device according to claim 1, wherein the second IO selection signal for selecting the column IO of 1) is output. 3. The IO selection circuit is an IO of the memory.
When the number of lines is N, (log ₂ N) -1 number of the first
The first IO selection signal is output based on the second fuse signal, and the second IO selection signal is output based on the second fuse signal.
2. The semiconductor device according to claim 1, wherein the IO selection signal is output. 4. A redundancy in which a spare word line is selected by a first spare word driver and a second spare word driver to repair a defective word line pair in a memory having a plurality of IO lines. a semiconductor memory device including a circuit to generate a first spare word line selection signal corresponding to one of the defective word line of the defective word line pair is supplied to the first spare word driver, even-numbered th Or a first selection circuit for selecting one of the odd-numbered spare word lines, and the other defective word line of the defective word line pair is either the upper word line or the lower word line of the one defective word line. A fuse circuit for generating a fuse signal indicating whether or not to correspond to the other defective word line based on the first spare word line selection signal and the fuse signal. A second selection circuit that generates a second spare word line selection signal and supplies the second spare word line selection signal to the second spare word driver to select one of the odd-numbered or even-numbered spare word lines. A semiconductor memory device characterized by: 5. The first selection circuit outputs the first spare word line selection signal for relieving a 2n-th (n is a natural number) defective word line, and the second selection circuit outputs the first spare word line selection signal. Adjacent to the upper side based on the logical value of the fuse signal (2
The second one for selecting the (n + 1) th spare word line or the (2n-1) th spare word line adjacent to the lower side.
5. The semiconductor memory device according to claim 4, wherein the spare word line selection signal is output. 6. When the total number of the spare word lines is M, the first selection circuit is configured such that the upper K−1 bits of the K-bit word address are input to the gates, respectively.
-1 first transistor group, K-1 second transistor group to which the K-1 bit signal having the opposite phase of the higher K-1 bits is respectively input to the gate, and the block address signal are One end is connected to each of the drains of the first and second transistor groups that are switched by being applied to the gate, and the other end is commonly connected to the drains of the select transistors. A circuit section consisting of individual fuses and a logic circuit for outputting a signal taken out from a connection point of the fuse and the selection transistor as the first spare word line selection signal is composed of M / 2 circuits in total, 5. The semiconductor memory device according to claim 4, wherein M / 2 pieces of the first spare word line selection signals are output.