JP3384442B2 - Bonding wire defect detection method - Google Patents
Bonding wire defect detection methodInfo
- Publication number
- JP3384442B2 JP3384442B2 JP18052698A JP18052698A JP3384442B2 JP 3384442 B2 JP3384442 B2 JP 3384442B2 JP 18052698 A JP18052698 A JP 18052698A JP 18052698 A JP18052698 A JP 18052698A JP 3384442 B2 JP3384442 B2 JP 3384442B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- bonding wire
- bonding wires
- semiconductor element
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
- H01L2224/8503—Reshaping, e.g. forming the ball or the wedge of the wire connector
- H01L2224/85035—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball"
- H01L2224/85045—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a corona discharge, e.g. electronic flame off [EFO]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/859—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving monitoring, e.g. feedback loop
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10162—Shape being a cuboid with a square active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、ボンディングワイ
ヤの不良検出方法に関し、特に、高周波デバイスの製造
工程におけるワイヤボンディング不良を検出する方法に
関する。
【０００２】このような半導体装置の例を図４に示す。
半導体素子１には、ソース電極１１、ドレイン電極１２
およびゲート電極１３を有する半導体トランジスタが形
成されている。
【０００３】同図に示すように、ソース電極１１は、Ｅ
字状に形成されており、二つの接続パッド１４，１５を
備えている。ドレイン電極１２は、Ｕ字状に形成されて
おり、一つの接続パッド１６を備え、ゲート電極１３は
一つの接続パッド１７を備えて形成されている。
【０００４】この半導体素子１は、アース端子を兼用し
た大型のソース端子３０上に搭載されており、このソー
ス端子３０の周囲には、二個のソース端子１８，１９と
一個のドレイン端子２０と一個のゲート端子２１とが配
置されている。
【０００５】そして、ソース電極１１の一方の接続パッ
ド１４には、二個のソース端子３０，１８に一本ずつ結
線された二本のボンディングワイヤ２２，２３が共通に
結線されており、他方の接続パッド１５にも、二個のソ
ース端子３０，１９に一本ずつ結線された二本のボンデ
ィングワイヤ２４，２５が共通に結線されている。
【０００６】ドレイン電極１２の一個の接続パッド１６
には、一本のボンディングワイヤ２６で一個のドレイン
端子２０が結線されており、ゲート電極１３の一個の接
続パッド１７には、一本のボンディングワイヤ２７で一
個のゲート端子２１が結線されている。
【０００７】これらボンディングワイヤ２２〜２７を結
線した後、図中破線で示す部分が樹脂封止される。
【０００８】かかる構造の半導体装置は、ゲート電極１
３に印加する電圧でソース電極１１からドレイン電極１
２に通電される電流を制御することができるので、マイ
クロ波の増幅などに利用される。そして、この増幅を低
雑音に実行するため、上述のように、ソース電極１１の
接続パッド１４，１５とソース端子３０，１８，１９と
を各々複数として複数のボンディングワイヤ２２〜２５
で結線し、半導体トランジスタのソースインピーダンス
を低減している。
【０００９】上述のような半導体装置では、製造工程中
のボンディングワイヤ２２〜２７のワイヤボンディング
工程において、ボンディングワイヤに断線やワイヤ無し
等の接続不良が生じることがある。そこで、この断線等
の不良を検査し、不良の生じた半導体装置を除去する必
要がある。
【００１０】通常、ボンディングワイヤの不良の検出
は、樹脂封止後に導通試験で、トランジスタの直流特性
を測定することによりおこなわれる。しかしながら、上
記の半導体装置では、ソース電極１１の二つの接続パッ
ド１４，１５と一個のソース端子３０とが二本のボンデ
ィングワイヤ２２，２４で結線されているため、ボンデ
ィングワイヤ２２，２４の一方が断線していても導通試
験においては正常に動作することとなり、不良を検出で
きず、断線があるにもかかわらず良品と判定されてしま
う。
【００１１】このため、従来このような構造の半導体装
置におけるボンディングワイヤの不良の有無は、マイク
ロ波帯で半導体素子の特性を想定することにより判定し
ていた。
【発明が解決しようとする課題】しかしながら、上述の
マイクロ波帯で半導体素子の特性を想定する従来の方法
を用いるためには、高価なテスターが必要であり、ま
た、測定の所要時間も長くなってしまうという問題があ
る。さらに、治具や工具の管理も煩雑であるため生産性
が低下することになる。
【００１２】したがって、本発明は、上記従来技術の問
題を解決し、確実にかつ簡易にボンディングワイヤの接
続不良の生じた半導体装置を除去しうるボンディングワ
イヤ不良検出方法を提供することを目的とする。
【課題を解決するための手段】本発明の不良ボンディン
グワイヤーの不良方法は、リードフレーム上に搭載され
た半導体素子の一つの電極が複数本のボンディングワイ
ヤでリード端子と接続された半導体装置のボンンディン
グワイヤ不良検出方法であって、前記複数本のボンディ
ングワイヤの接続状態を画像認識手段から求め、少なく
とも一本の前記ボンディングワイヤに接続不良が生じて
いた場合に、前記一つの電極に接続された複数本のボン
ディングワイヤ全てを強制的に断線させるか、または、
前記半導体素子に接続された全てのボンディングワイヤ
を強制的に断線させ、樹脂封止し、導通試験を行って不
良品として検出することを特徴とする。
【００１３】
【００１４】
【００１５】
【００１６】
【００１７】
【００１８】かかる方法によれば、通常の導通試験によ
り確実に不良除去を行なうことが可能となる。したがっ
て、高価なテスターは必要なくなり、所用時間も短縮さ
れる。
【発明の実施の形態】本発明の一実施の形態について図
面を参照して詳細に説明する。
【００１９】図１は本発明を用いた半導体装置の不良除
去装置の一実施例であり、製品の供給部９、送り部８、
収納部１０から成る製品搬送部と、半導体素子１のボン
ディングワイヤの状態を認識し、良否を判定する自動認
識装置６と、カメラ・レンズ７とから成るボンディング
ワイヤ自動認識部と、スパークジェネレータ２と電気ト
ーチ３と電気トーチ上下駆動部４から成るボンディング
ワイヤ切断装置と、全体を制御する制御装置５とから構
成されている。
【００２０】なお、同図に示す半導体素子１は、上述し
た図４に示す構造のものと同一である。
【００２１】供給部９には、リードフレームに複数搭載
され、ワイヤボンディング工程を経た半導体素子１が収
納されており、順次供給部９から送り部８により、カメ
ラ・レンズ７の直下、続いて電気トーチ上下駆動部４の
直下に位置するように送られる。
【００２２】次に、本実施例の動作につき図３の工程フ
ローチャートを参照して説明する。
【００２３】ワイヤボンディング工程後、製品供給部９
から送り出されたリードフレーム上の対象半導体素子１
は、カメラ・レンズ７の下に送られ、ボンディングワイ
ヤ自動認識部で画像情報としてとらえられ、ボンディン
グワイヤ断線やボンディングワイヤ無し等の異常を検出
し、異常が無い場合は良品、複数のボンディングワイヤ
のうち１本でも異常が発見された場合は不良品として良
否を判別される。
【００２４】ここで良品と判定された場合はそのまま製
品収納部１０に収納される。
【００２５】不良品と判定された場合、すなわち少なく
とも一本のボンディングワイヤに断線やワイヤ無し等が
存在する場合には、続いて対象の半導体素子１は送り部
８により電気トーチ３の下に送られる。続いて、ボンデ
ィングワイヤ切断装置において、図２に細部を示すよう
に、半導体素子１のボンディングワイヤ２２〜２７の近
傍に電気トーチ３が下降し、スパークジェネレータ２か
ら通電し電気トーチ３がスパークする。これによって半
導体素子１に結線されている全てのボンディングワイヤ
２２〜２７は強制的に溶融され断線される。その後、不
良品の半導体素子１は、リードフレームに載置されたま
ま、送り部８によって製品収納部１０に収納される。
【００２６】この後、樹脂封止工程において、リードフ
レーム上の半導体素子が樹脂封止される。なお、ここで
は、上記ボンディングワイヤ自動認識部で良品または不
良品のどちらの判定であったかにかかわらず、すべての
半導体素子が樹脂封止される。
【００２７】樹脂封止工程の終了後、導通試験が行われ
る。上記のボンディングワイヤ自動認識部において不良
と判定され強制的にボンディングワイヤを断線されたも
のは、導通試験においてオープン（通電不可）となり、
この工程で不良品として廃棄されることになる。
【００２８】また、通電可能なものは良品として収納さ
れる。
【００２９】このように、ワイヤボンディング工程にお
いて複数のボンディングワイヤのうち少なくとも一本に
断線等の不良が生じた半導体装置を、半導体装置の製造
方法において通常必ず行われる導通試験工程において確
実に不良と判定し除去することが可能となる。
【００３０】また、ボンディングワイヤ自動認識部にお
いて、異常が検出された時点で不良品を廃棄する、すな
わちリードフレームを切断して除去してしまうことも可
能であるが、この場合、それ以降の工程においてその位
置に製品がないということを認識するために、さらに新
たな装置の付加やソフトの変更等が必要となってしまう
ことになり、これまでの設備を有効に使用することがで
きなくなってしまう。これに対し、本実施例によれば、
ボンディングワイヤ自動認識部で不良品と判定されたも
のも、その場では除去せずに後の工程へ送っているた
め、後工程に乱れが生じることがない。すなわち、図１
に示すような装置を付加するだけで、これまでに使用し
ていた設備を変更することなく使用することができると
いう利点がある。
【００３１】なお、本実施例では、電気トーチ３は１対
で配備されているが、これは対象の半導体素子１のボン
ディングワイヤ２２〜２７の配置によって設けるもので
ある。従って回路上ボンディングワイヤが４方向に結線
されてあるものは、実施例の構成に限るものではなく、
さらに電気トーチ３の配置個数を増やしても良い。ま
た、半導体素子１が微小なもので、電気トーチ３が１個
で機能するのであればそれでも問題ない。
【００３２】また、上記実施例では、半導体トランジス
タのソース電極にのみ複数（二つ）の接続パッドを設け
られた例を示したが、他の電極にも複数の接続パッドが
設けられて一つの端子と複数のボンディングワイヤで結
線された半導体装置にも適応可能である。
【００３３】また、本発明は、上記実施例のような一つ
の電極に接続パッドが複数設けられて各接続パッドと一
つのリード端子（実施例におけるソース端子）とが複数
のボンディングワイヤで接続される構造のものに限ら
ず、一つの接続パッドと一つのリード端子とが複数のボ
ンディングワイヤで接続される半導体装置にも適応でき
る。
【００３４】さらに、実施例においては、半導体素子に
接続されているボンディングワイヤのうち一本が不良で
あった場合に、全てのボンディングワイヤを断線させる
構成としているが、これに限らず、不良であるボンディ
ングワイヤが接続されるべき電極およびリード端子と同
じ電極およびリード端子に接続されたボンディングワイ
ヤを全て断線させるだけでもよい。
【発明の効果】以上説明したとおり、本発明によれば、
半導体素子上の一つの電極と一つのリード端子とが複数
本のボンディングワイヤで接続されている半導体装置に
おいて、導通試験前にあらかじめワイヤボンディング工
程で生じたボンディングワイヤの断線やワイヤ無しとい
った不良を判定し不良が生じた半導体装置の全てのワイ
ヤを強制的に断線させておくことにより、導通試験工程
においてワイヤボンディング不良の生じた半導体装置を
確実に不良品と判定し廃棄することが可能となる。
【００３５】また、画像認識により不良と判定されたも
のも、その場でリードフレームから切断・除去をせずに
続く樹脂封止工程に送り、不良品の廃棄は、通常どおり
導通試験後に行なうことにより、これまでに使用してい
た設備を変更する必要がないため、ラインの乱れが生じ
ることもない。
【００３６】なお、本発明は、上記実施例に限定され
ず、本発明の技術思想の範囲内で適宜変更が可能である
ことは明らかである。BACKGROUND OF THE INVENTION [0001] [Technical Field of the Invention The present invention is, bonding wire
In particular, manufacturing of high-frequency devices
A method for detecting wire bonding defects in manufacturing processes
Related. An example of such a semiconductor device is shown in FIG.
The semiconductor element 1 includes a source electrode 11 and a drain electrode 12.
A semiconductor transistor having a gate electrode 13 is formed. As shown in FIG. 1, the source electrode 11 has an E
It is formed in a letter shape and includes two connection pads 14 and 15. The drain electrode 12 is formed in a U shape, and includes one connection pad 16, and the gate electrode 13 includes one connection pad 17. The semiconductor element 1 is mounted on a large source terminal 30 that also serves as a ground terminal. Around the source terminal 30, two source terminals 18, 19 and one drain terminal 20 are provided. One gate terminal 21 is arranged. [0005] Then, one connection pad 14 of the source electrode 11 is commonly connected with two bonding wires 22 and 23 which are connected to the two source terminals 30 and 18 one by one, and the other one is connected. Two bonding wires 24 and 25 connected to the two source terminals 30 and 19 one by one are also connected to the connection pad 15 in common. One connection pad 16 of the drain electrode 12
In this case, one drain terminal 20 is connected by one bonding wire 26, and one gate terminal 21 is connected by one bonding wire 27 to one connection pad 17 of the gate electrode 13. . After these bonding wires 22 to 27 are connected, the portions indicated by broken lines in the figure are sealed with resin. The semiconductor device having such a structure has a gate electrode 1.
3 from the source electrode 11 to the drain electrode 1
Since the current supplied to 2 can be controlled, it is used for microwave amplification and the like. In order to perform this amplification with low noise, a plurality of bonding wires 22 to 25 each including a plurality of connection pads 14 and 15 and source terminals 30, 18 and 19 of the source electrode 11 as described above.
In this way, the source impedance of the semiconductor transistor is reduced. In the semiconductor device as described above, connection failure such as disconnection or no wire may occur in the bonding wire in the wire bonding process of the bonding wires 22 to 27 during the manufacturing process. Therefore, it is necessary to inspect for defects such as disconnection and to remove the defective semiconductor device. Usually, the defect of the bonding wire is detected by measuring the direct current characteristics of the transistor by a continuity test after sealing the resin. However, in the semiconductor device described above, since the two connection pads 14 and 15 of the source electrode 11 and one source terminal 30 are connected by the two bonding wires 22 and 24, one of the bonding wires 22 and 24 is connected. Even if it is disconnected, it will operate normally in the continuity test, a failure cannot be detected, and it will be determined as a good product despite the disconnection. For this reason, conventionally, the presence or absence of bonding wire defects in a semiconductor device having such a structure has been determined by assuming the characteristics of the semiconductor element in the microwave band. However, in order to use the conventional method for assuming the characteristics of a semiconductor device in the above-described microwave band, an expensive tester is required and the time required for measurement is increased. There is a problem that it ends up. Furthermore, since the management of jigs and tools is complicated, productivity is lowered. Accordingly, an object of the present invention is to provide a bonding wire defect detection method capable of solving the above-mentioned problems of the prior art and reliably and easily removing a semiconductor device in which a bonding wire connection defect has occurred. . According to the present invention, there is provided a defect bonding wire defect method according to the present invention, in which a single electrode of a semiconductor element mounted on a lead frame is connected to a lead terminal by a plurality of bonding wires. A bonding wire defect detection method, wherein a connection state of the plurality of bonding wires is obtained from an image recognition means, and is connected to the one electrode when a connection defect occurs in at least one bonding wire. Forcibly disconnect all the bonding wires, or
All bonding wires connected to the semiconductor element are forcibly disconnected, resin-sealed, a continuity test is performed, and a defective product is detected. [0016] According to such a method, it is possible to reliably remove defects by a normal continuity test. Therefore, an expensive tester is not necessary and the required time is shortened. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of a semiconductor device defect removing apparatus according to the present invention. A product supply unit 9, a feed unit 8,
A product conveyance unit comprising a storage unit 10; an automatic recognition device 6 for recognizing the bonding wire state of the semiconductor element 1 to determine whether it is acceptable; an automatic bonding wire recognition unit comprising a camera and a lens 7; The apparatus comprises a bonding wire cutting device comprising an electric torch 3 and an electric torch vertical drive unit 4 and a control device 5 for controlling the whole. The semiconductor element 1 shown in the figure is the same as that of the structure shown in FIG. A plurality of semiconductor elements 1 mounted on a lead frame and subjected to a wire bonding process are accommodated in the supply unit 9, and sequentially supplied from the supply unit 9 to the feed unit 8 directly below the camera lens 7 and then electrically. It is sent so as to be located directly under the torch vertical drive unit 4. Next, the operation of this embodiment will be described with reference to the process flowchart of FIG. After the wire bonding process, the product supply unit 9
Target semiconductor element 1 on the lead frame sent out from
Is sent under the camera / lens 7 and is detected as image information by the automatic bonding wire recognition unit, and detects abnormalities such as a broken bonding wire or no bonding wire. If any one of them is found to be abnormal, it is determined whether the product is defective. If it is determined that the product is good, it is stored in the product storage unit 10 as it is. If it is determined that the product is defective, that is, if at least one bonding wire is disconnected or no wire is present, the target semiconductor element 1 is subsequently sent under the electric torch 3 by the feed unit 8. It is done. Subsequently, in the bonding wire cutting device, as shown in detail in FIG. 2, the electric torch 3 descends in the vicinity of the bonding wires 22 to 27 of the semiconductor element 1, energized from the spark generator 2, and the electric torch 3 sparks. As a result, all the bonding wires 22 to 27 connected to the semiconductor element 1 are forcibly melted and disconnected. Thereafter, the defective semiconductor element 1 is accommodated in the product accommodating portion 10 by the feeding portion 8 while being placed on the lead frame. Thereafter, in the resin sealing step, the semiconductor element on the lead frame is resin-sealed. Here, all the semiconductor elements are sealed with resin regardless of whether the above-described automatic bonding wire recognition unit determines whether the product is good or defective. After completion of the resin sealing process, a continuity test is performed. If the bonding wire is forcibly disconnected and the bonding wire is forcibly disconnected in the automatic bonding wire recognition unit, the continuity test will be open (energization is not possible)
In this process, it is discarded as a defective product. Those that can be energized are stored as non-defective products. As described above, a semiconductor device in which a defect such as disconnection occurs in at least one of the plurality of bonding wires in the wire bonding process is reliably determined to be defective in the continuity test process normally performed in the semiconductor device manufacturing method. It can be determined and removed. In addition, in the bonding wire automatic recognition unit, it is possible to discard the defective product when the abnormality is detected, that is, to cut and remove the lead frame. In order to recognize that there is no product at that location, it will be necessary to add new equipment or change software, making it impossible to use the existing facilities effectively. End up. In contrast, according to this embodiment,
Even if the bonding wire automatic recognition unit determines that the product is defective, it is not removed on the spot and sent to the subsequent process, so that the subsequent process is not disturbed. That is, FIG.
There is an advantage that it can be used without changing the equipment that has been used so far, simply by adding a device as shown in FIG. In this embodiment, the electric torch 3 is provided as a pair, but this is provided by arranging the bonding wires 22 to 27 of the target semiconductor element 1. Therefore, what is bonded on the circuit in four directions is not limited to the configuration of the embodiment,
Furthermore, the number of electric torches 3 may be increased. If the semiconductor element 1 is very small and the single electric torch 3 functions, there is no problem. In the above embodiment, an example is shown in which a plurality of (two) connection pads are provided only on the source electrode of the semiconductor transistor. The present invention can also be applied to a semiconductor device connected to a terminal by a plurality of bonding wires. In the present invention, a plurality of connection pads are provided on one electrode as in the above embodiment, and each connection pad and one lead terminal (source terminal in the embodiment) are connected by a plurality of bonding wires. The present invention is not limited to such a structure, and can be applied to a semiconductor device in which one connection pad and one lead terminal are connected by a plurality of bonding wires. Further, in the embodiment, when one of the bonding wires connected to the semiconductor element is defective, all the bonding wires are disconnected. However, the present invention is not limited to this. All the bonding wires connected to the same electrode and lead terminal as the electrode and lead terminal to which a certain bonding wire is to be connected may be disconnected. As described above, according to the present invention,
In a semiconductor device in which one electrode on a semiconductor element and one lead terminal are connected by multiple bonding wires, it is determined whether there is a defect such as disconnection of the bonding wire or no wire in the wire bonding process before the continuity test By forcibly disconnecting all the wires of the semiconductor device in which the defect has occurred, it becomes possible to reliably determine that the semiconductor device in which the wire bonding defect has occurred in the continuity test process is a defective product and discard it. In addition, even if the image is judged to be defective by image recognition, it is sent to the subsequent resin sealing process without being cut or removed from the lead frame on the spot, and the defective product is discarded after the continuity test as usual. Therefore, since it is not necessary to change the equipment used so far, the line is not disturbed. It should be noted that the present invention is not limited to the above-described embodiments, but can be modified as appropriate within the scope of the technical idea of the present invention.
【図面の簡単な説明】
【図１】本発明の一実施の形態のボンディングワイヤ不
良検出装置
【図２】図１の一部分の詳細図
【図３】本発明の一実施の形態の工程フローチャート図
【図４】本発明の一実施の形態の半導体装置の平面図
【符号の説明】
１ 半導体素子
２ スパークジェネレータ
３ 電気トーチ
４ 電気トーチ上下駆動部
５ 制御装置
６ 自動認識装置
７ カメラ
８ 製品（リードフレーム）送り部
９ 製品（リードフレーム）供給部
１０ 製品（リードフレーム）収納部
１１ ソース電極
１２ ドレイン電極
１３ ゲート電極
１４，１５，１６，１７ 接続パッド
１８，１９，３０ ソース端子
２０ ドレイン端子
２１ ゲート端子
２２，２３，２４，２５，２６，２７ ボンディング
ワイヤBRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a bonding wire defect detection device according to an embodiment of the present invention. FIG. 2 is a detailed view of a part of FIG. 1. FIG. 3 is a process flowchart of one embodiment of the present invention. FIG. 4 is a plan view of a semiconductor device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Spark generator 3 Electric torch 4 Electric torch up / down drive unit 5 Control device 6 Automatic recognition device 7 Camera 8 Product (Lead Frame) Feed section 9 Product (lead frame) supply section 10 Product (lead frame) storage section 11 Source electrode 12 Drain electrode 13 Gate electrodes 14, 15, 16, 17 Connection pads 18, 19, 30 Source terminal 20 Drain terminal 21 Gate Terminals 22, 23, 24, 25, 26, 27 Bonding wires
───────────────────────────────────────────────────── フロントページの続き (72)発明者 千田 昌男 東京都港区芝三丁目18番21号 日本電気 エンジニア リング株式会社内 (56)参考文献 特開 平６−132371（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Masao Senda NEC, Shiba 3-chome, 18-21, Minato-ku, Tokyo Engineering Co., Ltd. (56) References JP-A-6-132371 (JP, A)
Claims (1)
の一つの電極が複数本のボンディングワイヤでリード端
子と接続された半導体装置のボンンディングワイヤ不良
検出方法であって、前記複数本のボンディングワイヤの
接続状態を画像認識手段から求め、少なくとも一本の前
記ボンディングワイヤに接続不良が生じていた場合に、
前記一つの電極に接続された複数本のボンディングワイ
ヤ全てを強制的に断線させるか、または、前記半導体素
子に接続された全てのボンディングワイヤを強制的に断
線させ、樹脂封止し、導通試験を行って不良品として検
出することを特徴とするボンディングワイヤ不良検出方
法。(57) Claims 1. A method for detecting a bonding wire defect in a semiconductor device in which one electrode of a semiconductor element mounted on a lead frame is connected to a lead terminal by a plurality of bonding wires. Then, the connection state of the plurality of bonding wires is obtained from the image recognition means, and when there is a connection failure in at least one of the bonding wires,
A plurality of bonding wires connected to the one electrode.
All of the semiconductor elements are forcibly disconnected or the semiconductor element is
A bonding wire defect detection method comprising: forcibly disconnecting all bonding wires connected to a child , resin-sealing, and conducting a continuity test to detect a defective product.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18052698A JP3384442B2 (en) | 1998-06-26 | 1998-06-26 | Bonding wire defect detection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18052698A JP3384442B2 (en) | 1998-06-26 | 1998-06-26 | Bonding wire defect detection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000012602A JP2000012602A (en) | 2000-01-14 |
| JP3384442B2 true JP3384442B2 (en) | 2003-03-10 |
Family
ID=16084815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18052698A Expired - Fee Related JP3384442B2 (en) | 1998-06-26 | 1998-06-26 | Bonding wire defect detection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3384442B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5214867B2 (en) * | 2006-09-20 | 2013-06-19 | 東芝シュネデール・インバータ株式会社 | Inverter device |
| JP2013026342A (en) * | 2011-07-19 | 2013-02-04 | Sanken Electric Co Ltd | Nitride semiconductor device |
| JP5357235B2 (en) * | 2011-10-31 | 2013-12-04 | 東芝シュネデール・インバータ株式会社 | Inverter device |
| JP5357234B2 (en) * | 2011-10-31 | 2013-12-04 | 東芝シュネデール・インバータ株式会社 | Inverter device |
| CN112701060B (en) * | 2021-03-24 | 2021-08-06 | 高视科技(苏州)有限公司 | Method and device for detecting bonding wire of semiconductor chip |
-
1998
- 1998-06-26 JP JP18052698A patent/JP3384442B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000012602A (en) | 2000-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5326015A (en) | Wire bonder tail length monitor | |
| JP2009244077A (en) | Substrate inspection device and method | |
| US5058797A (en) | Detection method for wire bonding failures | |
| JP3384442B2 (en) | Bonding wire defect detection method | |
| JPH02222158A (en) | Tape structure applicable to dynamic chip burn-in | |
| JPH0580104A (en) | Manufacture of printed circuit board for motor | |
| JPH0794545A (en) | Wire bonder | |
| JP2000269278A (en) | Burn-in device and semiconductor wafer | |
| JP3908640B2 (en) | Wire bonding method and apparatus | |
| JP3544343B2 (en) | Device for removing defective chips from semiconductor integrated circuits | |
| JPH11243119A (en) | Method and device for wire bonding | |
| JP3878530B2 (en) | Wire bonding method and apparatus | |
| JP6676748B2 (en) | Wire bonding apparatus, circuit for wire bonding apparatus, and method for manufacturing semiconductor device | |
| JPH0621299A (en) | Semiconductor manufacturing device | |
| JP2000021938A (en) | Semiconductor wafer, and method for inspecting semiconductor device | |
| JPH08335616A (en) | Semiconductor device and testing method thereof | |
| JP3760655B2 (en) | Aging equipment | |
| JPH0254944A (en) | Wire bonder | |
| JPS6267830A (en) | Inspection device | |
| JP2000100857A (en) | Method and device for detecting defects in wire bonding device | |
| JPH11163067A (en) | Semiconductor device and manufacture thereof | |
| JP2012134276A (en) | Semiconductor device, method of manufacturing the same, and method of inspecting semiconductor device | |
| JPH06313786A (en) | Inspection device of film | |
| JP3496970B2 (en) | Semiconductor device | |
| KR20050109098A (en) | Automatic recovery method for chip pad open error in semiconductor wire bonding equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20001017 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313115 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071227 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081227 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081227 Year of fee payment: 6 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081227 Year of fee payment: 6 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091227 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091227 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101227 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101227 Year of fee payment: 8 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101227 Year of fee payment: 8 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111227 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111227 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121227 Year of fee payment: 10 |
|
| LAPS | Cancellation because of no payment of annual fees |