JP2012134276A - Semiconductor device, method of manufacturing the same, and method of inspecting semiconductor device - Google Patents

Semiconductor device, method of manufacturing the same, and method of inspecting semiconductor device Download PDF

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JP2012134276A
JP2012134276A JP2010284228A JP2010284228A JP2012134276A JP 2012134276 A JP2012134276 A JP 2012134276A JP 2010284228 A JP2010284228 A JP 2010284228A JP 2010284228 A JP2010284228 A JP 2010284228A JP 2012134276 A JP2012134276 A JP 2012134276A
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test
electrode
substrate
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Ichiro Shiga
一郎 志賀
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Renesas Electronics Corp
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Abstract

PROBLEM TO BE SOLVED: To screen bonding defective items with certainty and with ease.SOLUTION: A semiconductor device has: a semiconductor substrate 105 on which a semiconductor element 102 having a bonding pad 101 is mounted and an input-output terminal 103 and a power supply terminal 104 are formed; an encapsulation resin 111 covering the semiconductor substrate 105, the input-output terminal 103, and the power supply terminal 104; and first and second testing electrodes formed in a region that does not overlap with the semiconductor element 102 in a plan view, in the semiconductor substrate 105, and not covered with the encapsulation resin 111. The bonding pad 101 and the input-output terminal 103 are connected with each other via a bonding wire 106a. The bonding pad 101 and the power supply terminal 104 are connected with each other via a bonding wire 106b. The first testing electrode and the second testing electrode are electrically connected with each other independently of the semiconductor element 102, the input-output terminal 103, and the power supply terminal 104.

Description

本発明は、半導体装置、その製造方法、及び半導体装置の検査方法に関する。   The present invention relates to a semiconductor device, a manufacturing method thereof, and a semiconductor device inspection method.

従来、ワイヤーボンディングを用いて半導体素子を半導体基板に接続する技術が知られている（特許文献１−４）。   Conventionally, a technique for connecting a semiconductor element to a semiconductor substrate using wire bonding is known (Patent Documents 1-4).

特許文献１には、導電体上にチップをダイボンディングして該チップの各パッドとリード端子とを接続する半導体装置が記載されている。特許文献１では、チップ基板への供給電源を取り出し可能なパッドをチップに設け、該パッドとチップをダイボンディングした導電体とを電気的に接続するようにしたことで、より安定した電源供給が行えて電気的特性の安定した半導体装置を提供するものとされている。   Patent Document 1 describes a semiconductor device in which a chip is die-bonded on a conductor to connect each pad of the chip and a lead terminal. In Patent Document 1, a pad capable of taking out the power supply to the chip substrate is provided on the chip, and the pad is electrically connected to a conductor bonded to the chip so that more stable power supply can be achieved. A semiconductor device that can be performed and has stable electrical characteristics is provided.

特許文献２には、半導体基板にワイヤーボンディングを用いて半導体素子を接続する部位を樹脂封止する樹脂封止型半導体装置が記載されている。特許文献２では、ダミーワイヤーでワイヤーを覆い、かつ外側に該ワイヤーより本数を多くし、狭い間隔でダミーワイヤーを張ることで、半導体装置の封止樹脂中に含まれるカーボン粒子によるワイヤー間のリーク不良を低減することができ、また電磁シールド効果を発揮することができ、誤動作を防ぐことができるとされている。   Patent Document 2 describes a resin-encapsulated semiconductor device in which a portion where a semiconductor element is connected to a semiconductor substrate using wire bonding is resin-encapsulated. In Patent Document 2, a wire is covered with a dummy wire, and the number of wires is larger than that of the wire on the outside, and the dummy wire is stretched at a narrow interval, so that the leakage between the wires due to the carbon particles contained in the sealing resin of the semiconductor device. It is said that defects can be reduced, an electromagnetic shielding effect can be exhibited, and malfunction can be prevented.

特許文献３には、半導体チップ同士を金属線で接続するときに、一方の半導体チップ上でワイヤボンドを完了させることなく、近傍にあらかじめ設けられたダミーパッド上でワイヤボンドを完了させる半導体装置が記載されている。こうすることで、特許文献３では、半導体チップのカッターによる破損が防止され、歩留の高い、信頼性の高い半導体装置が得られるとされている。   Patent Document 3 discloses a semiconductor device that completes wire bonding on a dummy pad provided in the vicinity without completing wire bonding on one semiconductor chip when the semiconductor chips are connected by a metal wire. Are listed. By doing so, Patent Document 3 states that a semiconductor chip is prevented from being damaged by a cutter, and a high-reliability semiconductor device with high yield is obtained.

特許文献４には、基板に半導体チップをダイボンディングし、基板と半導体チップの電極間をワイヤーボンディング方式にて実装した半導体装置のリペア方法が記載されている。具体的には、特許文献４には、基板の電極に接続されているワイヤーの付け根部分にワイヤー切断用工具を加圧してワイヤーを切断し、その後、樹脂を加熱して半導体チップと基板との接着強度を低下させた状態で、半導体チップと基板との接着を剥離せしめ、ワイヤーを半導体チップの電極に保持したまま半導体チップを除去することが記載されている。特許文献４では、ワイヤーを除去する工程が不要であると共に配線間のショートなどが生じない、あるいは基板を熱により損傷させることなく半導体チップを除去できるとされている。   Patent Document 4 describes a method for repairing a semiconductor device in which a semiconductor chip is die-bonded to a substrate, and the substrate and the electrodes of the semiconductor chip are mounted by a wire bonding method. Specifically, in Patent Document 4, a wire cutting tool is pressed to the base portion of the wire connected to the electrode of the substrate to cut the wire, and then the resin is heated to bond the semiconductor chip and the substrate. It describes that the adhesion between the semiconductor chip and the substrate is peeled off in a state where the adhesive strength is lowered, and the semiconductor chip is removed while the wires are held on the electrodes of the semiconductor chip. In Patent Document 4, it is said that a step of removing a wire is unnecessary and a semiconductor chip can be removed without causing a short circuit between wirings or damaging the substrate by heat.

特開平９−１２０９７４号公報JP-A-9-120974 特開２００５−１２３３７９号公報JP 2005-123379 A 特開平２−１４６７３９号公報Japanese Patent Laid-Open No. 2-14639 特開平６−１６３６４５号公報JP-A-6-163645

ところで、ワイヤーボンディング工程でボンディング不良が発生した場合、出荷前には不良品として良品と選別される必要がある。そこで、入出力端子用のワイヤーがショートしたり、抜かれてオープンになったりすると、電気的に接続不良となることを利用し、まとまった単位（辺単位など）のワイヤーを倒してショートさせたり、抜いたりして、接続不良を発生させ、電気的テスト工程で、不良品として除去する方法が使われている。   By the way, when a bonding failure occurs in the wire bonding process, it is necessary to select a defective product as a defective product before shipment. Therefore, if the input / output terminal wire is shorted or pulled open, it will cause an electrical connection failure. There is a method in which a defective connection is generated by removing the defective product in the electrical test process.

しかしながら、ショートさせたワイヤー、又は、抜かれたワイヤーに入出力端子用のワイヤーが含まれていない場合は、接続不良を検出することは困難である。また、入出力端子用のワイヤーを目視で判別することは困難である。さらに、ワイヤーの本数や周回数が多い製品では、こうした処置自体に時間を要することに加え、接続不良を確実に発生させることも困難となる。   However, it is difficult to detect a connection failure when the shorted wire or the extracted wire does not include the input / output terminal wire. In addition, it is difficult to visually distinguish the wires for input / output terminals. Furthermore, in a product having a large number of wires and the number of turns, it takes time for such treatment itself, and it is difficult to reliably cause a connection failure.

そこで、ワイヤーボンディング工程で不良品が発見された場合に、後の電気的テスト工程において、簡便な手法で確実に不良品を検出できる技術が求められていた。   Thus, there is a need for a technique that can reliably detect a defective product by a simple method in a subsequent electrical test process when a defective product is found in the wire bonding process.

本発明によれば、
電極パッドを備えた半導体素子が搭載され、外部接続端子が形成された基板と、
前記半導体素子及び前記外部接続端子を覆う封止樹脂と、
前記基板のうち、平面視で前記半導体素子と重ならない領域に形成され、前記封止樹脂で覆われていない第一、第二のテスト用電極と、
を有し、
前記電極パッドと前記外部接続端子とがボンディングワイヤーを介して接続されており、
前記半導体素子及び前記外部接続端子から独立して、前記第一のテスト用電極と前記第二のテスト用電極とが電気的に接続されている、半導体装置が提供される。 According to the present invention,
A substrate on which a semiconductor element including an electrode pad is mounted and an external connection terminal is formed;
A sealing resin covering the semiconductor element and the external connection terminal;
Of the substrate, formed in a region that does not overlap the semiconductor element in plan view, the first and second test electrodes not covered with the sealing resin,
Have
The electrode pad and the external connection terminal are connected via a bonding wire,
A semiconductor device is provided in which the first test electrode and the second test electrode are electrically connected independently of the semiconductor element and the external connection terminal.

また、本発明によれば、
搭載される半導体素子ごとに設けられた一体基板の基板領域に、外部接続端子をそれぞれ形成する工程と、
前記外部接続端子から電気的に独立している第一、第二のテスト用電極を前記一体基板の前記基板領域ごとに形成する工程と、
前記一体基板の前記第一、第二のテスト用電極に重ならない領域に、電極パッドを備えた半導体素子を搭載する工程と、
ボンディングワイヤーを介して前記電極パッドと前記外部接続端子とを接続する工程と、
前記半導体素子及び前記外部接続端子を封止樹脂で覆う工程と、
を含み、
前記電極パッドと前記外部接続端子とを接続する前記工程において、前記第一、第二のテスト用電極は、前記半導体素子に電気的に接続されず、
前記封止樹脂で覆う前記工程において、前記第一、第二のテスト用電極を前記封止樹脂で覆わない、半導体装置の製造方法が提供される。 Moreover, according to the present invention,
Forming each external connection terminal in a substrate region of an integrated substrate provided for each semiconductor element to be mounted;
Forming first and second test electrodes that are electrically independent from the external connection terminals for each of the substrate regions of the integrated substrate;
Mounting a semiconductor element having an electrode pad on a region of the integrated substrate that does not overlap the first and second test electrodes;
Connecting the electrode pad and the external connection terminal via a bonding wire;
Covering the semiconductor element and the external connection terminal with a sealing resin;
Including
In the step of connecting the electrode pad and the external connection terminal, the first and second test electrodes are not electrically connected to the semiconductor element,
In the step of covering with the sealing resin, a method of manufacturing a semiconductor device is provided in which the first and second test electrodes are not covered with the sealing resin.

さらに、本発明によれば、
電極パッドを備えた半導体素子が搭載され、外部接続端子が形成された基板と、
前記半導体素子及び前記外部接続端子を覆う封止樹脂と、
前記基板のうち、平面視で前記半導体素子と重ならない領域に形成され、前記封止樹脂で覆われていない第一、第二のテスト用電極と、
を有し、
前記電極パッドと前記外部接続端子とがボンディングワイヤーを介して接続されており、
前記半導体素子及び前記外部接続端子から独立して、前記第一のテスト用電極と前記第二のテスト用電極とが電気的に接続されている半導体装置を用意するステップと、
前記ボンディングワイヤーを介した前記電極パッドと前記外部接続端子との接続が不良であるとき、前記第一のテスト用電極と前記第二のテスト用電極とを電気的に切断するステップと、
前記第一のテスト用電極と前記第二のテスト用電極とが電気的に切断されているか否かを判断するステップと、
を含み、
判断する前記ステップにおいて、前記第一のテスト用電極と前記第二のテスト用電極とが電気的に切断されていないとき、前記半導体装置を良品と判定し、前記第一のテスト用電極と前記第二のテスト用電極とが電気的に切断されているとき、前記半導体装置を不良品と判定する、半導体装置の検査方法が提供される。 Furthermore, according to the present invention,
A substrate on which a semiconductor element including an electrode pad is mounted and an external connection terminal is formed;
A sealing resin covering the semiconductor element and the external connection terminal;
Of the substrate, formed in a region that does not overlap the semiconductor element in plan view, the first and second test electrodes not covered with the sealing resin,
Have
The electrode pad and the external connection terminal are connected via a bonding wire,
Preparing a semiconductor device in which the first test electrode and the second test electrode are electrically connected independently of the semiconductor element and the external connection terminal;
Electrically disconnecting the first test electrode and the second test electrode when the connection between the electrode pad and the external connection terminal via the bonding wire is defective;
Determining whether the first test electrode and the second test electrode are electrically disconnected; and
Including
In the step of determining, when the first test electrode and the second test electrode are not electrically disconnected, the semiconductor device is determined to be a non-defective product, and the first test electrode and the A method for inspecting a semiconductor device is provided in which the semiconductor device is determined to be defective when the second test electrode is electrically disconnected.

この発明によれば、半導体素子及び外部接続端子から独立して、第一のテスト用電極と第二のテスト用電極とが電気的に接続されている。これにより、ワイヤーボンディング工程で不良品が発見された場合は、第一のテスト用電極と第二のテスト用電極とを電気的に切断することにより、電気的テストを行うことで、第一のテスト用電極と第二のテスト用電極との接続不良を検出することができる。したがって、ワイヤーボンディング工程で発見された不良品を確実かつ簡便に良品から選別することが可能になる。   According to this invention, the first test electrode and the second test electrode are electrically connected independently from the semiconductor element and the external connection terminal. As a result, if a defective product is found in the wire bonding process, the first test electrode and the second test electrode are electrically disconnected, and an electrical test is performed. A connection failure between the test electrode and the second test electrode can be detected. Accordingly, it becomes possible to reliably and easily sort defective products found in the wire bonding process from non-defective products.

本発明によれば、ワイヤーボンディングの不良品を確実かつ簡便に選別することができる。   According to the present invention, defective products of wire bonding can be reliably and easily selected.

第１の実施形態に係る半導体装置を模式的に示した平面図である。1 is a plan view schematically showing a semiconductor device according to a first embodiment. （ａ）は、図１のＡ−Ａ'断面図であり、（ｂ）は、（ａ）の部分拡大図である。(A) is AA 'sectional drawing of FIG. 1, (b) is the elements on larger scale of (a). 実施の形態の半導体装置の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the semiconductor device of embodiment. 第１の実施形態に係る半導体装置の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 図４のＢ−Ｂ'断面図である。It is BB 'sectional drawing of FIG. 第１の実施形態に係る半導体装置の検査方法を説明する図である。It is a figure explaining the test | inspection method of the semiconductor device which concerns on 1st Embodiment. 第１の実施形態に係る半導体装置の検査方法を説明する図である。It is a figure explaining the test | inspection method of the semiconductor device which concerns on 1st Embodiment. 第２の実施形態に係る半導体装置を模式的に示した平面図である。It is the top view which showed typically the semiconductor device which concerns on 2nd Embodiment. （ａ）は、図８のＣ−Ｃ'断面図であり、（ｂ）は、（ａ）の部分拡大図である。(A) is CC 'sectional drawing of FIG. 8, (b) is the elements on larger scale of (a). 第２の実施形態に係る半導体装置の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 図１０のＤ−Ｄ'断面図である。It is DD 'sectional drawing of FIG. 第２の実施形態に係る半導体装置の検査方法を説明する図である。It is a figure explaining the test | inspection method of the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態に係る半導体装置の検査方法を説明する図である。It is a figure explaining the test | inspection method of the semiconductor device which concerns on 2nd Embodiment. 関連する半導体装置を模式的に示した平面図である。It is the top view which showed the related semiconductor device typically. 図１４のＥ−Ｅ'断面図である。It is EE 'sectional drawing of FIG.

以下、本発明の実施の形態について、図面を用いて説明する。尚、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

（第１の実施形態）
図１は、本実施形態の半導体装置を示す模式的な平面図である。また、図２（ａ）は、図１のＡ−Ａ'断面図である。図２（ｂ）は、図２（ａ）の破線で囲んだ領域を拡大した図である。図示するように、本実施形態の半導体装置は、ボンディングパッド（電極パッド）１０１を備えた半導体素子１０２が搭載され、入出力用端子１０３及び電源用端子１０４（外部接続端子）が形成された半導体基板１０５と、半導体素子１０２、入出力用端子１０３及び電源用端子１０４を覆う封止樹脂１１１と、半導体基板１０５のうち、平面視で半導体素子１０２と重ならない領域に形成され、封止樹脂１１１で覆われていない第一、第二のテスト用電極１１０ａ、１１０ｂと、を有する。ボンディングパッド１０１と入出力用端子１０３とがボンディングワイヤー１０６ａを介して接続されており、ボンディングパッド１０１と電源用端子１０４とがボンディングワイヤー１０６ｂを介して接続されている。半導体素子１０２、入出力用端子１０３及び電源用端子１０４から独立して、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に接続されている。 (First embodiment)
FIG. 1 is a schematic plan view showing the semiconductor device of this embodiment. FIG. 2A is a cross-sectional view taken along the line AA ′ of FIG. FIG. 2B is an enlarged view of a region surrounded by a broken line in FIG. As shown in the figure, the semiconductor device of the present embodiment includes a semiconductor element 102 having a bonding pad (electrode pad) 101 and a semiconductor in which an input / output terminal 103 and a power supply terminal 104 (external connection terminal) are formed. A sealing resin 111 that covers the substrate 105, the semiconductor element 102, the input / output terminal 103 and the power supply terminal 104, and a region of the semiconductor substrate 105 that does not overlap with the semiconductor element 102 in plan view. The first and second test electrodes 110a and 110b are not covered with the first and second test electrodes 110a and 110b. The bonding pad 101 and the input / output terminal 103 are connected via a bonding wire 106a, and the bonding pad 101 and the power supply terminal 104 are connected via a bonding wire 106b. The first test electrode 110a and the second test electrode 110b are electrically connected independently of the semiconductor element 102, the input / output terminal 103, and the power supply terminal 104.

図２（ａ）で示すように、半導体基板１０５は、第一の面１ａと、第一の面１ａの反対側に設けられた第二の面１ｂとを有している。半導体素子１０２は、第一の面１ａに搭載されている。また、入出力用端子１０３及び電源用端子１０４もまた、第一の面１ａに搭載されている。一方、第一のテスト用電極１１０ａ及び第二のテスト用電極１１０ｂは、第二の面１ｂに形成されている。半導体基板１０５の第一の面１ａは、封止樹脂１１１で覆われているが、第二の面１ｂは、封止樹脂１１１で覆われていない。   As shown in FIG. 2A, the semiconductor substrate 105 has a first surface 1a and a second surface 1b provided on the opposite side of the first surface 1a. The semiconductor element 102 is mounted on the first surface 1a. The input / output terminal 103 and the power supply terminal 104 are also mounted on the first surface 1a. On the other hand, the first test electrode 110a and the second test electrode 110b are formed on the second surface 1b. The first surface 1 a of the semiconductor substrate 105 is covered with the sealing resin 111, but the second surface 1 b is not covered with the sealing resin 111.

より具体的には、第一の面１ａには、第一、第二のマーク用パッド１０８ａ、１０８ｂが形成されている。マーク用ワイヤー１０７を第一のマーク用パッド１０８ａ及び第二のマーク用パッド１０８ｂにボンディングすることで、第一の面１ａ側で、第一のマーク用パッド１０８ａと第二のマーク用パッド１０８ｂとを接続させることができる。第一、第二のマーク用パッド１０８ａ、１０８ｂは、それぞれ、半導体基板１０５を貫通する第一、第二の貫通電極１０９ａ、１０９ｂを介して、第一、第二のテスト用電極１１０ａ、１１０ｂに接続されている。一方、第一、第二のマーク用パッド１０８ａ、１０８ｂ、及び、第一、第二のテスト用電極１１０ａ、１１０ｂは、いずれも、製品用の配線には接続していない。したがって、マーク用ワイヤー１０７により、半導体素子１０２、入出力用パッド１０３及び電源用端子１０４から独立して、第一のマーク用パッド１０８ａと第二のマーク用パッド１０８ｂとが接続されることになり、これにより、半導体素子１０２、入出力用端子１０３及び電源用端子１０４から独立して、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に接続されることになる。このようにして、本実施形態の半導体装置には、第一、第二のマーク用パッド１０８ａ、１０８ｂと、第一、第二の貫通電極１０９ａ、１０９ｂと、第一、第二のテスト用電極１１０ａ、１１０ｂと、マーク用ワイヤー１０７とで、製品の動作とは電気的に分離した配線構造が設けられている。   More specifically, first and second mark pads 108a and 108b are formed on the first surface 1a. By bonding the mark wire 107 to the first mark pad 108a and the second mark pad 108b, the first mark pad 108a and the second mark pad 108b are formed on the first surface 1a side. Can be connected. The first and second mark pads 108a and 108b are connected to the first and second test electrodes 110a and 110b via the first and second through electrodes 109a and 109b penetrating the semiconductor substrate 105, respectively. It is connected. On the other hand, the first and second mark pads 108a and 108b and the first and second test electrodes 110a and 110b are not connected to the product wiring. Therefore, the first mark pad 108 a and the second mark pad 108 b are connected by the mark wire 107 independently of the semiconductor element 102, the input / output pad 103, and the power supply terminal 104. Thus, the first test electrode 110a and the second test electrode 110b are electrically connected independently of the semiconductor element 102, the input / output terminal 103, and the power supply terminal 104. Thus, the semiconductor device of this embodiment includes the first and second mark pads 108a and 108b, the first and second through electrodes 109a and 109b, and the first and second test electrodes. 110a and 110b and the mark wire 107 are provided with a wiring structure that is electrically separated from the operation of the product.

半導体基板１０５は、特に限定されないが、本実施形態では、ＢＧＡ（Ｂａｌｌ ｇｒｉｄ ａｒｒａｙ）パッケージ用基板を例に挙げて説明する。半導体基板１０５の形状は、特に限定されず、矩形（長方形、正方形）であってもよいし、円形であってもよい。ここでは、矩形のものを例に挙げて説明する。   The semiconductor substrate 105 is not particularly limited, but in the present embodiment, a description will be given using a BGA (Ball Grid Array) package substrate as an example. The shape of the semiconductor substrate 105 is not particularly limited, and may be a rectangle (rectangle or square) or a circle. Here, a rectangular shape will be described as an example.

第一、第二のテスト用電極１１０ａ、１１０ｂは、半導体装置の動作に影響のない位置に配置すればよく、半導体基板１０５の任意の領域に形成させることができるが、半導体素子１０２の形成面（第一の面１ａ）とは反対面（第二の面１ｂ）に形成させることが好ましい。また、製造上簡便に形成させることができるという観点から、図示するように、半導体基板１０５のコーナー部に形成させることがより好ましい。また、第一、第二のマーク用パッド１０８ａ、１０８ｂもまた、半導体装置の動作に影響のない位置に配置すればよく、半導体基板１０５のコーナー部に形成させることが好ましい。また、第一、第二のマーク用パッド１０８ａ、１０８ｂを半導体素子１０２の形成面と同じ面（第一の面１ａ）に形成し、かつ、封止樹脂１１１により第一の面１ａを覆うまでの工程では、マーク用ワイヤー１０７の切断の有無を容易に視認することができる。   The first and second test electrodes 110a and 110b may be arranged at positions that do not affect the operation of the semiconductor device, and can be formed in any region of the semiconductor substrate 105. It is preferable to form it on the surface (second surface 1b) opposite to (first surface 1a). Further, from the viewpoint that it can be formed easily in terms of manufacturing, it is more preferable to form it at the corner portion of the semiconductor substrate 105 as shown in the figure. The first and second mark pads 108 a and 108 b may also be disposed at positions that do not affect the operation of the semiconductor device, and are preferably formed at corner portions of the semiconductor substrate 105. Also, until the first and second mark pads 108 a and 108 b are formed on the same surface (first surface 1 a) as the surface on which the semiconductor element 102 is formed and the first surface 1 a is covered with the sealing resin 111. In this step, the presence or absence of cutting of the mark wire 107 can be easily visually confirmed.

なお、入出力用端子１０３は、半導体基板１０５の入出力用端子であり、電源用端子１０４は、半導体基板１０５の電源用端子である。   The input / output terminal 103 is an input / output terminal of the semiconductor substrate 105, and the power supply terminal 104 is a power supply terminal of the semiconductor substrate 105.

続いて、本実施形態の半導体装置の製造方法について図３〜７を用いて説明する。
まず、図３で示すように、基板領域１０ａ、１０ｂと、スクライブ領域１１とが設けられた一体基板１２を用意する。基板領域１０ａ、１０ｂは、搭載される半導体素子１０２ごとに設けられる。一体基板１２がスクライブ領域１１に沿って切断され、個片化したものが半導体基板１０５であり、換言すると、一体基板１２は、半導体基板１０５の集合体である。
ついで、一体基板１２の基板領域１０ａ、１０ｂごとに入出力用端子１０３及び電源用端子１０４を形成する。また、基板領域１０ａ、１０ｂごとに一体基板１２を貫通する第一、第二の貫通電極１０９ａ、１０９ｂを形成する。そして、一体基板１２の半導体素子１０２の形成面側に露出した第一の貫通電極１０９ａの端部に第一のマーク用パッド１０８ａを形成し、半導体素子１０２の形成面と反対面に露出した第一の貫通電極１０９ａの端部に、第一のテスト用電極１１０ａを形成する。また、一体基板１２の半導体素子１０２の形成面側に露出した第二の貫通電極１０９ｂの端部には、第二のマーク用パッド１０８ｂを形成し、半導体素子１０２の形成面と反対面に露出した第二の貫通電極１０９ｂの端部には、第二のテスト用電極１１０ｂを形成する。したがって、第一、第二のテスト用電極１１０ａ、１１０ｂは、いずれも、入出力用端子１０３及び電源用端子１０４から電気的に独立するように形成される。
その後、基板領域１０ａ、１０ｂの第一、第二のテスト用電極１１０ａ、１１０ｂに重ならない領域に、それぞれ、ボンディングパッド１０１を備えた半導体素子１０２を搭載する。
ついで、ボンディングワイヤー１０６ａを介してボンディングパッド１０１と入出力用端子１０３とを接続し、ボンディングワイヤー１０６ｂを介してボンディングパッド１０１と電源用端子１０４とを接続する。また、第一のマーク用パッド１０８ａと第二のマーク用パッド１０８ｂとをマーク用ワイヤー１０７で接続する。このとき、第一、第二のテスト用電極１１０ａ、１１０ｂは半導体素子１０２に電気的に接続されない。したがって、第一、第二のテスト用電極１１０ａ、１１０ｂは、入出力用端子１０３、電源用端子１０４及び半導体素子１０２から電気的に独立して、第一のテスト用電極１１０ａと第二１１０ｂとが接続されることになる。このようにして、図３で示す基板領域１０ａ、１０ｂには、それぞれ、図１に示す同様な構造が形成される。 Next, the method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.
First, as shown in FIG. 3, an integrated substrate 12 provided with substrate regions 10a and 10b and a scribe region 11 is prepared. The substrate regions 10a and 10b are provided for each semiconductor element 102 to be mounted. The integrated substrate 12 is cut along the scribe region 11 and separated into pieces, which is a semiconductor substrate 105. In other words, the integrated substrate 12 is an aggregate of the semiconductor substrates 105.
Next, the input / output terminal 103 and the power supply terminal 104 are formed for each of the substrate regions 10 a and 10 b of the integrated substrate 12. In addition, first and second through electrodes 109a and 109b penetrating the integrated substrate 12 are formed for each of the substrate regions 10a and 10b. A first mark pad 108a is formed at the end of the first through electrode 109a exposed on the surface of the integrated substrate 12 where the semiconductor element 102 is formed, and the first mark pad 108a is exposed on the surface opposite to the surface where the semiconductor element 102 is formed. A first test electrode 110a is formed at the end of one through electrode 109a. A second mark pad 108b is formed at the end of the second through electrode 109b exposed on the surface of the integrated substrate 12 where the semiconductor element 102 is formed, and is exposed on the surface opposite to the surface where the semiconductor element 102 is formed. A second test electrode 110b is formed at the end of the second through electrode 109b. Accordingly, the first and second test electrodes 110 a and 110 b are both formed so as to be electrically independent from the input / output terminal 103 and the power supply terminal 104.
Thereafter, the semiconductor elements 102 each having the bonding pad 101 are mounted on regions of the substrate regions 10a and 10b that do not overlap the first and second test electrodes 110a and 110b, respectively.
Next, the bonding pad 101 and the input / output terminal 103 are connected via the bonding wire 106a, and the bonding pad 101 and the power supply terminal 104 are connected via the bonding wire 106b. Further, the first mark pad 108 a and the second mark pad 108 b are connected by the mark wire 107. At this time, the first and second test electrodes 110 a and 110 b are not electrically connected to the semiconductor element 102. Therefore, the first and second test electrodes 110a and 110b are electrically independent from the input / output terminal 103, the power supply terminal 104, and the semiconductor element 102, and are connected to the first test electrode 110a and the second test electrode 110b. Will be connected. In this way, the same structure as shown in FIG. 1 is formed in each of the substrate regions 10a and 10b shown in FIG.

ここで、ボンディングワイヤー１０６ａをボンディングパッド１０１及び入出力用端子１０３にボンディングしたり、ボンディングワイヤー１０６ｂをボンディングパッド１０１及び電源用端子１０４にボンディングしたりするとき、ボンディング不良が発生することがある。例えば、図３で示す基板領域１０ａでは、良好にボンディングが行われたが、基板領域１０ｂにおいて、ボンディング不良が発見されたとする。そうすると、基板領域１０ｂでは、手動又は治具を用いるなどしてマーク用ワイヤー１０７を抜き、第一のマーク用パッド１０８ａと第二のマーク用パッド１０８ｂとを電気的にも物理的にも切断する。こうすることで、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に切断されることになる。図４は、切断後の基板領域１０ｂの平面図であり、図５は、図４のＢ−Ｂ'断面図である。   Here, when the bonding wire 106a is bonded to the bonding pad 101 and the input / output terminal 103, or when the bonding wire 106b is bonded to the bonding pad 101 and the power supply terminal 104, a bonding failure may occur. For example, it is assumed that bonding has been performed satisfactorily in the substrate region 10a shown in FIG. 3, but a bonding failure has been found in the substrate region 10b. Then, in the substrate region 10b, the mark wire 107 is pulled out manually or using a jig, and the first mark pad 108a and the second mark pad 108b are electrically and physically cut. . By doing so, the first test electrode 110a and the second test electrode 110b are electrically disconnected. 4 is a plan view of the substrate region 10b after cutting, and FIG. 5 is a cross-sectional view taken along the line BB ′ of FIG.

その後、半導体素子１０２、入出力用端子１０３及び電源用端子１０４を封止樹脂１１１で覆うが、このとき、第一、第二のテスト用電極１１０ａ、１１０ｂは、封止樹脂１１１で覆わない。そして、スクライブ領域１１に沿って基板領域１０ａ、１０ｂごとに一体基板１２を切断する（ダイシング工程）。   Thereafter, the semiconductor element 102, the input / output terminal 103, and the power supply terminal 104 are covered with the sealing resin 111. At this time, the first and second test electrodes 110a and 110b are not covered with the sealing resin 111. And the integrated substrate 12 is cut | disconnected for every board | substrate area | region 10a, 10b along the scribe area | region 11 (dicing process).

ついで、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に切断されているか否かを判断し、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に切断されていない基板領域内に形成された半導体素子１０２を選別する（検査工程）。第一、第二のマーク用パッド１０８ａ、１０８ｂが封止樹脂１１１で覆われていないときは、切断されたマーク用ワイヤー１０７ｂが視認できるので、視覚により、マーク用ワイヤー１０７が切断されているか否かを判断することができる。このため、マーク用ワイヤー１０７が切断されていれば、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に切断されていると判断することができる。   Next, it is determined whether the first test electrode 110a and the second test electrode 110b are electrically disconnected, and the first test electrode 110a and the second test electrode 110b are electrically connected. The semiconductor elements 102 formed in the substrate region that is not cut in the process are selected (inspection process). When the first and second mark pads 108a and 108b are not covered with the sealing resin 111, the cut mark wire 107b can be visually recognized, so whether or not the mark wire 107 is cut visually. Can be determined. Therefore, if the mark wire 107 is cut, it can be determined that the first test electrode 110a and the second test electrode 110b are electrically cut.

また、図６、７で示すように電気的テスト用テスタ３０１を用いた電気的テスト（オープン／ショートテスト）を実行することで、確実に第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとの切断を確認することができる。図６は、基板領域１０ａで形成された半導体素子１０２を個片化して得られた半導体装置の検査工程を説明する図であり、図７は、基板領域１０ｂで形成された半導体素子１０２を個片化して得られた半導体装置の検査工程を説明する図である。こうした電気的テスト用テスタ３０１を用いたテストでは、まず、半導体基板１０５裏面（第二の面１ｂ）に形成された第二のテスト用電極１１０ｂに入力配線３０３を接続し、第一のテスト用電極１１０ａに出力配線３０４を接続する。つまり、第一、第二のテスト用電極１１０ａ、１１０ｂは、電気的テスト用テスタ３０１に接続するための専用部品の役割を有する。そして、電圧印加端子３０２から入力配線３０３に電圧が印加され、入力配線３０３と、第二のテスト用電極１１０ｂと、第二の貫通電極１０９ｂと、第二のマーク用パッド１０８ｂと、マーク用ワイヤー１０７と、第一のマーク用パッド１０８ａと、第一の貫通電極１０９ａと、第一のテスト用電極１１０ａと、出力配線３０４との間にこの順で電流Ｉが流れ、電気的テスト用テスタ３０１の入出力端子（電圧印加端子３０２、電圧計測端子３０５）が接続されるか否かが検査される。   Also, as shown in FIGS. 6 and 7, by performing an electrical test (open / short test) using the electrical test tester 301, the first test electrode 110a and the second test electrode are surely provided. The disconnection with 110b can be confirmed. FIG. 6 is a diagram for explaining an inspection process of a semiconductor device obtained by dividing the semiconductor element 102 formed in the substrate region 10a, and FIG. 7 shows the semiconductor element 102 formed in the substrate region 10b. It is a figure explaining the inspection process of the semiconductor device obtained by singulation. In a test using such an electrical test tester 301, first, the input wiring 303 is connected to the second test electrode 110b formed on the back surface (second surface 1b) of the semiconductor substrate 105, and the first test test is performed. The output wiring 304 is connected to the electrode 110a. That is, the first and second test electrodes 110 a and 110 b have a role of dedicated parts for connecting to the electrical test tester 301. A voltage is applied from the voltage application terminal 302 to the input wiring 303, and the input wiring 303, the second test electrode 110 b, the second through electrode 109 b, the second mark pad 108 b, and the mark wire 107, the first mark pad 108a, the first through electrode 109a, the first test electrode 110a, and the output wiring 304 in this order, the current I flows, and the electrical test tester 301 It is inspected whether or not the input / output terminals (voltage application terminal 302, voltage measurement terminal 305) are connected.

図６で示すように、基板領域１０ａでは、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に切断されていないので、電気的テスト用テスタ３０１の電圧印加端子３０２から印加された電圧により、入力配線３０３とマーク用ワイヤー１０７と出力配線３０４とを介して電流Ｉが流れる。そのため、電気的テスト用テスタ３０１の電圧計測端子３０５において、電圧が計測されることとなる。一方、図７で示すように、基板領域１０ｂでは、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に切断されているため、入力配線３０３を通過した電流Ｉはマーク用ワイヤー１０７で遮断されてしまう。そのため、電気的テスト用テスタ３０１の電圧計測端子３０５では、電圧を計測することができない。したがって、電圧計測端子３０５で電圧が計測されるか否かを調べることにより、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に切断されているかどうかを判断することができる。   As shown in FIG. 6, in the substrate region 10a, the first test electrode 110a and the second test electrode 110b are not electrically disconnected, so that the voltage application terminal 302 of the electrical test tester 301 The applied voltage causes a current I to flow through the input wiring 303, the mark wire 107, and the output wiring 304. Therefore, the voltage is measured at the voltage measurement terminal 305 of the electrical test tester 301. On the other hand, as shown in FIG. 7, since the first test electrode 110a and the second test electrode 110b are electrically disconnected in the substrate region 10b, the current I that has passed through the input wiring 303 is marked. It will be blocked by the wire 107 for use. Therefore, the voltage cannot be measured at the voltage measurement terminal 305 of the electrical test tester 301. Therefore, it is possible to determine whether or not the first test electrode 110a and the second test electrode 110b are electrically disconnected by examining whether or not the voltage is measured at the voltage measurement terminal 305. it can.

このように、視覚又は電気的テストにより、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に切断されていないと判断されたとき、得られた半導体装置を良品と判定する。一方、視覚又は電気的テストにより、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に切断されていると判断されたとき、得られた半導体装置を不良品と判定する。したがって、ここでは、基板領域１０ａから得られた半導体装置は、良品と判定され、基板領域１０ｂから得られた半導体装置は、不良品と判定される。これにより、良品のみを選別して出荷することが可能になる。   As described above, when it is determined by visual or electrical test that the first test electrode 110a and the second test electrode 110b are not electrically disconnected, the obtained semiconductor device is determined to be a non-defective product. To do. On the other hand, when it is determined by visual or electrical test that the first test electrode 110a and the second test electrode 110b are electrically disconnected, the obtained semiconductor device is determined as a defective product. . Therefore, here, the semiconductor device obtained from the substrate region 10a is determined as a non-defective product, and the semiconductor device obtained from the substrate region 10b is determined as a defective product. As a result, it is possible to select and ship only non-defective products.

つづいて、本実施形態の半導体装置の作用効果について説明する。この発明によれば、半導体素子１０２、入出力用端子１０３及び電源用端子１０４から独立して、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとがマーク用ワイヤー１０７で電気的に接続されている。これにより、ワイヤーボンディング工程で不良品が発見された場合は、マーク用ワイヤー１０７を切断することで、容易に第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとを電気的に切断することができ、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に切断されているか否かを視覚的あるいは電気的テストにより確認することができる。したがって、ワイヤーボンディング工程で発見された不良品を確実かつ簡便に選別して、良品から不良品を除去することが可能になる。   Next, functions and effects of the semiconductor device of this embodiment will be described. According to the present invention, the first test electrode 110 a and the second test electrode 110 b are electrically connected by the mark wire 107 independently of the semiconductor element 102, the input / output terminal 103 and the power supply terminal 104. It is connected. Thereby, when a defective product is found in the wire bonding process, the first test electrode 110a and the second test electrode 110b are easily electrically disconnected by cutting the mark wire 107. It can be confirmed by visual or electrical test whether or not the first test electrode 110a and the second test electrode 110b are electrically disconnected. Therefore, it becomes possible to reliably and easily sort out defective products found in the wire bonding process and remove defective products from non-defective products.

図１４には、比較の半導体装置の構造を示す。図１５には、図１４のＥ−Ｅ'断面を示す（９０１：ボンディングパッド、９０２：半導体素子、９０３：入出力用端子、９０４：電源用端子、９０５：半導体基板）。図示するように、マーク用パッド、並びに、これに接続する貫通電極及びテスト用電極を有しない構造では、電気的テスト工程で確実に不良品とするには、良品・不良品の判定が可能な入出力用端子９０３に接続するボンディングワイヤー９０６ａを含めた不良処置が必要となる。しかしながら、ボンディングワイヤーが入出力用端子９０３に接続しているのか、電源用端子９０４（またはグラウンド端子用パッド）に接続しているのかを視覚的に判別するのが困難である。そのため、入出力用端子９０３に接続するボンディングワイヤー９０６ａが含まれる様に、複数のボンディングワイヤー（例えば１辺の全ワイヤ）を倒してショートさせる、または複数のボンディングワイヤーを引き抜いてオープンにすることが行われていた。そのため、ワイヤーの本数や周回数が多くなると不良処置に時間を要し、倒し方が不十分だと不良と検出されない可能性があることが問題とされていた。   FIG. 14 shows a structure of a comparative semiconductor device. FIG. 15 shows a cross section taken along the line EE ′ of FIG. 14 (901: bonding pad, 902: semiconductor element, 903: input / output terminal, 904: power supply terminal, 905: semiconductor substrate). As shown in the figure, a non-defective / defective product can be judged in order to ensure a defective product in the electrical test process with a structure that does not have a mark pad, and a through electrode and a test electrode connected thereto. Defects including the bonding wire 906a connected to the input / output terminal 903 are required. However, it is difficult to visually determine whether the bonding wire is connected to the input / output terminal 903 or the power supply terminal 904 (or the ground terminal pad). For this reason, a plurality of bonding wires (for example, all wires on one side) may be brought down and shorted or a plurality of bonding wires may be pulled open so that the bonding wire 906a connected to the input / output terminal 903 is included. It was done. Therefore, when the number of wires and the number of turns increase, it takes time for the failure treatment, and if the method of overturning is insufficient, there is a possibility that the failure may not be detected.

一方、本実施形態の半導体装置では、第一、第二のテスト用電極１１０ａ、１１０ｂ、第一、第二の貫通電極１０９ａ、１０９ｂ及び、第一、第二のマーク用パッド１０８ａ、１０８ｂを製品動作で使用する入出力用端子１０３及び電源用端子１０４から独立して半導体基板１０５に設けるため、ボンディング不良の半導体装置でのワイヤー処理を短時間で実施することができる。また、本実施形態の半導体装置では、第一、第二のマーク用パッド１０８ａ、１０８ｂを半導体素子１０２の形成面に形成し、製品動作で使用する入出力用端子１０３及び電源用端子１０４から独立して、マーク用ワイヤー１０７により接続するため、ボンディング不良の半導体装置を視覚で識別することができ、さらに、簡便かつ短時間でボンディングの不良品を良品と選別することができる。さらに、不良識別のために必要な処置は、１本のワイヤー（マーク用ワイヤー１０７）を抜くだけなので、処置に掛かる手間はかからず、時間も短く済む。したがって、ボンディング不良品が流出するリスクを確実に低減することが可能になる。   On the other hand, in the semiconductor device of this embodiment, the first and second test electrodes 110a and 110b, the first and second through electrodes 109a and 109b, and the first and second mark pads 108a and 108b are manufactured. Since the semiconductor substrate 105 is provided independently from the input / output terminal 103 and the power supply terminal 104 used in the operation, wire processing in a semiconductor device having a bonding failure can be performed in a short time. In the semiconductor device of the present embodiment, the first and second mark pads 108a and 108b are formed on the formation surface of the semiconductor element 102, and are independent from the input / output terminals 103 and the power supply terminals 104 used in the product operation. Then, since the connection is made by the mark wire 107, it is possible to visually identify the defective semiconductor device, and further, it is possible to sort out the defective bonding device as a non-defective product easily and in a short time. Furthermore, since the treatment required for defect identification is only to pull out one wire (mark wire 107), it does not take time and effort for the treatment. Therefore, it is possible to reliably reduce the risk of a defective bonding product flowing out.

（第２の実施形態）
図８は、本実施形態の半導体装置を示す模式的な平面図である。また、図９（ａ）は、図８のＣ−Ｃ'断面図である。図９（ｂ）は、図９（ａ）の破線で囲んだ領域を拡大した図である。図示するように、本実施形態の半導体装置では、第１の実施形態とは異なり、第一、第二のマーク用パッド１０８ａ、１０８ｂ、マーク用ワイヤー１０７は有しない代わりに、マーク用配線２０７が第一の貫通電極１０９ａと第二の貫通電極１０９ｂとを接続している。これにより、第一のテスト用電極１１０ａと、第二のテスト用電極１１０ｂとがマーク用配線２０７を介して接続されることになる。マーク用配線２０７は、半導体基板１０５の内部に形成されている。その他の構成は、第１の実施形態の半導体装置と同様である。 (Second Embodiment)
FIG. 8 is a schematic plan view showing the semiconductor device of this embodiment. FIG. 9A is a cross-sectional view taken along the line CC ′ of FIG. FIG. 9B is an enlarged view of a region surrounded by a broken line in FIG. As shown in the figure, in the semiconductor device of this embodiment, unlike the first embodiment, instead of having the first and second mark pads 108a and 108b and the mark wire 107, a mark wiring 207 is provided. The first through electrode 109a and the second through electrode 109b are connected. As a result, the first test electrode 110 a and the second test electrode 110 b are connected via the mark wiring 207. The mark wiring 207 is formed inside the semiconductor substrate 105. Other configurations are the same as those of the semiconductor device of the first embodiment.

続いて、本実施形態の半導体装置の製造方法について、図３、１０〜１３を用いつつ、第１の実施形態とは異なる点のみを説明する。
まず、図３で示す一体基板１２を用意し、基板領域１０ａ、１０ｂに、図８に示す同様な構造を形成させる。本実施形態では、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとは半導体基板１０５内のマーク用配線２０７で電気的に接続させるため、ワイヤーボンディング工程でワイヤーによる接続は行わない。そして、例えば、基板領域１０ｂにおいて、ボンディング不良が発見されたとすると、基板領域１０ｂでは、半導体基板１０５の表面のレジストを塗布していない箇所のマーク用配線２０７を手動又は治具を用いるなどして切断して、オープンの状態にする。こうすることで、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとを電気的に切断させることができる。図１０は、切断後の基板領域１０ｂの平面図であり、図１１は、図１０のＤ−Ｄ'断面図である。 Subsequently, the method for manufacturing the semiconductor device according to the present embodiment will be described only with respect to differences from the first embodiment with reference to FIGS.
First, the integrated substrate 12 shown in FIG. 3 is prepared, and the similar structure shown in FIG. 8 is formed in the substrate regions 10a and 10b. In the present embodiment, since the first test electrode 110a and the second test electrode 110b are electrically connected by the mark wiring 207 in the semiconductor substrate 105, the connection by the wire is not performed in the wire bonding process. For example, if a bonding defect is found in the substrate region 10b, the mark wiring 207 in the portion where the resist on the surface of the semiconductor substrate 105 is not applied is manually or used in the substrate region 10b. Disconnect and leave open. By doing so, the first test electrode 110a and the second test electrode 110b can be electrically disconnected. 10 is a plan view of the substrate region 10b after cutting, and FIG. 11 is a cross-sectional view taken along the line DD ′ of FIG.

ついで、半導体基板１０５の第一の面１ａを封止樹脂１１１で覆い、ダイシングを行う。その後、電気的テストにより、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが切断されているか否かを判断し、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが切断されていない基板領域内に形成された半導体素子１０２を選別する。   Next, the first surface 1a of the semiconductor substrate 105 is covered with a sealing resin 111, and dicing is performed. Thereafter, it is determined by electrical test whether the first test electrode 110a and the second test electrode 110b are disconnected, and the first test electrode 110a and the second test electrode 110b The semiconductor element 102 formed in the substrate region that is not cut is selected.

具体的には、図１２、１３で示すように電気的テスト用テスタ３０１を用いた電気的テストを実行し、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとの切断を確認することでボンディングの良不良を選別する。図１２は、基板領域１０ａで形成された半導体素子１０２が個片化して得られた半導体装置の検査工程を説明する図である。図１３は、基板領域１０ｂで形成された半導体素子１０２が個片化して得られた半導体装置の検査工程を説明する図である。こうした電気的テスト用テスタ３０１を用いたテストでは、まず、半導体基板１０５裏面（第二の面１ｂ）に形成された第二のテスト用電極１１０ｂに入力配線３０３が接続され、第一のテスト用電極１１０ａに出力配線３０４が接続される。そして、電圧印加端子３０２から入力配線３０３に電圧が印加され、入力配線３０３と、第二のテスト用電極１１０ｂと、第二の貫通電極１０９ｂとマーク用配線２０７と、第一の貫通電極１０９ａと、第一のテスト用電極１１０ａと、出力配線３０４との間にこの順で電流Ｉが流れ、電気的テスト用テスタ３０１の入出力端子（電圧印加端子３０２、電圧計測端子３０５）が接続されるか否かが検査される。   Specifically, as shown in FIGS. 12 and 13, an electrical test using an electrical test tester 301 is performed to confirm the disconnection between the first test electrode 110a and the second test electrode 110b. This sorts the bonding quality. FIG. 12 is a diagram for explaining the inspection process of the semiconductor device obtained by dividing the semiconductor element 102 formed in the substrate region 10a into pieces. FIG. 13 is a diagram illustrating an inspection process of a semiconductor device obtained by dividing the semiconductor element 102 formed in the substrate region 10b into pieces. In a test using such an electrical test tester 301, first, the input wiring 303 is connected to the second test electrode 110b formed on the back surface (second surface 1b) of the semiconductor substrate 105, and the first test test is performed. An output wiring 304 is connected to the electrode 110a. A voltage is applied from the voltage application terminal 302 to the input wiring 303, and the input wiring 303, the second test electrode 110 b, the second through electrode 109 b, the mark wiring 207, and the first through electrode 109 a The current I flows between the first test electrode 110a and the output wiring 304 in this order, and the input / output terminals (voltage application terminal 302, voltage measurement terminal 305) of the electrical test tester 301 are connected. Whether it is inspected.

図１２で示すように、基板領域１０ａでは、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとの接続が切断されていないので、電気的テスト用テスタ３０１の電圧印加端子３０２から印加された電圧により、入力配線３０３とマーク用配線２０７と出力配線３０４とを介して電流が流れる。そのため、電気的テスト用テスタ３０１の電圧計測端子３０５において、電圧が計測されることとなる。一方、図１３で示すように、チップ領域１０ｂでは、マーク用配線２０７間の接続が切断されているため、電気的テスト用テスタ３０１の電圧印加端子３０２から印加された電圧により、入力配線３０３からの電流Ｉはマーク用配線２０７ｂで遮断されてしまう。そのため、電気的テスト用テスタ３０１の電圧計測端子３０５では、電圧を計測することができない。したがって、電圧計測端子３０５で電圧が計測されるか否かを調べることにより、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に切断されているかどうかを判断することができる。   As shown in FIG. 12, in the substrate region 10a, since the connection between the first test electrode 110a and the second test electrode 110b is not disconnected, the voltage is applied from the voltage application terminal 302 of the electrical test tester 301. Due to the applied voltage, a current flows through the input wiring 303, the mark wiring 207, and the output wiring 304. Therefore, the voltage is measured at the voltage measurement terminal 305 of the electrical test tester 301. On the other hand, as shown in FIG. 13, in the chip region 10b, since the connection between the mark wirings 207 is cut off, the voltage applied from the voltage application terminal 302 of the electrical test tester 301 causes the input wiring 303 to Current I is interrupted by the mark wiring 207b. Therefore, the voltage cannot be measured at the voltage measurement terminal 305 of the electrical test tester 301. Therefore, it is possible to determine whether or not the first test electrode 110a and the second test electrode 110b are electrically disconnected by examining whether or not the voltage is measured at the voltage measurement terminal 305. it can.

このように、電気的テストにより、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に切断されていないと判断されたとき、得られた半導体装置を良品と判定する。一方、電気的テストにより、第一のテスト用電極１１０ａと第二のテスト用電極１１０ｂとが電気的に切断されていると判断されたき、得られた半導体装置を不良品と判定する。したがって、ここでは、基板領域１０ａから得られた半導体装置は、良品と判定され、基板領域１０ｂから得られた半導体装置は、不良品と判定される。これにより、本実施形態においても第１の実施形態と同様に、良品のみを選別して出荷することが可能になる。   As described above, when it is determined by the electrical test that the first test electrode 110a and the second test electrode 110b are not electrically disconnected, the obtained semiconductor device is determined as a non-defective product. On the other hand, when it is determined by the electrical test that the first test electrode 110a and the second test electrode 110b are electrically disconnected, the obtained semiconductor device is determined as a defective product. Therefore, here, the semiconductor device obtained from the substrate region 10a is determined as a non-defective product, and the semiconductor device obtained from the substrate region 10b is determined as a defective product. Thereby, also in this embodiment, it becomes possible to select and ship only non-defective products, as in the first embodiment.

本実施形態においても、第１の実施形態と同様な効果が得られるが、本実施形態では、第１の実施形態とは異なり、第一、第二のマーク用パッド１０８ａ、１０８ｂやマーク用ワイヤー１０７を使用していない。そのため、半導体基板の構成のみを変更だけすればよく、第１の実施形態の技術よりも安価に、ワイヤーボンディング工程の良品と不良品との識別が可能になる。   In this embodiment, the same effect as that of the first embodiment can be obtained. However, in this embodiment, unlike the first embodiment, the first and second mark pads 108a and 108b and the mark wire are used. 107 is not used. Therefore, it is only necessary to change the configuration of the semiconductor substrate, and the non-defective product and the defective product in the wire bonding process can be identified at a lower cost than the technique of the first embodiment.

以上、図面を参照して本発明の実施形態について述べたが、これらは本発明の例示であり、上記以外の様々な構成を採用することもできる。
たとえば、実施の形態では、第一、第二のマーク用電極、第一、第二の貫通電極、及び、第一、第二のテスト用電極をそれぞれ１ずつ有する例のみを挙げて説明したが、これに限定されず、複数有することもできる。
また、実施の形態では、検査工程をダイシング工程の後に行う例を示したが、検査工程は、ワイヤーボンディング工程の後であれば、どのようなタイミングで行ってもよい。
また、実施の形態では、第一、第二のテスト用電極が貫通電極を介して接続される例を挙げて説明したが、第一のテスト用電極と第二のテスト用電極との間は、半導体素子など、製品の動作に影響する部材と電気的に分離されるように接続されていればよく、一般的な配線により、接続されていてもよい。例えば、第１の実施形態では、第一、第二のマーク用パッドと第一、第二のテスト用電極とが直線上に配置されていたが、配線で接続させることにより、第一のマーク用パッド及び第一のテスト用電極の配置や、第二のマーク用パッド及び第二のテスト用電極の配置を直線上にしなくても、これらが接続可能である。したがって、第一、第二のマーク用パッド及び第一、第二のテスト用電極の配置やパターンのバリエーションがさらに豊富になるというメリットが得られる。 As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.
For example, in the embodiment, the first and second mark electrodes, the first and second through electrodes, and the first and second test electrodes have been described as examples only. However, the present invention is not limited to this, and a plurality of them can be provided.
Moreover, although the example which performs an inspection process after a dicing process was shown in embodiment, as long as an inspection process is after a wire bonding process, you may perform it at what timing.
In the embodiment, the first and second test electrodes are connected to each other through the through electrode. However, between the first test electrode and the second test electrode, As long as it is connected so as to be electrically separated from a member that affects the operation of the product such as a semiconductor element, it may be connected by general wiring. For example, in the first embodiment, the first and second mark pads and the first and second test electrodes are arranged on a straight line. Even if the arrangement of the first pad and the first test electrode and the arrangement of the second mark pad and the second test electrode are not linear, they can be connected. Therefore, there can be obtained an advantage that variations in arrangement and pattern of the first and second mark pads and the first and second test electrodes are further abundant.

１ａ 第一の面
１ｂ 第二の面
１０ａ 基板領域
１０ｂ 基板領域
１１ スクライブ領域
１２ 一体基板
１０１ ボンディングパッド
１０２ 半導体素子
１０３ 入出力用端子
１０４ 電源用端子
１０５ 半導体基板
１０６ａ ボンディングワイヤー
１０６ｂ ボンディングワイヤー
１０７ マーク用ワイヤー
１０７ｂ 切断されたマーク用ワイヤー
１０８ａ 第一のマーク用パッド
１０８ｂ 第二のマーク用パッド
１０９ａ 第一の貫通電極
１０９ｂ 第二の貫通電極
１１０ａ 第一のテスト用電極
１１０ｂ 第二のテスト用電極
１１１ 封止樹脂
２０７ マーク用配線
２０７ｂ 切断されたマーク用配線
３０１ 電気的テスト用テスタ
３０２ 電圧印加端子
３０３ 入力配線
３０４ 出力配線
３０５ 電圧計測端子
９０２ 半導体素子
９０３ 入出力用端子
９０４ 電源用端子
９０５ 半導体基板
９０６ａ ボンディングワイヤー
９０６ｂ ボンディングワイヤー
Ｉ 電流 DESCRIPTION OF SYMBOLS 1a 1st surface 1b 2nd surface 10a Substrate area | region 10b Substrate area | region 11 Scribing area | region 12 Integrated substrate 101 Bonding pad 102 Semiconductor element 103 Input / output terminal 104 Power supply terminal 105 Semiconductor substrate 106a Bonding wire 106b Bonding wire 107 Marking wire 107b Cut mark wire 108a First mark pad 108b Second mark pad 109a First through electrode 109b Second through electrode 110a First test electrode 110b Second test electrode 111 Sealing Resin 207 Mark wiring 207 b Cut mark wiring 301 Electrical test tester 302 Voltage application terminal 303 Input wiring 304 Output wiring 305 Voltage measurement terminal 902 Semiconductor element 903 Input / output terminal 904 Power supply terminal 905 Conductor substrate 906a bonding wire 906b bonding wire I Current

Claims (9)

電極パッドを備えた半導体素子が搭載され、外部接続端子が形成された基板と、
前記半導体素子及び前記外部接続端子を覆う封止樹脂と、
前記基板のうち、平面視で前記半導体素子と重ならない領域に形成され、前記封止樹脂で覆われていない第一、第二のテスト用電極と、
を有し、
前記電極パッドと前記外部接続端子とがボンディングワイヤーを介して接続されており、
前記半導体素子及び前記外部接続端子から独立して、前記第一のテスト用電極と前記第二のテスト用電極とが電気的に接続されている、半導体装置。 A substrate on which a semiconductor element including an electrode pad is mounted and an external connection terminal is formed;
A sealing resin covering the semiconductor element and the external connection terminal;
Of the substrate, formed in a region that does not overlap the semiconductor element in plan view, the first and second test electrodes not covered with the sealing resin,
Have
The electrode pad and the external connection terminal are connected via a bonding wire,
A semiconductor device, wherein the first test electrode and the second test electrode are electrically connected independently of the semiconductor element and the external connection terminal. 前記基板は、矩形であり、
前記第一、第二のテスト用電極が前記基板のコーナー部に形成されている、請求項１に記載の半導体装置。 The substrate is rectangular;
The semiconductor device according to claim 1, wherein the first and second test electrodes are formed at corner portions of the substrate. 前記基板は、第一の面と、前記第一の面とは異なる第二の面とを有し、
前記半導体素子が、前記第一の面に搭載されており、
前記第一、第二のテスト用電極が、前記第二の面に形成されている、請求項１又は２に記載の半導体装置。 The substrate has a first surface and a second surface different from the first surface;
The semiconductor element is mounted on the first surface;
The semiconductor device according to claim 1, wherein the first and second test electrodes are formed on the second surface. 前記第一の面に形成された第一、第二のマーク用パッドと、
前記第一のマーク用パッドと第二のマーク用パッドとを接続しているマーク用ワイヤーと、
をさらに有し、
前記マーク用ワイヤーが、前記半導体素子及び前記電極パッドから独立して、前記第一のマーク用パッドと第二のマーク用パッドとを接続することにより、前記第一のテスト用電極と前記第二のテスト用電極とが電気的に接続されている、請求項３に記載の半導体装置。 First and second mark pads formed on the first surface;
A mark wire connecting the first mark pad and the second mark pad;
Further comprising
The mark wire connects the first mark pad and the second mark pad independently of the semiconductor element and the electrode pad, whereby the first test electrode and the second test electrode are connected. The semiconductor device according to claim 3, wherein the test electrode is electrically connected. 前記第一のテスト用電極と、前記第二のテスト用電極とを電気的に接続しているマーク用配線をさらに有し、
前記マーク用配線が前記基板の内部に形成されている、請求項３に記載の半導体装置。 A mark wiring that electrically connects the first test electrode and the second test electrode;
The semiconductor device according to claim 3, wherein the mark wiring is formed inside the substrate. 搭載される半導体素子ごとに設けられた一体基板の基板領域に、外部接続端子をそれぞれ形成する工程と、
前記外部接続端子から電気的に独立している第一、第二のテスト用電極を前記一体基板の前記基板領域ごとに形成する工程と、
前記一体基板の前記第一、第二のテスト用電極に重ならない領域に、電極パッドを備えた半導体素子を搭載する工程と、
ボンディングワイヤーを介して前記電極パッドと前記外部接続端子とを接続する工程と、
前記半導体素子及び前記外部接続端子を封止樹脂で覆う工程と、
を含み、
前記電極パッドと前記外部接続端子とを接続する前記工程において、前記第一、第二のテスト用電極は、前記半導体素子に電気的に接続されず、
前記封止樹脂で覆う前記工程において、前記第一、第二のテスト用電極を前記封止樹脂で覆わない、半導体装置の製造方法。 Forming each external connection terminal in a substrate region of an integrated substrate provided for each semiconductor element to be mounted;
Forming first and second test electrodes that are electrically independent from the external connection terminals for each of the substrate regions of the integrated substrate;
Mounting a semiconductor element having an electrode pad on a region of the integrated substrate that does not overlap the first and second test electrodes;
Connecting the electrode pad and the external connection terminal via a bonding wire;
Covering the semiconductor element and the external connection terminal with a sealing resin;
Including
In the step of connecting the electrode pad and the external connection terminal, the first and second test electrodes are not electrically connected to the semiconductor element,
A method of manufacturing a semiconductor device, wherein the first and second test electrodes are not covered with the sealing resin in the step of covering with the sealing resin. 前記第一、第二のテスト用電極を前記基板領域ごとに形成する前記工程、又は、前記電極パッドと前記外部接続端子とを接続する前記工程において、前記第一のテスト用電極と第二のテスト用電極とを電気的に接続し、
前記電極パッドと前記外部接続端子とを接続する前記工程の後、前記基板領域内で前記外部接続端子と前記電極パッドとの接続不良を発見したとき、不良を発見した前記基板領域内の前記第一のテスト用電極と前記第二のテスト用電極とを電気的に切断する、請求項６に記載の半導体装置の製造方法。 In the step of forming the first and second test electrodes for each substrate region, or the step of connecting the electrode pad and the external connection terminal, the first test electrode and the second test electrode Electrical connection with test electrode
After the step of connecting the electrode pad and the external connection terminal, when a connection failure between the external connection terminal and the electrode pad is found in the substrate region, the first in the substrate region where a failure is found. The method for manufacturing a semiconductor device according to claim 6, wherein one test electrode and the second test electrode are electrically disconnected. 前記基板領域ごとに前記一体基板を切断するダイシング工程と、
前記第一のテスト用電極と前記第二のテスト用電極とが電気的に切断されているか否かを判断し、前記第一のテスト用電極と前記第二のテスト用電極とが電気的に切断されていない前記基板領域内に形成された前記半導体素子を選別する検査工程と、
を含む請求項７に記載の半導体装置の製造方法。 A dicing step of cutting the integrated substrate for each of the substrate regions;
It is determined whether the first test electrode and the second test electrode are electrically disconnected, and the first test electrode and the second test electrode are electrically An inspection step of selecting the semiconductor element formed in the substrate region that has not been cut;
The manufacturing method of the semiconductor device of Claim 7 containing this. 電極パッドを備えた半導体素子が搭載され、外部接続端子が形成された基板と、
前記半導体素子及び前記外部接続端子を覆う封止樹脂と、
前記基板のうち、平面視で前記半導体素子と重ならない領域に形成され、前記封止樹脂で覆われていない第一、第二のテスト用電極と、
を有し、
前記電極パッドと前記外部接続端子とがボンディングワイヤーを介して接続されており、
前記半導体素子及び前記外部接続端子から独立して、前記第一のテスト用電極と前記第二のテスト用電極とが電気的に接続されている半導体装置を用意するステップと、
前記ボンディングワイヤーを介した前記電極パッドと前記外部接続端子との接続が不良であるとき、前記第一のテスト用電極と前記第二のテスト用電極とを電気的に切断するステップと、
前記第一のテスト用電極と前記第二のテスト用電極とが電気的に切断されているか否かを判断するステップと、
を含み、
判断する前記ステップにおいて、前記第一のテスト用電極と前記第二のテスト用電極とが電気的に切断されていないとき、前記半導体装置を良品と判定し、前記第一のテスト用電極と前記第二のテスト用電極とが電気的に切断されているとき、前記半導体装置を不良品と判定する、半導体装置の検査方法。 A substrate on which a semiconductor element including an electrode pad is mounted and an external connection terminal is formed;
A sealing resin covering the semiconductor element and the external connection terminal;
Of the substrate, formed in a region that does not overlap the semiconductor element in plan view, the first and second test electrodes not covered with the sealing resin,
Have
The electrode pad and the external connection terminal are connected via a bonding wire,
Preparing a semiconductor device in which the first test electrode and the second test electrode are electrically connected independently of the semiconductor element and the external connection terminal;
Electrically disconnecting the first test electrode and the second test electrode when the connection between the electrode pad and the external connection terminal via the bonding wire is defective;
Determining whether the first test electrode and the second test electrode are electrically disconnected; and
Including
In the step of determining, when the first test electrode and the second test electrode are not electrically disconnected, the semiconductor device is determined to be a non-defective product, and the first test electrode and the A method for inspecting a semiconductor device, wherein the semiconductor device is determined to be defective when the second test electrode is electrically disconnected.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017024276A (en) * 2015-07-23 2017-02-02 キヤノン株式会社 Liquid discharge head and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017024276A (en) * 2015-07-23 2017-02-02 キヤノン株式会社 Liquid discharge head and method for manufacturing the same

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