JP3382467B2 - Active matrix substrate manufacturing method - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method for manufacturing an active matrix substrate.

[0002]

2. Description of the Related Art A semiconductor device is usually provided with wiring for connecting a semiconductor substrate or a semiconductor layer to the outside.
As such a wiring, an Al (aluminum) wiring is generally used. As an example of Al wiring, a '94 VLSI S
CMP (Chemical Mechanical Polish) reported in ymp.
There is a method of forming an Al wiring or an Al electrode by a damascene method using (ing). This will be described with reference to FIG. First, the thermal oxide film 61 and the interlayer insulating film 62 are formed on the silicon substrate 60 (FIG. 14A). Interlayer insulation film 6
2 is patterned to form an Al-embedded pattern 63 (FIG. 14 (b)). Al using the sputtering method
The film 64 is formed (FIG. 14C). At this time, the Al film 6
The thickness of No. 4 is larger than the step of the Al-embedded pattern 63. Then, the Al film 64 is CMP-polished to form an Al electrode 65 (FIG. 14D).

[0003]

However, in the above-mentioned wiring or electrode formation by the damascene method,
Actually, as shown in FIG. 15E, a shape called dishing in which the central portion of the Al electrode 65 is depressed is produced. This is because the polishing cloth is deformable when materials having different CMP polishing rates in the metal layer typified by Al and the insulating layer typified by p-SiO are mixed in the same polishing surface. This is caused by excessive polishing of a material having a large polishing rate. For Al and p-SiO, polishing rate of Al
Is 4 to 5 times larger than p-SiO, the Al electrode 6
Dishing occurs at 5. This dishing is shown in Figure 1.
As shown in Fig. 6, the size increases as the size of the Al electrode increases, and is about 3000 for an Al electrode of 300 μm.
Å Dishing occurs. In the case of an Al electrode having a size of several hundred μm, such as a pad portion for wire bonding, a part of the Al electrode 65 disappears due to large dishing as shown in FIG. This is also a cause of lowering the yield of the device. Further, in the Al wiring, the wiring resistance increases due to dishing, which causes deterioration of the element characteristics.

An object of the present invention is to provide a method of manufacturing an active matrix substrate using a metal pixel electrode with a reduced dishing amount.

[0005]

A method of manufacturing an active matrix substrate of the present invention which achieves the above object is as follows.

That is, in the method for manufacturing an active matrix substrate of the present invention, a first step of preparing a semiconductor substrate having a signal line portion, a scanning line portion and a transistor portion, and silicon nitride (50) on the surface of the semiconductor substrate. A second step of forming a first insulating layer made of, a third step of forming a second insulating layer made of silicon oxide (51) on the first insulating layer,
The insulating region (5) left in the second insulating layer in the opening (53)
2) is formed by patterning the second insulating layer by etching the second insulating layer while using the first insulating layer as an etching stopper, thereby forming the opening (53). Forming a contact hole (54) extending to the transistor portion in the opening, filling the contact hole with a metal (55), and forming the contact hole on the semiconductor substrate after the fifth step. , A sixth step of coating aluminum (56), and a second insulation located outside the opening of the fourth step while using the remaining insulation region (52) of the second insulation layer as a polishing stop. A layer and a metal pixel electrode (56), which is polished in the sixth step, so that it is insulated from each other by the polished second insulating layer.
It has the 7th process of forming.

[0007]

[0008]

In the present invention, the conductive material or the pixel electrode is preferably Al. Also, the different regions or different materials may be SiO or SiN.

The method of manufacturing an active matrix substrate of the present invention can be applied to a method of manufacturing an integrated liquid crystal display device in which a display section and a driving section are integrated, including a general IC manufacturing method. Further, the semiconductor device according to the method of the present invention can be applied to an active matrix substrate, and this active matrix substrate is used for a liquid crystal display device or a DMD (Digital Micromirror).
It can be used for a display device such as a device.

[0011]

DETAILED DESCRIPTION OF THE INVENTION A description will be given with reference to FIGS.
Hereinafter, the procedure for forming the semiconductor device of the present invention will be described step by step. In the description, in these drawings, only the pads that are the wire bonding portions of the semiconductor device are shown, and the transistor portion, the wiring portion, and the like are
It should be formed using a normal semiconductor process.

First, the semiconductor substrate 1 is thermally oxidized to a thickness of 80.
A field oxide film 2 having a thickness of about 00Å is formed. For example,
Simultaneously with the formation of the gate electrode of the MOS transistor, the polysilicon 3 is formed to a thickness of about 4400Å. The polysilicon 3 is provided to form the pad portion at the highest height in the wafer surface before the subsequent CMP process. Next, BPSG (Bo
vo-Phospho-Silicate Glass
s) 4 is deposited to a thickness of about 8000Å (Fig. 1
(A)). Next, an Al (aluminum) film 5 which is a wiring material is formed (FIG. 1B). Next, plasma C
VD (Chemical Vapor Deposition)
ion) to stack p-SiN6 and p-SiO7 (FIG. 1C). In the present application, p-SiN and p-SiO represent a SiN region SiO region formed by plasma CVD. Next, p-SiO7 is patterned to form an island-shaped polishing stop portion 8 inside the pad (FIG. 1 (d)).
In the dry etching and wet etching in patterning, p-SiN6 functions as an etching stopper layer, the dry etching has a selectivity of about 3 with p-SiO, and wet using BHF (buffered hydrofluoric acid). The etching selection ratio is about 6. The through-hole 9 is formed (FIG. 2 (e)). A tungsten film is selectively deposited in the through hole 9 by using the CVD method to form a tungsten plug 10 (FIG. 2).
(F)). Although an example in which tungsten is used to fill the through hole 9 is shown here, other metals such as Al and T are used.
i or the like can also be used. The Al film 11 is formed by using the sputtering method or the like (FIG. 2G). Here, the Al film 11 is made thicker than the p-SiO7. Next, the wafer surface is polished by CMP (chemical mechanical polishing) to flatten the device surface, and
The pad portion including the l-electrode 12 is insulated from other electrodes (FIG. 2 (h)). For actual CMP polishing, for example,
A CMP-224 CMP apparatus manufactured by Speed Fam, a Politex DG as a polishing cloth, and a PLANERLITE 5102 manufactured by Fujimi Co., Ltd. as a slurry, for example, a slurry flow rate of 100 ml / min, PLATEN SPEE
D / CARRIER SPEED 40rpm / 39r
The polishing can be performed under the polishing conditions of pm and a wafer pressing pressure of 200 g / cm ² . In addition, EP manufactured by Ebara Corporation
O-114 CMP equipment, SUPERME RN for polishing cloth
-H (D51), slurry to Fujimi PLANE
Using RLITE5102, slurry-flow rate 200 ml /
min, PLATEN SPEED / CARRIER
Similar results can be obtained by polishing under the conditions of SPEED of 50 rpm / 49 rpm and wafer pressing pressure of 200 g / cm ² . The cleaning after the CMP polishing is performed by scrub cleaning using a PVA brush after performing megasonic spin cleaning using cathodic water having an electrolyzed pure water that is electrolyzed and having a pH of more than 7. The megasonic spin cleaning using the cleaning liquid in which 0.01 ppm of NH ₄ OH is added to the cathode water of the electrolytic ion water is more effective in removing particles.

FIG. 3 (i) is a perspective view of FIG. 1 (a).
1J is a perspective view of FIG. 1B, and FIG. 3K is FIG. 1D.
FIG. 4 (l) is a perspective view of FIG. 2 (h). FIG. 4 (m) is a plan view of FIG. 2 (h) and FIG. 4 (l) seen from the surface. As shown in FIG. 3 (k), the polishing stop portion 8
Is formed in a columnar shape, and is formed so as not to electrically separate the Al electrode 12 as shown in FIGS. 4 (l) and 4 (m).

The feature of the present embodiment is that the polishing stop portion 8 is provided inside the pattern of the Al electrode 12 which is the pad portion, whereby the Al electrode 12 generated during CMP polishing is formed.
It is possible to reduce the dishing and to prevent the Al electrode 12 from disappearing due to overpolishing. That is, metal CMP
The process yield can be improved. In addition,
Although the polishing stopper 8 is square in FIG. 4 (m), it may be regular polygon such as regular pentagon or regular hexagon. The shortest distance from any point on the Al electrode 12 to the polishing stop portion 8 or the side wall of the Al electrode 12 is 5
It is preferably 0 μm or less.

[0015]

【Example】

(Embodiment 1) This will be described with reference to FIGS. These figures are plan views of the pad portion similarly to FIG. 4 (m).
In FIG. 5A, the polishing stop portion 8 is formed in a stripe shape. In FIG. 5B, the cross-sectional shape of the polishing stop portion 8 is polygonal. In FIG. 6 (c),
The cross-sectional shape of the polishing stop portion 8 is triangular. Figure 6
In (d), the cross-sectional shape of the polishing stopper 8 is circular or elliptical. In FIG. 6E, the cross-sectional shape of the polishing stop portion 8 is arbitrary and plural. In any of FIGS. 5A to 6E, the polishing stop portion 8 or A from an arbitrary point on the Al electrode 12 is removed.
The shortest distance to the side wall of the l-electrode 12 is preferably 50 μm or less. The feature of this example is that the cross-sectional shape of the polishing stop portion 8 is formed in an arbitrary shape, which reduces dishing of the Al electrode 12 during CMP polishing, prevents the pad portion Al film from disappearing, and improves the CMP. The process yield can be improved.

(Second Embodiment) A description will be given with reference to FIG. Figure 7
FIG. 4B is a plan view of the pad portion as in FIG. In FIG. 7, 5 is a lower layer Al wiring, and 12 is an upper layer Al electrode. Reference numeral 8 is a polishing stop portion, and 9 is a through hole for electrically connecting the Al wiring 5 and the Al electrode 12. The feature of this example is that the polishing stop portion is formed in a lattice shape and the Al of the same pad portion is formed.
The electrode 12 is divided into a plurality of segments, and each Al electrode 1
The second segment is electrically connected by the through hole 9 and the Al wiring. As a result, the dishing of the Al electrode 12 can be made smaller and the disappearance of the Al electrode 12 can be prevented, so that the yield of the CMP process is improved. The segments of each Al electrode 12 can be formed in a plurality of arbitrary shapes, and the shortest distance from any point on the segment of the Al electrode 12 to the polishing stop portion 8 is 100 μm.
It is desirable that the thickness is m or less.

(Third Embodiment) A third embodiment will be described with reference to FIGS. In FIG. 8A, 1 is a semiconductor substrate, 2 is a thermal oxide film formed by thermally oxidizing the semiconductor substrate 1, and 4 is BPSG.
(Boro-Phospho-Silicate Gl
and 20 is p-SiO. The p-SiO20 is patterned to form the polishing stop portion 8 (FIG. 8).
(B)). In dry etching or wet etching during patterning, a pattern having a desired depth is formed by controlling the time. The Al film 5 is formed by using the sputtering method or the like (FIG. 8C). The thickness of the Al film 5 is formed larger than the depth of the pattern formed in FIG. 8 (b). The Al wiring 5 is formed by CMP polishing (FIG. 8D). The CMP polishing conditions and cleaning conditions can be the same as those in the above-described example. A film of p-SiN21 is formed (FIG. 8E). After that, the multilayer wiring can be formed by a similar method such as the second Al film and the third Al film. 9 (f) is a perspective view of FIG. 8 (b), and FIG. 9 (g) is a perspective view of FIG. 8 (d). 8 (a) to 8 (d)
Is a method of forming the Al wiring 5 by the damascene method, and the feature of this example is that an island-shaped polishing stop portion 8 is provided inside the Al wiring 5. This polishing stop portion 8 is shown in FIG.
(F), as shown in FIG. 9 (g), the same Al wiring 5 is formed in an island shape so as not to be electrically separated, and its cross-sectional shape is formed in an arbitrary plurality of shapes as described above. You can The polishing stop portion 8 is preferably arranged such that the shortest distance from an arbitrary point on the Al wiring 5 to the polishing stop portion 8 or the side wall of the Al electrode 5 is 10 μm or less. Through the above steps, the dishing of the Al wiring 5 by CMP polishing can be suppressed to 200 Å or less. As a result, an increase in wiring resistance due to dishing and a variation in wiring resistance can be suppressed. In addition, device stabilization and high yield can be realized.

(Embodiment 4) With reference to FIGS. 10 to 13, description will be made below step by step. As shown in FIG. 10A, the N-type silicon substrate 30 having a thickness of 2.0 to 3.0 Ω · cm is thermally oxidized to form a thermal oxide film having a thickness of 7,000 Å, and then B
A pattern of P-type wells is formed by wet etching of HF. N-type Si substrate 3 before implantation of P-type well
After thermal oxidation of 0 to 500 Å to form a P-type well buffer-oxide film, boron is ion-implanted at a dose amount of 9 × 10 ¹² cm ⁻² and an acceleration voltage of 60 KeV. After removing the thermal oxide films 31 and 32 by etching using BHF, 115
A P-type well 33 is formed by annealing at 0 ° C. for 840 minutes (FIG. 10B). The Si substrate 30 is thermally oxidized,
After forming the thermal oxide film 34 of 350 Å, the SiN film 35 is formed by the low pressure CVD method. Si by dry etching
After patterning the N film 35, a field oxide film of 8000 Å is formed by thermal oxidation of the Si substrate 30 (FIG. 10).
(C)). After removing the SiN film 35 by wet etching using hot phosphoric acid, a buffer thermal oxide film having a thickness of 350 Å is formed. Next, 700 Å thick poly-Si
38 is formed. By patterning the resist 39,
A poly-which will later form a thin film transistor (TFT)
BF ₂ dose amount 1 × 10 ¹² cm only in the Si 38 part
^-2 , Ion implantation is performed at an acceleration voltage of 35 KeV. After removing the resist, annealing is performed at 1100 ° C. for 60 minutes (FIG. 10).
(D)). After patterning the poly-Si 38, the buffer oxide film 37 is removed by etching using BHF to form a gate oxide film of 850 Å.

After forming the poly-Si gate electrode 40, NLD 41, NSD 42, PLD are formed by ion implantation.
43, PSD44 is formed. In the formation of each diffusion layer, the dose / accelerating voltage of the NLD 41 is 1 × 10.
¹³ cm ^-2 / 95 KeV, NSD42 has P of 5 × 10 ¹⁵ c
m ⁻² / 95 KeV, PLD43 makes B 1.5 × 10 ¹² c
m ⁻² / 40 KeV, PSD44 is 3 × 10 ¹⁵ cm ^{−2 for} B
/ 100 KeV, 950 ° C., 6 after all ion implantation
The diffusion layer is activated by 0 min annealing (Fig. 1).
0 (e)). After 7000 Å deposition of BPSG45, BPS
Form a contact hole on G45 by patterning
The film 46 is formed and the Al wiring 46 is patterned (FIG. 11F). The structure of the Al wiring 46 is Ti100.
0Å / TiN2000Å / AlSi4000Å / TiN
The sheet resistance is 1000Å, and the sheet resistance of the Al wiring 46 is 0.1Ω / □ or less. The interlayer insulating film 47 is set to 10
000Å, P-SiN48 2700Å film (Fig. 1
1 (g)). The interlayer insulating film 47 is made of P-SiO4000Å
/ SOG2000Å / P-SiO4000Å, and the SOG contains T-10 manufactured by Tokyo Ohka Kogyo Co., Ltd.
Was used to reduce the step. After forming Ti49 3000 Å film and after patterning P-SiN50 3000 Å, P-SiN50
SiO51 is formed in 1000 liters (FIG. 11 (h)). p
-SiO51 is patterned to form a stop portion 52 for CMP polishing and a portion 53 where Al remains by the damascene method. Then, the through-hole 54 is formed by patterning (FIG. 12 (i)). A tungsten plug 55 was formed by selectively filling the through-hole 54 with a tungsten film by a CVD method. The Al electrode 5 is formed by polishing the Al electrode 56 by 10000 Å or more by the sputtering method.
6 electrodes are formed (FIG. 12 (j)). The CMP polishing conditions and the cleaning conditions after CMP polishing are the same as those in the above-mentioned embodiment. Further, the tungsten plug 55 can be replaced with another metal such as aluminum.

FIG. 13 (k) is a perspective view of the Al electrode 56 portion of FIG. 12 (j). This portion corresponds to the image display section of the reflective liquid crystal display. The feature of this example is that the polishing stop portion 52 for CMP is provided inside the Al electrode 56 which is the reflective electrode of the reflective liquid crystal display.
As a result, the dishing amount of the Al electrode 56 can be reduced. Therefore, the light incident on the Al electrode 56, which is a reflective electrode, is reflected in the same direction, and the brightness and contrast of the reflective liquid crystal display can be improved. FIG.
The pixel electrode substrate shown in (k) is a so-called active matrix substrate, and a signal line is provided in the source of the transistor.
A scanning line is connected to the gate, and a reflective electrode which is a pixel electrode is connected to the drain of the transistor. A polishing stop portion 52 is provided inside the reflective electrode. That is, the active matrix substrate shown in FIG. 13 (k) is, in short, a pixel electrode provided corresponding to the intersection of a plurality of signal lines and a plurality of scanning lines, a means for applying a voltage to the pixel electrode, And an area formed of a material different from the metal forming the pixel electrode is present in the area of the pixel electrode. The cross-sectional shape of the polishing stop portion 52 can be any shape as shown in the above-described embodiment, and a plurality of polishing stop portions 52 can be formed inside the Al electrode 56. The shortest polishing stop portion 52 or Al electrode 5 from a point on the arbitrary Al electrode 56.
By setting the distance to the side wall of 6 to 10 μm or less,
The amount of dishing can be less than 100Å.
In this example, the switching transistor of the pixel display section is composed of the TFT, but a transistor formed by forming a diffusion layer on the Si substrate 30 may be used. In the description of this example, a display device using a liquid crystal material is given as an example, but the application of the present invention is not limited to this, and a device for changing the angle of the mirror electrode (reflection electrode) by voltage is used. It can also be applied to electrode and pad structures.

[0021]

As described above in detail, the semiconductor device and the method for manufacturing an active matrix substrate of the present invention can suppress dishing of electrodes or wirings. As a result, with respect to the wiring, variations in wiring resistance can be suppressed to an extremely low level, so that the characteristics of the semiconductor device become extremely excellent. Also, regarding the electrodes,
Since it is extremely close to a plane, the method for manufacturing an active matrix substrate of the present invention is to improve the brightness of a display image,
This will improve the contrast.

In the semiconductor device and active matrix substrate of the present invention, the wiring has a very small wiring resistance and the electrodes have a shape close to a plane, and the brightness of the displayed image is improved.

[Brief description of drawings]

FIG. 1 is a schematic view showing an example of a manufacturing process of a semiconductor device of the present invention.

FIG. 2 is a schematic view showing an example of a manufacturing process of a semiconductor device of the present invention.

FIG. 3 is a schematic view showing an example of a manufacturing process of a semiconductor device of the present invention.

FIG. 4 is a schematic view showing an example of a manufacturing process of a semiconductor device of the present invention.

FIG. 5 is a schematic view showing an example of a manufacturing process of a semiconductor device of the present invention.

FIG. 6 is a schematic view showing an example of a manufacturing process of a semiconductor device of the present invention.

FIG. 7 is a schematic view showing an example of a manufacturing process of a semiconductor device of the present invention.

FIG. 8 is a schematic view showing an example of a manufacturing process of a semiconductor device of the present invention.

FIG. 9 is a schematic view showing an example of a manufacturing process of a semiconductor device of the present invention.

FIG. 10 is a schematic view showing an example of the manufacturing process of the active matrix substrate of the present invention.

FIG. 11 is a schematic view showing an example of the manufacturing process of the active matrix substrate of the present invention.

FIG. 12 is a schematic view showing an example of the manufacturing process of the active matrix substrate of the present invention.

FIG. 13 is a schematic view showing an example of the manufacturing process of the active matrix substrate of the present invention.

FIG. 14 is a schematic view showing an example of a manufacturing process of a conventional semiconductor device.

FIG. 15 is a schematic view showing an example of a conventional manufacturing process of a semiconductor device.

FIG. 16 is a graph showing a dishing amount in a conventional semiconductor device.

[Explanation of symbols]

1 Semiconductor substrate 2 field oxide film 3 Polysilicon 4BPSG 5Al film 6p-SiN 7p-SiO 8 Polishing stop part 9 through holes 10 Tungsten plug 11 Al film 12 Al electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/304 622 H01L 21/3205-21/3213 H01L 21/768 G02F 1/1368

Claims (3)

(57) [Claims] 1. A first step of preparing a semiconductor substrate having a signal line portion, a scanning line portion and a transistor portion, and a second step of forming a first insulating layer made of silicon nitride (50) on a surface of the semiconductor substrate. A third step of forming a second insulating layer made of silicon oxide (51) on the first insulating layer, an insulating region (5) in which the second insulating layer is left in the opening (53)
2) is formed by patterning the second insulating layer by etching the second insulating layer while using the first insulating layer as an etching stopper, thereby forming the opening (53). A fourth step of forming a contact hole (54) extending to the transistor portion in the opening, and forming a metal (5) in the contact hole.
5) embedding with 5), aluminum (5
6) covering the second insulating layer and the second insulating layer located outside the opening of the fourth step while using the remaining insulating region (52) of the second insulating layer as a polishing stop. A method of manufacturing an active matrix substrate, comprising a seventh step of polishing aluminum in the sixth step, thereby forming metal pixel electrodes (56) insulated and separated from each other by the polished second insulating layer. . 2. The method for manufacturing an active matrix substrate according to claim 1, wherein the polishing is a step performed by CMP. 3. The shortest distance between the sidewall of the metal pixel electrode (56) and the remaining insulating region (52) of the second insulating layer is set to 50 μm or less.
A method for manufacturing an active matrix substrate according to.