JP2000021885A - Method for forming substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent dishing without affecting layout at the time of forming wiring or an electrode by damascene and dual damascene method using CMP (chemical-mechanical polishing). SOLUTION: This method comprises a process for forming a groove 103 in an interlayer insulating film 102 on a semiconductor region 101, process for forming a conductive material film on the entire face of the interlayer insulating film 102 including the groove part 103, and process for removing the conductive material film on the interlayer insulating film 102 through chemical-mechanical polishing by leaving the conductive materials in the groove 103. In the process for forming the conductive material film on the entire face of the interlayer insulating film 102 including the groove part 103, the mean grain diameter of a conductive material 104 formed in the groove part 103 is made larger than the mean grain particle of a conductive material 105 formed on a part other than the groove part 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of embedding a groove or a groove and a via hole formed in an insulating film with a conductive material film and using the same as a wiring or an electrode by using chemical mechanical polishing (CMP). The present invention relates to a substrate forming method for forming a conductive material film to be formed.

[0002]

2. Description of the Related Art In recent years, in semiconductor devices, in order to miniaturize wiring, increase the number of layers, and reduce the cost, damascene using chemical mechanical polishing (CMP) without using dry etching of a metal film.
A wiring forming method by a (Damacene) method has been proposed (US Pat. No. 4,944,836). In this method, as shown in FIG. 6, an Al film 304 thicker than the groove pattern is formed on the insulating film 302 on which the groove pattern 303 is formed by vapor deposition or sputtering (FIG. 6A). This is a technique in which the formed Al film is removed by CMP to obtain a wiring layer (buried aluminum wiring) 306 having a structure in which the groove is buried with Al (FIG. 6B). In FIG. 3,
Reference numeral 301 denotes a silicon substrate.

In order to reduce the cost, as shown in FIG. 7, a via hole 406 for connecting a groove 403 as a wiring and a lower wiring 404 is formed (FIG. 7A). Embedding with the film 407 (FIG. 7B), and simultaneously removing the metal film other than the grooves and via holes by chemical mechanical polishing (FIG. 7C), reducing the number of steps and forming a multilayer wiring Dual damascene
acene) is attracting attention. In FIG. 7, reference numerals 401, 402, and 405 denote boards,
An interlayer insulating film and a photoresist.

[0004] These methods have been regarded as promising for copper, which is difficult to dry-etch, in response to the demand for lowering the resistance of wirings or electrodes.

[0005] CMP performs polishing utilizing a chemical etching effect of a chemical component contained in an abrasive and a mechanical polishing operation. As shown in FIG. 8, the CMP process attaches a substrate 504 to be polished to a rotatable polishing head 502 via a carrier pad 503, and then attaches the substrate 50 to a rotating platen (polishing platen) 501.
Polishing is performed by pressing the surface of No. 4. A pad (polishing cloth) 506 is attached to the surface of the platen 501, and the slurry attached to the pad 506
(Abrasive) Polishing proceeds with 505.

[0006]

However, in the method of forming wirings or electrodes by the above-described damascene or dual damascene method, as shown in FIG.
A phenomenon called dishing in which the center of the (or electrode) 603 is depressed occurs. In FIG. 9, reference numerals 601 and 602 denote a substrate and an interlayer insulating film, respectively.

As shown in FIG. 10, this dishing does not cause any problem in the portion where the line width (wiring width) of the Al wiring is small, but it becomes larger as the line width becomes larger, and the width becomes 300 μm.
In this case, dishing (dents) of 300 nm or more occurs. Therefore, in the case of an Al electrode having a thickness of several hundreds of micrometers, such as a pad portion for performing wire bonding, Al in the central portion is removed by dishing, and a defect may occur in wire bonding. In addition, even in the case of a power supply line having a large width even in the case of an Al wiring, dishing occurs, the wiring depth at the center is reduced, the wiring resistance is increased, and there is a problem that the element characteristics are deteriorated. In addition, since the dishing causes a depression and an absolute step increase, a depth of focus in lithography of a wiring formed in the upper layer is pressed, which causes a problem of disconnection of the wiring.

In this dishing, since the polishing pad 506 has a finite hardness, the pressure at which the polishing pad 506 comes into contact with the metal at the bottom of the groove increases as the groove width increases. The bottom of the groove extending over several mm has almost the same pressure as the convex portion other than the groove, resulting in the same polishing rate. Therefore, there is no difference in the amount of polishing between the extremely wide groove portion and the portion other than the groove, and the groove portion has no metal. Also, as polishing progresses, the surface becomes flat, and the difference between the upper part of the step (the part where the metal other than the groove is removed) and the lower part of the step (the groove part, the part where the metal remains as wiring) becomes smaller. , Below the step (groove)
Also, the polishing cloth comes into contact and the metal is removed. In a realistic pattern size, when the width and the level difference of the groove portion become larger than the deflection of the polishing pad due to the combination of the above two actions, the metal of the groove portion is removed, which causes dishing.
Furthermore, near the end point of polishing (when the metal is almost completely removed except in the groove used as the wiring), metal represented by Al is exposed in the groove, and in the portion other than the groove, If the insulating films typified by p-SiO ₂ are exposed and the polishing rates of these CMPs are different, materials having a high polishing rate will be polished excessively. In general, in the case of Al and p-SiO _2, p-Si
Since the polishing rate of Al is 5 times or more as compared with O ₂ ,
The further away from the end point (when metal is almost completely removed except in the groove used as the wiring), the more Al in the groove is polished and dishing increases.

As a measure against this dishing, a polishing cloth 5
A method of increasing the hardness of No. 06 has been reported. When the hardness is increased, the deformation of the polishing pad 506 is suppressed and dishing is reduced, but the uniformity of the polishing rate on the inner surface of the substrate is deteriorated. The metal removed by polishing is also A
With a soft metal such as 1, by making the polishing cloth hard, scratches due to the polishing cloth such as scratches occur on the metal surface, resulting in poor characteristics.

Japanese Patent Application Laid-Open No. Hei 9-148329 discloses, as shown in FIG. 11, a region made of a material different from a conductive material (Al) 703 used as a wiring or an electrode inside a groove.
It has been proposed to prevent dishing by disposing a (polishing stop portion 704). In FIG. 11, reference numerals 701 and 702 denote a substrate and p-Si, respectively.
O ₂ .

Regarding the arrangement of the polishing stop portion 704, the shortest distance from an arbitrary point on the conductive material (Al) 703 to the polishing stop portion 704 or the side wall of the conductive material (Al) 703 is a certain distance (for example, 50 μm) or less. However, in order to prevent dishing, such a polishing stop 704 is required.
In addition to the distance at which the polishing is stopped, the area ratio of the area remaining as a wiring or an electrode to the area of the polishing stop 704 arranged to prevent dishing, and the polishing stop 7
04 area is important. If the area ratio of the polishing stop portion 704 provided for preventing dishing to the area of the region 703 remaining as a wiring or an electrode is sufficiently small, or if the area of the polishing stop portion 704 is not sufficiently large, the fine groove wiring Like Tnining, which is likely to occur in densely arranged portions, a material having a low polishing rate (for example, p-SiO ₂ ) does not sufficiently function as a polishing stop portion, and is polished similarly to the conductive material (Al). As a result, the wiring in the center of the wiring (electrode) is the same as in dishing.
The (electrode) depth decreases, leading to an increase in wiring (electrode) resistance. On the other hand, in order to secure a region that functions sufficiently as the polishing stop layer 704, a relatively large region 704 must be secured in the conductive material region 703, which affects wiring resistance and wire bonding strength. Also,
Polishing stop layer 70 that does not function as wiring (electrode) inside
4, there is a need for arranging larger wiring widths and electrodes, which is disadvantageous in layout. In addition, when this is applied to a reflection type liquid crystal device or an electrode of a device that changes the angle of a mirror electrode by a voltage, the polishing stop portion 704 does not have a reflection function, and thus acts as a reflection plate. There is a problem that the area (opening ratio) is reduced.

According to the present invention, in the formation of wiring or electrodes by the damascene and dual damascene methods using CMP, dishing is prevented without affecting the layout, and the wiring (electrode) is increased by increasing the wiring (electrode) resistance and wiring width. ) Variation of resistance can be prevented, and
It is an object of the present invention to provide a substrate forming method capable of improving the brightness of a display image and increasing the contrast of an electrode.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device, comprising: forming an interlayer insulating film on a semiconductor region, forming a groove in the interlayer insulating film; Forming a conductive material film on the entire surface of the interlayer insulating film, and removing the conductive material film on the interlayer insulating film by chemical mechanical polishing while leaving the conductive material in the groove portion. In the method, in the step of forming a conductive material film over the entire surface of the interlayer insulating film including the groove, the average particle size of the conductive material formed in the groove is reduced by the average particle size of the conductive material formed in the portion other than the groove. It is characterized in that it is larger than the diameter.

According to another aspect of the present invention, an insulating film is formed on an active matrix substrate, a groove is formed in the insulating film, and a conductive material film is formed on the entire surface of the insulating film including the groove. And a step of removing the conductive material film on the insulating film by chemical mechanical polishing while leaving the conductive material in the groove, and including the groove on the entire surface of the interlayer insulating film. In the step of forming the conductive material film, the average particle diameter of the conductive material formed in the groove is set to be larger than the average particle diameter of the conductive material formed in portions other than the groove.

According to a third aspect of the present invention, in the method of forming a substrate according to the first or second aspect, a film having a different film type or a different composition is disposed in each of the groove and the portion other than the groove. Is characterized in that the average particle size of the conductive material formed thereon is controlled using the underlayer dependence.

According to a fourth aspect of the present invention, in the method of forming a substrate according to the first or second aspect, the average particle size of the conductive material formed in the groove is increased by laser irradiation. And

According to a fifth aspect of the present invention, in the substrate forming method according to the first or second aspect, the average particle diameter of the conductive material other than the groove is reduced by ion implantation. And

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a view showing an example of steps of a substrate forming method according to the present invention. Referring to FIG. 1, first, a trench 103 is formed in an interlayer insulating film 102 on a semiconductor region (substrate) 101.
Is formed (FIG. 1A). Thereafter, a conductive material film (metal) is formed on the entire surface of the interlayer insulating film 102 including the groove 103 (FIG. 1B).

At this time, according to the present invention, the average particle size of the conductive material (for example, Al) 104 formed in the groove 103 is adjusted to the conductive material (for example, Al) formed in a portion other than the groove 103.
Al) 105 to be larger than the average particle size. That is,
In the case of changing the film forming temperature, the type of the lower layer film, and the film forming method, Al films having different average particle diameters are formed. As shown in FIG. Early,
As the grain size increases, the polishing rate decreases, and in a film close to a single crystal, the polishing rate decreases extremely. In the present invention,
By utilizing this, the average particle diameter of the conductive material (Al) 105 in a portion other than the groove to be polished and removed is reduced as compared with the conductive material (Al) 104 formed in the groove portion 103, The conductive material (Al) 104 in the groove 103 is hardly polished.

As shown in FIG. 1B, the conductive material 104,
After the formation of 105, the conductive materials 104 and 105 are removed by chemical mechanical polishing (CMP) while leaving the conductive material 104 in the groove 103 (FIGS. 1C and 1D). In addition,
FIG. 1C shows a state in which metal removal by CMP is performed while metal removal by CMP is performed, and FIG. 1D shows a state in which a region 106 functioning as a wiring or an electrode is formed in the trench 103. .

According to the present invention, as compared with the conductive material (Al) 104 formed in the groove 103, the average particle diameter of the conductive material (Al) 105 other than the groove to be polished and removed is smaller than that of the conductive material (Al) 104 formed in the groove 103. By reducing the size, the conductive material (Al) 104 in the groove 103 is hardly polished, and dishing can be prevented. The difference between the average grain size of the crystal formed in the groove 103 and the crystal formed in the portion other than the groove is determined by the polishing rate ratio.
It is desirable that the ratio (polishing rate of portions other than the grooves / polishing rate of the grooves) be 1.5 or more.

In other words, the present invention provides a process of forming an interlayer insulating film on a semiconductor region, forming a groove in the interlayer insulating film, and forming a conductive material film on the entire surface of the interlayer insulating film including the groove. And a step of removing the conductive material film on the interlayer insulating film by chemical mechanical polishing while leaving the conductive material in the groove, wherein the entire surface of the interlayer insulating film including the groove is In the step of forming a conductive material film, the average particle size of the conductive material formed in the groove is made larger than the average particle size of the conductive material formed in the portions other than the groove.

Further, the present invention can be applied to the formation of an active matrix substrate. That is, in this case, a step of forming an insulating film on the active matrix substrate and forming a groove in the insulating film; a step of forming a conductive material film on the entire surface of the insulating film including the groove portion; Removing the conductive material film on the film by chemical mechanical polishing while leaving the conductive material in the groove, and forming the conductive material film on the entire surface of the interlayer insulating film including the groove. By making the average particle size of the conductive material formed in the groove portion larger than the average particle size of the conductive material formed in the portions other than the groove portion, dishing can be prevented in the same manner as described above.

In the above example, the conductive material (metal)
Although it is assumed that 104 and 105 are Al, the conductive material 10
4, 105 may be any as long as films having different average particle sizes are formed by changing the film forming temperature, the type of the lower layer, and the film forming method. A metal containing at least one of copper Cu, silver Ag, chromium Cr, nickel Ni, or a metal containing Si, Cu, Pb, Ti, Pd, Sr, Ni, C
An alloy to which at least one of d, Ta, and W is added may be used.

Further, in the above-described example, the conductive materials 104 and 105 are formed directly on the groove 103 and the portion other than the groove, but the groove 103 and the portion other than the groove have different film types or different compositions. A film may be provided, and the average particle size of the conductive material formed thereon may be controlled using the dependence on the base of the film. For example, a TiN film is disposed in the groove 103,
By arranging a Ti film in a portion other than the groove and forming a conductive material on these films, the average particle size of the conductive material can be controlled. More specifically, Ti
An N film is provided, a Ti film is provided in a portion other than the groove, and Al or an alloy of Al can be used as the conductive material.

Alternatively, the average particle size of the conductive material formed in the groove 103 can be increased by laser irradiation.

Alternatively, the average particle diameter of the conductive material other than the groove can be reduced by ion implantation.

[0028]

Embodiments of the present invention will be described below.

Example 1 In Example 1, a substrate was formed (wiring formation). FIG. 3 is a diagram illustrating an example of a process of forming a substrate (forming a wiring) according to the first embodiment. In the first embodiment, first, the semiconductor substrate 201 is formed by a known technique. More specifically, for example, after a semiconductor is formed, a contact is formed thereon by lithography and etching, and W is embedded therein. 201. After forming the semiconductor substrate 201 in this manner,
On this upper layer, a silicon oxide film 202 as an interlayer insulating film having a thickness of 600 nm was formed by plasma CVD using tetraethoxysilane (TEOS). Next, after applying and exposing a photoresist 209, CHF ₃
A C ₂ wiring by anisotropic etching using the F ₆ has a groove portion 203 (the depth 600 nm) to be formed (FIG. 3
(a)).

Next, degassing treatment is performed at a temperature of 500 ° C. for 1 minute, reverse sputter cleaning of 20 nm in terms of a thermal oxide film is performed, and then long distance sputtering (LTS) with a distance between the substrate and the target. , Ti film 207
0 nm, and then the TiN film 208 is
A film having a thickness of nm was formed (FIG. 3B).

Next, the grooves 2 are formed by chemical mechanical polishing (CMP).
The TiN film 208 other than the portion 03 was removed (FIG. 3).
(c)). In addition, as the CMP, IPEC-PLANA
QCTT1010 manufactured by Rodel as slurry for the primary polishing using an apparatus of Westech372M manufactured by R
And a 30% hydrogen peroxide solution H ₂ O ₂ mixed at a ratio of 1: 1 just before polishing.
Using a laminate of C-1000 and SUBA-400, the secondary polishing was performed with pure water and Rodel Sup.
This was performed using a reme RNH pad. After the CMP polishing, cleaning with a chemical and a brush scrub was performed. T
Regarding the removal of the iN film 208, dishing did not occur because the step due to the groove was as large as 600 nm with respect to the thickness of the TiN film 208 of 40 nm.

Next, a degassing process is performed at a temperature of 550 ° C. for 3 minutes, and a reverse sputter cleaning of 5 nm in terms of a thermal oxide film is performed.
After forming the film at ℃, press the metal (Al
−0.5% Cu) (FIG. 3D). Al-0.
The film thickness of 5% Cu was 800 nm. At this time, the TiN film 208 is formed on the side wall and the bottom of the groove.
In portions other than the grooves, the TiN film 208 is removed and the Ti film 20 is removed.
7, metal 204 having an average particle size of about 10 μm is formed in a groove portion having a width of several hundred μm and a groove other than the groove to be removed has an average particle size of about 3 μm. Metal 205 was formed.

Here, TiN and Ti are used as the film for controlling the particle size, but a metal film such as W and Ta,
Nitride films such as N and TaN, oxide films such as silicon oxide films, films obtained by adding fluorine, boron, phosphorus, etc., silicon oxide films called inorganic or organic SOG such as silanol and siloxane, polyimide and acrylic resin It is also possible to control the metal particle size of the upper layer by combining different kinds of films such as organic films.
Further, by changing the composition of the same film type, such as by changing the composition ratio of Ti and N in TiN, the metal grain size of the upper layer can be controlled.

Next, in the same manner as in the step of FIG.
Using a device of Westech 372M manufactured by PEC-PLANAR Co., as a slurry for the first polishing, a mixture of QCTT1010 manufactured by Rodel and 30% hydrogen peroxide H ₂ O ₂ mixed 1: 1 immediately before polishing was used. A pad made of a laminate of Rodel IC-1000 and SUBA-400 is used as the pad, and the secondary polishing is performed using pure water and Rod.
Using a Supreme RNH pad manufactured by El Corporation,
Except in the groove, metal (Al-Cu) and Ti film 20
7 was removed (FIG. 3 (e)). Here, Down Forc
e: 7.0 psi, Platen Speed: 50r
pm, Carrier Speed: An Al-Cu film on the TiN film 208 corresponding to the groove bottom under the condition of 40 rpm
The polishing rate for (average particle size of about 10 μm) is about 140 nm / min. On the other hand, the polishing rate of the polished Al—Cu film (average grain size: about 3 μm) on the Ti film 207 corresponding to portions other than the grooves is about 3 μm.
00 nm / min, the ratio is 1: 2.1, and the polishing rate of the groove portion is lower. In this case, it was confirmed that the dishing in the Al polishing was 20 nm or less. Therefore, it is possible to suppress an increase in wiring resistance and a variation in wiring resistance due to dishing. Further, the depth of focus of lithography is not suppressed, and a multi-layered wiring that is miniaturized becomes possible.

For a portion having a groove width of 10 μm or less,
The particle size is substantially smaller than 10 μm because of the influence of the width of the groove. However, the polishing cloth does not follow such a decrease in the width, and the width of the groove is reduced. About twice as much as the metal film formation amount, it is buried with metal, becomes completely flat, and there is no drop in the groove portion.

Example 2 In Example 2, a reflection type active matrix liquid crystal display device was manufactured. FIG. 4 is a diagram for explaining a manufacturing process of the reflection type active matrix liquid crystal display device according to the second embodiment. Note that this reflection type active matrix liquid crystal display device is provided corresponding to the intersection of a plurality of signal lines and a plurality of scanning lines, and has means for applying a voltage to a pixel electrode made of metal. The pixel pitch is, for example, 300 μm.

In the second embodiment, first, using a known technique,
A 300-nm-thick tantalum Ta metal is formed on a 1.1-mm-thick glass substrate 802 by sputtering, and patterning is performed by photolithography and etching to form a gate electrode and a gate bus wiring. Next, a gate insulating film 80 made of a silicon nitride film SiN _{x is} formed by plasma CVD (chemical vapor deposition).
3, a 100 nm thick amorphous silicon thin film (a-Si) formed by plasma CVD using silane SiH ₄ and hydrogen H ₂ , and a 50 nm thick n ⁺ -type a- An Si layer was formed continuously.
The n ⁺ -type a-Si layer and the a-Si layer are patterned, aluminum is formed by a sputtering method, and patterning is performed, so that the source electrode 805 and the drain electrode 804 are formed.
A source bus wiring 806 is formed, and a thin film transistor (T
FT) 801 is completed.

Next, plasma CVD using TEOS
To form a SiO ₂ film 808 to a thickness of 1.5 μm,
Flattening was performed by CMP. In addition, as CMP,
An IPEC-PLANAR Westech 372M device was used, Cabot's SS-12 was used as the primary polishing slurry, and a Rodel's I-12 was used as the pad.
Using a laminated product of C-1000 and SUBA-400, as secondary polishing, pure water and Supr manufactured by Rodel are used.
This was performed using an eme RNH pad.

After CMP polishing, cleaning was performed with 1% HF and a brush scrub. Apply resist on the top,
First, exposure was performed using a mask for a pixel electrode, development and patterning were performed, and a groove 809 serving as a pixel electrode was formed by dry etching using CHF ₃ and C ₂ F ₆ . The depth of the groove 809 was 400 nm. Thereafter, the resist was stripped. Next, in order to form a via hole, a resist was applied again, patterning was performed, and a via hole 810 was formed by dry etching.

After that, the resist is peeled off,
After performing degassing for 20 seconds and reverse sputter cleaning of 20 nm in oxide film conversion, the TiN film is continuously
m, then Al-0.5% Cu metal 8
11 was formed to a thickness of 600 nm, and the groove 809 and the via hole 810 were simultaneously filled. At this time, Al
Since the film formation temperature was set as low as 100 ° C., the average particle size of Al was about 1 μm irrespective of the groove 809 and the groove 809.

Next, the wavelength at which the absorption of Al is high is 193 nm.
The center of the groove 809 corresponding to the pixel electrode 811 was intensively irradiated by using the ArF laser (scanning the laser light to irradiate only a specific portion) to increase the Al particle size.
At this time, the provision of TiN on the base promotes an increase in the crystal grain size. This allows
The Al particle size of the groove portion 809 corresponding to the pixel electrode 811 is:
The average particle size was about 8 μm. Here, the ArF laser is used, but another laser for local heating may be used.

Thereafter, IPEC-PLANAR W
estech 372M apparatus, as a slurry for primary polishing, QCTT1010 manufactured by Rodel and 30%
A mixture of a hydrogen peroxide solution H ₂ O ₂ at a ratio of 1: 1 immediately before polishing is used, and an IC-10 manufactured by Rodel is used as a pad.
00 and SUBA-400, and
The secondary polishing is performed using pure water and Supreme manufactured by Rodel.
Using an RNH pad, the Al—Cu and Ti films were removed except in the trench. Here, Down Forc
e: 7.0 psi, Platen Speed: 50r
pm, Carrier Speed: Under the condition of 40 rpm, the polishing rate of the Al-Cu film (average particle diameter of about 1 μm) corresponding to the area other than the groove is polished against the polishing rate of the Al-Cu film (average particle diameter of about 8 μm) corresponding to the groove. The speed is a ratio of 1: 2.5, and the polishing speed of the groove portion is lower. In this case, it was confirmed that the dishing in the Al polishing was 10 nm or less. As described above, the pixel electrode 811 and the via hole 810 can be formed at the same time by the dual damascene method, and a pixel electrode that can be extremely flat and can contribute to the improvement of the brightness of the display image and the increase of the contrast can be manufactured with fewer steps.

In the above-described example, the case where the present invention is applied to the fabrication of a switching element for an active matrix liquid crystal display and an a-Si TFT is used has been described, but polysilicon or single crystal silicon or the like is used. TF
T, MIM (Metal Insulator Met)
The present invention can also be applied to a two-terminal drive element such as al) and a varistor. In the above-described example, glass is used as the substrate. However, an insulating material made of plastic such as Si wafer or quartz substrate, PC (polycarbonate), PES (polyethersulfone), PI (polyimide), or PET (polyethylene terephthalate) is used. A flexible substrate can also be used.

In the above-described example, a display element using a liquid crystal material has been described as an example. However, the application of the present invention is not limited to this. It can also be applied to wiring and pad structures.

Example 3 In Example 3, a miniaturized multilayer wiring was formed. FIG.
FIG. 9 is a diagram for explaining a manufacturing process of a miniaturized multilayer wiring according to the third embodiment. In the third embodiment, as in the first embodiment,
A contact is formed by lithography and etching on a substrate 901 on which a semiconductor is formed, W is buried, and tetraethoxysilane is
An interlayer insulating film (silicon oxide film) 902 was formed to a thickness of 500 nm by plasma CVD using (TEOS).
Further, resist coating and exposure are performed, and CHF ₃ and C ₂ F ₆
Region 903 to be a wiring by anisotropic etching using silicon
(Depth 500 nm).

Subsequently, a degassing process is performed at a temperature of 550 ° C. for 3 minutes, reverse sputter cleaning is performed at a thickness of 20 nm in terms of a thermal oxide film, and then a long distance sputtering (LTS) is performed with a distance between the substrate and the target. , TiN film 40n
After forming a film of Al-0.5% Cu metal 904 at 450 ° C. continuously, a high pressure was applied to fill the fine grooves 903 with metal. Al-0.5% Cu film 9
The film thickness of 04 was 700 nm. At this time, except for the fine grooves, the groove portions 903 and other portions have Al-0.
The average particle size of 5% Cu was about 10 μm.

In the upper layer of the Al-0.5% Cu film 904, all the grooves corresponding to the wiring are formed by a photoresist 905.
Covered. FIG. 5 shows the state at this time. On the left side of FIG. 5, for a groove width about twice the film thickness of Al-0.5% Cu, Al-0.5% Cu is completely buried, and a drop of Al-0.5% Cu is seen. It is not possible to implant ions to the part that functions as wiring even without a resist mask, so there is no problem even if it is not covered with resist,
Therefore, it is not necessary to use an expensive exposure apparatus for forming a fine pattern, and a cheaper and easier rough exposure may be used.

Further, even if impurity ions are implanted, if there is no problem with the electrical characteristics and electromigration (EM) resistance of the metal, only a groove portion having a certain line width or more (for example, 20 μm or more) which causes dishing is used as a mask. May be covered with a resist. Thereafter, phosphorus ions are implanted at an energy of 100 keV and a dose of 5E15 / cm.
Inject ² The impurity ions to be implanted and the dose amount are
A sufficient amount of argon, silicon, oxygen, nitrogen, arsenic or other metal is implanted to make the metal amorphous, and ions are implanted at a position where the lower layer is not affected by the ion species and metal film thickness. Adjusted to be injected. By ion implantation, Al other than the groove removed by CMP could be made amorphous.

Then, polishing was performed under the same conditions as in Examples 1 and 2, and an Al-Cu film at the bottom of the groove (average particle size: about 10 μm)
The ratio of the polishing rate of the Al—Cu film (amorphous) other than the groove to the polishing rate of 1: 3 is 1: 3, and the polishing rate of the groove portion is low.
In this case, it was confirmed that the dishing in the Al polishing was 10 nm or less. Therefore, it is possible to suppress an increase in wiring resistance and a variation in wiring resistance due to dishing. Further, the depth of focus of lithography is not suppressed, and a multi-layered wiring that is miniaturized becomes possible.

If all the wirings are not masked with a resist, a part of the line width not less than twice the metal film formation width to a specific line width not masked with the resist becomes amorphous by ion implantation. Although a problem occurs in the electromigration resistance, the crystallinity can be recovered by an annealing process or the like after polishing.

[0051]

As described above, according to the first aspect of the present invention, a step of forming an interlayer insulating film on a semiconductor region and forming a groove in the interlayer insulating film; A method for forming a substrate, comprising: forming a conductive material film on the entire surface of an interlayer insulating film; and removing the conductive material film on the interlayer insulating film by chemical mechanical polishing while leaving the conductive material in the groove. Wherein, in the step of forming a conductive material film over the entire surface of the interlayer insulating film including the groove, the average particle size of the conductive material formed in the groove is adjusted to an average particle size of the conductive material formed in other than the groove. The polishing rate can be controlled by changing the particle size of the conductive material between the groove and the portion other than the groove, so that dishing of the wiring or the electrode can be prevented. That is, dishing can be prevented without affecting the layout in the formation of wiring or electrodes by damascene and dual damascene methods using CMP, whereby an increase in wiring resistance can be suppressed, and wiring resistance due to line width can be reduced. Variation can be reduced, and device stability and high yield can be achieved. Further, in the pad portion, wire bonding failure is eliminated. Furthermore, in the case of a reflective electrode,
An extremely flat reflector can be obtained, and the brightness of the displayed image can be improved and the contrast can be increased.

According to the second aspect of the present invention, a step of forming an insulating film on the active matrix substrate and forming a groove in the insulating film, and a step of forming a conductive material on the entire surface of the insulating film including the groove. A method of forming a substrate, comprising: forming a film; and removing a conductive material film on the insulating film by chemical mechanical polishing while leaving a conductive material in the groove. In the step of forming a conductive material film over the entire surface of the insulating film, the average particle size of the conductive material formed in the groove portion is to be larger than the average particle size of the conductive material formed in other than the groove portion, By changing the particle size of the conductive material in the groove and the portion other than the groove, the polishing rate can be controlled, and dishing of the wiring or the electrode can be prevented.
As a result, an increase in the wiring resistance can be suppressed, and variations in the wiring resistance due to the line width can be reduced, whereby the device can be stabilized and a high yield can be achieved. Further, in the pad portion, wire bonding failure is eliminated. Furthermore, in the case of a reflective electrode, an extremely flat reflective plate can be obtained, so that the brightness of a display image can be improved and the contrast can be increased.

According to the third aspect of the present invention, different types or different compositions of the films are provided in the groove and the portions other than the groove, and are formed thereon by using the base of the film. By controlling the average particle size of the conductive material, the effects of the first and second aspects can be obtained while ensuring the reliability of the wiring.

According to the fourth aspect of the present invention, the average particle size of the conductive material formed in the groove is increased by laser irradiation, so that the steps of lithography and the like are not increased. The function and effect of claim 2 can be obtained.

According to the fifth aspect of the present invention, the substrate can be treated collectively by reducing the average particle size of the conductive material in the portion other than the groove by ion implantation. The functions and effects of the first and second aspects can be obtained.

[Brief description of the drawings]

FIG. 1 is a view showing a process example of a substrate forming method according to the present invention.

FIG. 2 is a diagram showing a relationship between an average particle size and a polishing rate.

FIG. 3 is a diagram illustrating an example of a process of forming a substrate according to the first embodiment.

FIG. 4 is a diagram for explaining a manufacturing process of the reflective active matrix liquid crystal display device of Example 2.

FIG. 5 is a diagram for explaining a manufacturing process of a miniaturized interlayer wiring according to a third embodiment.

FIG. 6 is a view showing a conventional wiring forming method by a damascene method.

FIG. 7 is a diagram illustrating a dual damascene method.

FIG. 8 is a diagram for explaining chemical mechanical polishing.

FIG. 9 is a diagram for explaining dishing;

FIG. 10 is a diagram illustrating a relationship between a wiring width and dishing.

FIG. 11 is a diagram for explaining a conventional technique intended to prevent dishing.

[Explanation of symbols]

 Reference Signs List 101 semiconductor substrate 102 interlayer insulating film 103 groove 104, 105 conductive material 106 region functioning as wiring or electrode 201 semiconductor substrate 202 interlayer insulating film 203 groove 204, 205 metal (Al-Cu) 206 region functioning as wiring or electrode 207 Ti film 208 TiN film 209 Photoresist 801 TFT (thin film transistor) 802 Glass substrate 803 Insulating film 809 Groove 810 Via hole 811 Pixel electrode 901 Substrate 902 Interlayer insulating film 903 Groove 904 Al-Cu film 905 Photoresist

Continued on the front page F-term (reference) 2H092 GA25 HA06 JA03 JA24 JA33 JB24 JB33 JB58 KA05 KA10 KA12 KA18 KB04 KB22 KB25 MA05 MA08 MA15 MA18 MA27 MA37 NA01 NA07 NA19 NA28 NA29 PA01 5F033 AA02 AA04 AA13 AABA ABAA BAA BA25 BA38 BA41 CA01 EA03 EA11 EA19 EA25 EA28

Claims (5)

[Claims] A step of forming an interlayer insulating film on a semiconductor region and forming a groove in the interlayer insulating film; and a step of forming a conductive material film on the entire surface of the interlayer insulating film including the groove.
Removing the conductive material film on the interlayer insulating film by chemical mechanical polishing while leaving the conductive material in the groove portion, the conductive material film being electrically conductive on the entire surface of the interlayer insulating film including the groove portion. A method for forming a substrate, comprising: in a step of forming a conductive material film, making an average particle diameter of a conductive material formed in a groove part larger than an average particle diameter of a conductive material formed in a part other than the groove part. A step of forming an insulating film on the active matrix substrate and forming a groove in the insulating film; a step of forming a conductive material film on the entire surface of the insulating film including the groove; Removing the conductive material film on the film by chemical mechanical polishing while leaving the conductive material in the groove portion, wherein the conductive material film is formed on the entire surface of the interlayer insulating film including the groove portion. Forming a substrate, wherein the average particle size of the conductive material formed in the groove portion is made larger than the average particle size of the conductive material formed in portions other than the groove portion. 3. The substrate forming method according to claim 1, wherein a different film type or a different composition is disposed in each of the groove and the portion other than the groove, and the film is formed by using a base dependence of the film. A method for forming a substrate, comprising controlling an average particle size of a conductive material formed thereon. 4. The substrate forming method according to claim 1, wherein the average particle size of the conductive material formed in the groove is increased by laser irradiation. 5. The method for forming a substrate according to claim 1, wherein the average particle size of the conductive material other than the groove is reduced by ion implantation.