JP3219838B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3219838B2 JP3219838B2 JP11890492A JP11890492A JP3219838B2 JP 3219838 B2 JP3219838 B2 JP 3219838B2 JP 11890492 A JP11890492 A JP 11890492A JP 11890492 A JP11890492 A JP 11890492A JP 3219838 B2 JP3219838 B2 JP 3219838B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon oxide
- silicon
- pattern
- teos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子の製造方法
に係り、特に層間絶縁膜の平坦化に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for flattening an interlayer insulating film.
【０００２】[0002]
【従来の技術】従来、このような分野における技術とし
ては、例えば、以下に示すようなものがあった。2. Description of the Related Art Conventionally, techniques in such a field include, for example, the following.
【０００３】図３は従来の半導体素子の製造方法におけ
る層間絶縁膜の平坦化の一例を示す工程断面図である。FIG. 3 is a process sectional view showing an example of flattening an interlayer insulating film in a conventional method for manufacturing a semiconductor device.
【０００４】この図において、１０は半導体基板、１１
はその半導体基板１０上に形成される第１層金属配線、
１２はプラズマＣＶＤシリコン酸化膜（以下、Ｐ−Ｓｉ
Ｏ）、１３はＯ3 −ＴＥＯＳ（オゾン−テトラ・エチル
・オルソ・シリケート）を用いた常圧ＣＶＤシリコン酸
化膜（以下、Ｏ3 −ＴＥＯＳ・ＮＳＧ）、１４は第２層
金属配線である。In this figure, reference numeral 10 denotes a semiconductor substrate, 11
Is a first-layer metal wiring formed on the semiconductor substrate 10,
12 is a plasma CVD silicon oxide film (hereinafter referred to as P-Si
O), 13 denotes a normal pressure CVD silicon oxide film using O 3 -TEOS (ozone-tetra-ethyl-ortho-silicate) (hereinafter, O 3 -TEOS · NSG), and 14 denotes a second-layer metal wiring.
【０００５】まず、図３（ａ）に示すように、半導体基
板１０上に５０００Åの第１層金属配線１１を形成す
る。First, as shown in FIG. 3A, a 5000 ° first-layer metal wiring 11 is formed on a semiconductor substrate 10.
【０００６】次に、図３（ｂ）に示すように、Ｐ−Ｓｉ
Ｏ１２を２０００Å形成し、続いてＯ3 −ＴＥＯＳ・Ｎ
ＳＧ１３を段差被覆性の良い、高Ｏ3 濃度条件で８００
０Å程度形成する。[0006] Next, as shown in FIG.
O12 is formed at 2000 °, followed by O 3 -TEOS · N
SG13 with good step coverage and high O 3 concentration of 800
It is formed about 0 °.
【０００７】次に、図３（ｂ）に示すように、第２層金
属配線１４を形成する。Next, as shown in FIG. 3B, a second-layer metal wiring 14 is formed.
【０００８】この従来技術を、Ｏ3 −ＴＥＯＳ・ＮＳＧ
プロセスと呼ぶ。[0008] This prior art is described as O 3 -TEOS NSG.
Call it a process.
【０００９】図４に従来の他の半導体素子の製造方法に
おける層間絶縁膜の平坦化の一例を示す工程断面図であ
る。FIG. 4 is a process sectional view showing an example of flattening an interlayer insulating film in another conventional method for manufacturing a semiconductor device.
【００１０】この図において、２０は半導体基板、２１
は第１層金属配線、２２はＰ−ＳｉＯ、２３はＳＯＧ、
２４はＰ−ＳｉＯ、２５は第２層金属配線である。In FIG. 1, reference numeral 20 denotes a semiconductor substrate;
Is a first layer metal wiring, 22 is P-SiO, 23 is SOG,
Reference numeral 24 denotes P-SiO, and 25 denotes a second-layer metal wiring.
【００１１】まず、図４（ａ）に示すように、半導体基
板２０上に５０００Åの第１層金属配線２１を形成した
後に、Ｐ−ＳｉＯ２２を３０００Å形成する。First, as shown in FIG. 4A, after a first-layer metal interconnection 21 of 5000.degree. Is formed on a semiconductor substrate 20, P-SiO22 is formed at 3000.degree.
【００１２】次に、図４（ｂ）に示すように、ＳＯＧ２
３を２０００Åコートする。Next, as shown in FIG.
3 is coated at 2000 mm.
【００１３】次に、図４（ｃ）に示すように、Ｐ−Ｓｉ
Ｏ２４を３０００Å形成する。Next, as shown in FIG.
O24 is formed at 3000 °.
【００１４】最後に、図４（ｄ）に示すように、第２層
金属配線２５を形成する。Finally, as shown in FIG. 4D, a second-layer metal wiring 25 is formed.
【００１５】この従来技術を、ＳＯＧプロセスと呼ぶ。This conventional technique is called an SOG process.
【００１６】図５は従来の更なる他の半導体素子の製造
方法における層間絶縁膜の平坦化の一例を示す工程断面
図である。FIG. 5 is a process sectional view showing an example of flattening an interlayer insulating film in still another conventional method for manufacturing a semiconductor device.
【００１７】この図において、３０は半導体基板、３１
は第１層金属配線、３２はＰ−ＳｉＯあるいはＯ3 −Ｔ
ＥＯＳ・ＮＳＧ、３３は犠牲膜（ＳＯＧあるいはレジス
ト）、３４は第２層金属配線であるまず、図５（ａ）に
示すように、第１層金属配線（５０００Å）３１、Ｐ−
ＳｉＯあるいはＯ3 −ＴＥＯＳ・ＮＳＧ（１５０００
Å）３２を形成する。In this figure, 30 is a semiconductor substrate, 31
Is a first layer metal wiring, 32 is P-SiO or O 3 -T
EOS / NSG 33 is a sacrificial film (SOG or resist), and 34 is a second-layer metal wiring. First, as shown in FIG. 5A, a first-layer metal wiring (5000 °) 31, P−
SiO or O 3 -TEOS / NSG (15000
Å) Form 32.
【００１８】続いて、図５（ｂ）に示すように、第２犠
牲膜３３を５０００Å形成する。Subsequently, as shown in FIG. 5B, a second sacrificial film 33 is formed at 5000 °.
【００１９】次に、図５（ｃ）に示すように、全面エッ
チバックを１００００Åする。Next, as shown in FIG. 5C, the entire surface is etched back by 10000 °.
【００２０】最後に、図５（ｄ）に示すように、第２層
金属配線３４を形成する。Finally, as shown in FIG. 5D, a second-layer metal wiring 34 is formed.
【００２１】この従来技術をエッチバックプロセスと呼
ぶ。This conventional technique is called an etch back process.
【００２２】[0022]
【発明が解決しようとする課題】しかしながら、以上述
べた従来の技術においては、いずれの方法であっても、
第１層配線のパターンとパターンのスリット部あるいは
パターン部とパターンなし部における平坦度が完全でな
く、第２層配線形式においてもその段差が反映され、配
線の微細化が進んでくると、 （１）段差部で第２層配線のカバレージが悪くなり、断
線に至ってしまう。However, in the prior art described above, any of the methods
When the flatness between the pattern of the first layer wiring and the slit portion of the pattern or the pattern portion and the portion without the pattern is not perfect, and the level difference is reflected also in the second layer wiring type, and as the wiring becomes finer, 1) The coverage of the second layer wiring is deteriorated at the stepped portion, resulting in disconnection.
【００２３】（２）ホトリソ工程において、焦点深度に
差が生じる。 という問題が起こり、配線の微細化の阻害要因となった
り、配線の信頼性が低下したりして、技術的に満足でき
る層間絶縁膜の平坦化ができなかった。(2) In the photolithography process, a difference occurs in the depth of focus. This causes a problem of miniaturization of the wiring and a reduction in the reliability of the wiring, so that it is impossible to flatten the interlayer insulating film which is technically satisfactory.
【００２４】本発明は、以上述べた層間絶縁膜の形成に
おいて、完全に平坦な形状が得られず、微細化の阻害要
因となったり、信頼性が低下するといった問題を除去す
るため、第１層配線形成後に、下地によって成長速度及
びエッチング速度が変化するＯ3 −ＴＥＯＳ・ＮＳＧを
用いて、完全に平坦な層間絶縁膜を形成することができ
る半導体素子の製造方法を提供することを目的とする。According to the present invention, in forming the above-described interlayer insulating film, a completely flat shape cannot be obtained, and the problems of obstructing miniaturization and reducing reliability are eliminated. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of forming a completely flat interlayer insulating film by using O 3 -TEOS.NSG whose growth rate and etching rate change depending on a base after forming a layer wiring. I do.
【００２５】[0025]
【課題を解決するための手段】本発明は、上記目的を達
成するために、半導体素子の製造方法において、ボロン
とリンが添加された第１シリコン酸化膜を準備する工程
と、第１配線パターン、及び前記第１シリコン酸化膜と
組成が異なり、かつ、リンが添加された第２シリコン酸
化膜とから成る積層構造を前記第１シリコン酸化膜上に
形成する工程であって、前記第２シリコン酸化膜が前記
第１配線パターン上に配置される前記積層構造を形成す
る工程と、前記第２シリコン酸化膜上を含む前記第１シ
リコン酸化膜上にオゾン及びＴＥＯＳ（テトラ・エチル
・オルソ・シリケート）を用いてＣＶＤ法により第３シ
リコン酸化膜を堆積し、前記第２シリコン酸化膜上方の
前記第３シリコン酸化膜に前記第１配線パターン及び前
記第２シリコン酸化膜の形状を反映した段差を形成する
工程と、エッチバック法により前記第３シリコン酸化膜
の膜厚を前記段差が除去されるまで減じることにより、
前記第１及び第２シリコン酸化膜を覆う前記第３シリコ
ン酸化膜の上面を実質的に平坦にする工程と、平坦にさ
れた前記第３シリコン酸化膜上に第２配線パターンを形
成する工程とを備えるようにしたものである。SUMMARY OF THE INVENTION The present invention, in order to achieve the above object, in the method for manufacturing a semiconductor device, boron
For preparing a first silicon oxide film to which phosphorus and phosphorus are added
And a first wiring pattern and the first silicon oxide film.
Second silicon acid of different composition and to which phosphorus is added
A laminated structure composed of an oxide film on the first silicon oxide film.
Forming a second silicon oxide film,
Forming the laminated structure arranged on the first wiring pattern;
Forming the first silicon oxide film including on the second silicon oxide film.
Ozone and TEOS (tetra-ethyl) on the silicon oxide film
・ Ortho silicate) by CVD method
Depositing a silicon oxide film, and depositing a silicon oxide film on the second silicon oxide film;
The third silicon oxide film has the first wiring pattern and the
Forming a step reflecting the shape of the second silicon oxide film
And the third silicon oxide film by an etch-back method.
By reducing the film thickness of the step until the step is removed,
The third silicon covering the first and second silicon oxide films
Substantially flattening the upper surface of the oxide film;
Forming a second wiring pattern on the third silicon oxide film thus formed.
And a forming step .
【００２６】[0026]
【作用】本発明によれば、上記のように、半導体素子の
製造方法における層間絶縁膜の平坦化を図るために、Ｏ
3 −ＴＥＯＳ・ＮＳＧが下地の種類によって成長速度が
変化することを利用したものである。つまり、配線パタ
ーンのある場所とない場所で、Ｏ3 −ＴＥＯＳ・ＮＳＧ
の成長速度を変え、Ｏ3 −ＴＥＯＳ・ＮＳＧの成長を制
御して完全平坦化を行なうことができる。According to the present invention, as described above, in order to planarize an interlayer insulating film in a method of manufacturing a semiconductor device, an O layer is required.
3- TEOS · NSG utilizes the fact that the growth rate changes depending on the type of the base. In other words, O 3 -TEOS · NSG is used in the place where the wiring pattern exists and in the place where it does not exist.
The growth rate of O 3 -TEOS · NSG can be controlled to achieve complete planarization.
【００２７】また、前記第２の下地膜に段差が残る場合
には、全面エッチバックによって、前記第１の下地膜上
のエッチング速度を前記基板上のエッチング速度よりも
大きくして、前記第２の下地膜の平坦化を行なうことが
できる。In the case where a step remains in the second underlayer, the etching rate on the first underlayer is made higher than the etching rate on the substrate by etching back the entire surface. The underlayer can be flattened.
【００２８】[0028]
【実施例】以下、本発明の実施例について図を参照しな
がら詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.
【００２９】図１は本発明の実施例を示す半導体素子の
製造工程断面図である。FIG. 1 is a sectional view showing a semiconductor device manufacturing process according to an embodiment of the present invention.
【００３０】この図において、１は下地基板となるボロ
ンとリンを添加したシリコン酸化膜（以下、ＢＰＳＧ：
Ｂｏｒｏ・Ｐｈｏｓｐｈｏ−Ｓｉｌｉｃａｔｅ・Ｇｌａ
ｓｓと呼ぶ）、２は第１層金属配線、３はリンを添加し
たＣＶＤ酸化膜（以下、ＰＳＧ：Ｐｈｏｓｐｈｏ−Ｓｉ
ｌｉｃａｔｅ・Ｇｌａｓｓと呼ぶ）、４はＯ3 とＴＥＯ
Ｓを用いた常圧ＣＶＤシリコン酸化膜（以下、Ｏ3 −Ｔ
ＥＯＳ・ＮＳＧと呼ぶ）、５は第２層金属配線である。In this figure, reference numeral 1 denotes a silicon oxide film (hereinafter referred to as BPSG) to which boron and phosphorus are added as a base substrate.
Boro Phospho-Silicate Gla
ss), 2 is a first layer metal wiring, 3 is a CVD oxide film to which phosphorus is added (hereinafter, PSG: Phospho-Si)
4 is O 3 and TEO
Atmospheric pressure CVD silicon oxide film using S (hereinafter referred to as O 3 -T
5 is a second-layer metal wiring.
【００３１】以下、この図を用いて製造方法について説
明する。Hereinafter, the manufacturing method will be described with reference to FIG.
【００３２】まず、図１（ａ）に示すように、ＢＰＳＧ
１上に第１層金属配線２を５０００Å堆積させ、その
後、プラズマＣＶＤあるいは常圧ＣＶＤにて、ＰＳＧ３
を１０００Å堆積させる。First, as shown in FIG.
A first-layer metal wiring 2 is deposited on the substrate 1 at 5000.degree.
Is deposited at 1000 °.
【００３３】続いて、図１（ｂ）に示すように、通常の
ホトリソ・パターニングにて所望の配線を形成する。Subsequently, as shown in FIG. 1B, a desired wiring is formed by ordinary photolithographic patterning.
【００３４】次に、Ｏ3 −ＴＥＯＳ・ＮＳＧを形成する
が、Ｏ3 −ＴＥＯＳ・ＮＳＧは下地によってその成長速
度が変化することが知られており、ＢＰＳＧ１上とＰＳ
Ｇ３上では略１：（２／３）である。Next, O 3 -TEOS.NSG is formed. It is known that the growth rate of O 3 -TEOS.NSG varies depending on the underlayer.
On G3, it is approximately 1: (2/3).
【００３５】そこで、図１（ｃ）に示すように、Ｏ3 −
ＴＥＯＳ・ＮＳＧ４をＢＰＳＧ１上で１８０００Å成長
させれば、ＰＳＧ３上では１２０００Å成長し、その下
地の段差（ＰＳＧ＋金属配線＝６０００Å）を含めれ
ば、完全に平坦となる。[0035] Therefore, as shown in FIG. 1 (c), O 3 -
When TEOS / NSG4 is grown at 18000 ° on BPSG1, it grows at 12000 ° on PSG3, and becomes completely flat if the underlying step (PSG + metal wiring = 6000 °) is included.
【００３６】続いて、図１（ｄ）に示すように、第２層
金属配線５を形成する。Subsequently, as shown in FIG. 1D, a second-layer metal wiring 5 is formed.
【００３７】すなわち、Ｏ3 −ＴＥＯＳ・ＮＳＧのパタ
ーンなし上の成長速度と、パターン上の成長速度の比
を、１：ａ、パターンの厚さをｂとすれば、完全平坦と
なるパターンなし上の膜厚ｘは、 ｘ＝ｂ／１−ａ で決定される。That is, if the ratio of the growth rate of O 3 -TEOS · NSG without a pattern to the growth rate on the pattern is 1: a and the thickness of the pattern is b, the pattern becomes completely flat. Is determined by x = b / 1−a.
【００３８】ここで、層間絶縁膜をもっと薄くしたい場
合（パターン上のＯ3 −ＴＥＯＳ・ＮＳＧを５０００
Å）は、全面エッチバックを併用して行なえばよい。た
だし、Ｏ3 −ＴＥＯＳ・ＮＳＧは下地によって、そのエ
ッチング速度が変化することが知られており、ＢＰＳＧ
上とＰＳＧ上では略１：１．５である。Here, when it is desired to make the interlayer insulating film thinner (O 3 -TEOS · NSG on the pattern is 5000
Ii) may be performed by using etch back on the entire surface. However, it is known that the etching rate of O 3 -TEOS · NSG changes depending on the underlayer.
It is approximately 1: 1.5 on the top and on the PSG.
【００３９】すなわち、図１（ｂ）に続いて、Ｏ3 −Ｔ
ＥＯＳ・ＮＳＧ４をＢＰＳＧ１上で１３８００Å成長さ
せると、ＰＳＧ３上では９２００Å成長し、図２（ａ）
に示すような段差が残る。この後、全面エッチバックを
ＢＰＳＧ１上で２８００Å行なうと、ＰＳＧ３上では４
２００Åエッチングされて、ＢＰＳＧ１上でＯ3 −ＴＥ
ＯＳ・ＮＳＧ１１０００Å残して完全に平坦となる。That is, following FIG. 1B, O 3 -T
When EOS • NSG4 grows 13800 ° on BPSG1, it grows 9200 ° on PSG3, and FIG.
As shown in FIG. Thereafter, when the whole surface is etched back at 2800 ° on BPSG1, 4G is generated on PSG3.
200 ° etched and O 3 -TE on BPSG1
Completely flat, leaving 11000 ° of OS · NSG.
【００４０】続いて、図２（ｂ）に示すように、第２層
金属配線５を形成する。すなわち、Ｏ3 −ＴＥＯＳ・Ｎ
ＳＧの成長速度をパターンなし上：パターン上の場合、
１：ａとし、エッチング速度をパターンなし上：パター
ン上の場合、１：ｃとし、パターンの厚さをｂ、エッチ
バック後のＯ3 −ＴＥＯＳ・ＮＳＧの膜厚をｄとすれ
ば、完全平坦となるＯ3 −ＴＥＯＳ・ＮＳＧのパターン
なし上での成長膜厚及びエッチング量は、 （ａ−１）ｘ＋ｂ＝（ｃ−１）ｙ ａｘ−ｃｙ＝ｄ の式で与えられる。Subsequently, as shown in FIG. 2B, a second-layer metal wiring 5 is formed. That is, O 3 -TEOS · N
SG growth rate without pattern: On pattern:
1: a, no etching rate on pattern: on pattern: 1: c, pattern thickness b, O 3 -TEOS.NSG film thickness after etch-back d, perfect flat The growth film thickness and the etching amount on the O 3 -TEOS · NSG pattern without pattern are given by the following formula: (a−1) x + b = (c−1) y ax−cy = d
【００４１】上記したように、平坦化すべき膜に段差が
残る場合には、Ｏ3 −ＴＥＯＳ・ＮＳＧは下地によっ
て、そのエッチング速度が変化する点に着目して、完全
平坦化を図ることができる。As described above, when a step remains in the film to be flattened, complete flattening can be achieved by paying attention to the fact that the etching rate of O 3 -TEOS · NSG changes depending on the base. .
【００４２】なお、上記実施例においては、金属配線の
層間絶縁膜について述べたが、他工程においても適用で
きることは言うまでもない。In the above embodiment, the interlayer insulating film for metal wiring has been described, but it goes without saying that the present invention can be applied to other processes.
【００４３】また、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づき種々の変形が可能で
あり、それらを本発明の範囲から排除するものではな
い。Further, the present invention is not limited to the above-described embodiment, and various modifications are possible based on the gist of the present invention, and they are not excluded from the scope of the present invention.
【００４４】[0044]
【発明の効果】以上説明したように、本発明によれば、
Ｏ3 −ＴＥＯＳ・ＮＳＧの下地による成長速度及びエッ
チング速度の変化を利用して、パターン上とパターンな
し上の下地を任意に設定することによって、層間絶縁膜
の完全平坦化を図ることができるので、層間絶縁膜の上
層のカバレージに影響しない。また、ホトリソ工程が容
易になるといった効果が期待でき、半導体素子の微細化
及び信頼性向上を図ることができる。As described above, according to the present invention,
The interlayer insulating film can be completely flattened by arbitrarily setting the base on the pattern and the base without the pattern by utilizing the change in the growth rate and the etching rate due to the base of O 3 -TEOS · NSG. It does not affect the coverage of the upper layer of the interlayer insulating film. Further, an effect that the photolithography process becomes easy can be expected, and miniaturization and improvement of reliability of the semiconductor element can be achieved.
【図１】本発明の実施例を示す半導体素子の製造工程断
面図である。FIG. 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.
【図２】本発明の他の実施例を示す半導体素子の製造工
程断面図である。FIG. 2 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to another embodiment of the present invention.
【図３】従来の半導体素子の製造方法における層間絶縁
膜の平坦化の一例を示す工程断面図である。FIG. 3 is a process cross-sectional view showing an example of planarization of an interlayer insulating film in a conventional method for manufacturing a semiconductor device.
【図４】従来の他の半導体素子の製造方法における層間
絶縁膜の平坦化の一例を示す工程断面図である。FIG. 4 is a process sectional view showing an example of flattening an interlayer insulating film in another conventional method for manufacturing a semiconductor device.
【図５】従来の更なる他の半導体素子の製造方法におけ
る層間絶縁膜の平坦化の一例を示す工程断面図である。FIG. 5 is a process sectional view showing an example of planarization of an interlayer insulating film in still another conventional method for manufacturing a semiconductor device.
１ ＢＰＳＧ ２ 第１層金属配線 ３ ＰＳＧ ４ Ｏ3 −ＴＥＯＳ・ＮＳＧ ５ 第２層金属配線DESCRIPTION OF SYMBOLS 1 BPSG 2 1st layer metal wiring 3 PSG 4 O 3 -TEOS / NSG 5 2nd layer metal wiring
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768 ──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. 7 , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768
Claims (1)
コン酸化膜を準備する工程と、 （ｂ）第１配線パターン、及び前記第１シリコン酸化膜
と組成が異なり、かつ、リンが添加された第２シリコン
酸化膜とから成る積層構造を前記第１シリコン酸化膜上
に形成する工程であって、前記第２シリコン酸化膜が前
記第１配線パターン上に配置される前記積層構造を形成
する工程と、 （ｃ）前記第２シリコン酸化膜上を含む前記第１シリコ
ン酸化膜上にオゾン及びＴＥＯＳ（テトラ・エチル・オ
ルソ・シリケート）を用いてＣＶＤ法により第３シリコ
ン酸化膜を堆積し、前記第２シリコン酸化膜上方の前記
第３シリコン酸化膜に前記第１配線パターン及び前記第
２シリコン酸化膜の形状を反映した段差を形成する工程
と、 （ｄ）エッチバック法により前記第３シリコン酸化膜の
膜厚を前記段差が除去されるまで減じることにより、前
記第１及び第２シリコン酸化膜を覆う前記第３シリコン
酸化膜の上面を実質的に平坦にする工程と、 （ｅ）平坦にされた前記第３シリコン酸化膜上に第２配
線パターンを形成する工程とを備えたことを特徴とする
半導体素子の製造方法。(A) a first silicon doped with boron and phosphorus;
Preparing a silicon oxide film; and (b) a first wiring pattern and the first silicon oxide film.
And the second silicon to which the composition is different and phosphorus is added
Forming a laminated structure comprising an oxide film on the first silicon oxide film;
Wherein the second silicon oxide film is
Forming the laminated structure disposed on the first wiring pattern;
Said first silicon containing a step, (c) a second silicon oxide film on the
Ozone and TEOS (tetra-ethyl-o
3rd silicon by CVD method using
Depositing a silicon oxide film, and forming the silicon oxide film above the second silicon oxide film.
The third wiring pattern and the first wiring pattern are formed on a third silicon oxide film.
Step of forming a step reflecting the shape of the silicon oxide film
When, of the third silicon oxide film by (d) etch-back method
By reducing the film thickness until the step is removed,
The third silicon covering the first and second silicon oxide films.
A step of substantially flat upper surface of the oxide film, (e) a second distribution in the flattened been said third silicon oxide film
Forming a line pattern .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11890492A JP3219838B2 (en) | 1992-05-12 | 1992-05-12 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11890492A JP3219838B2 (en) | 1992-05-12 | 1992-05-12 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05315324A JPH05315324A (en) | 1993-11-26 |
| JP3219838B2 true JP3219838B2 (en) | 2001-10-15 |
Family
ID=14748049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11890492A Expired - Fee Related JP3219838B2 (en) | 1992-05-12 | 1992-05-12 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3219838B2 (en) |
Cited By (6)
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|---|---|---|---|---|
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| US9198883B1 (en) | 2011-07-15 | 2015-12-01 | Nusirt Sciences, Inc. | Compositions and methods for modulating metabolic pathways |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101523191B (en) | 2006-10-06 | 2012-06-06 | 株式会社岛津制作所 | Spectrophotometer |
-
1992
- 1992-05-12 JP JP11890492A patent/JP3219838B2/en not_active Expired - Fee Related
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| US9855235B2 (en) | 2011-07-15 | 2018-01-02 | Nusirt Sciences, Inc. | Compositions and methods for modulating metabolic pathways |
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Also Published As
| Publication number | Publication date |
|---|---|
| JPH05315324A (en) | 1993-11-26 |
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