JP3380252B2 - Decoder device - Google Patents

Description

FIELD OF THE INVENTION The present invention relates to the field of digital satellite communication systems, and more particularly to an error correction device for a receiver in such a system.

Background of the Invention Generally, satellites receive signals representing audio, video, or data information from a transmitter. The satellite then amplifies this signal and broadcasts it to the receiver via a communication channel of specified frequency and bandwidth. Error correction is desirable because communication channels are susceptible to errors due to noise within the channel itself or noise from external sources. Forward error correction (FEC) is one technique for reducing or eliminating errors. This technique sends a certain amount of special information along with the original information. When an error occurs, the receiver uses this extra information to locate and correct the error without extra communication with the transmitter.

Widely used in forward error correction systems 2
The two forms employ convolutional coding and block coding. Convolutional coding operates on a continuum of data that is transmitted serially and continuously to the encoder. The convolutional encoder analyzes the current data and a certain amount of previous data. The encoder adds the error correction data to the current data and thereby creates a new data signal. The system then outputs a continuous stream of new data at high speed, ie, more data, faster, or more data over a longer period of time. The receiver is conditioned to analyze the signal encoded with the convolutional error coding method used by the transmitter.

Block coding, such as Reed-Solomon coding, encodes a data signal with additional error correction data using a specified algorithm. Reed-Solomon encoders
Data is typically divided into equally sized units or blocks of convenient size. When using the Reed-Solomon algorithm, these blocks have data attached to them in some way based on the data itself. These processes produce new blocks of somewhat larger size that may or may not resemble the original data. However, a receiver that understands the coding technique used analyzes the new block of data and derives the original data, even if errors are generated in the data.

Each form of error coding has an associated code rate that is based on the number of bits input to an encoder divided by the number of bits output from that encoder. Therefore, if 750-bit data is input, 250-bit error correction code is added, and 1000-bit (750 + 2
50) output, the code rate is said to be 3/4 (750/1000) code rate and the device is said to operate at 3/4 error correction code rate. This is sometimes referred to as rate 3/4 forward error correction.

Even if the reverse operation is performed, these same rates will indicate the coding rate with the error used at the decoder. For example, when 1000-bit data is input, 250 bits of it are error correction codes and the remaining 750 bits are data. The 250-bit error correction code is stripped from the data signal and used to detect and correct errors in the data signal. The remaining 750 bits of data are output.
This decoder is said to operate at a coding rate with 3/4 error correction.

The amount of error correction information encoded in the data signal depends in part on the operation of the satellite. For example, satellite broadcast systems operate in two power modes, low and high. In high power mode, the signal received and transmitted by the satellite is strong. As a result, the quality of the received signal is improved,
Fewer error correction codings are needed to obtain the data with the desired quality. For example, at high power, the transmitted data consists of approximately 25% error correction data and 75% usable data. Similarly, when the satellite operates at low power, the transmitted and received signals are weak. for that reason,
It requires additional error correction data to obtain the desired quality of data. For example, at low power, about 40% of transmitted data is error correction data and about 60% is usable data.

The preferred error correction coding rate maximizes the usable data transmitted and minimizes the error correction data.
If the error correction data contained in the transmitted signal is insufficient, even if the receiver receives the signal, the signal cannot be reliably received. If the error correction data is included too much, the signal can be received correctly, but the output signal that can be used for actual data is more than that when the error correction data is matched with the transmission power of the satellite. The proportion will decrease.

SUMMARY OF THE INVENTION In accordance with the principles of the present invention, the error correction coding rate (co
It has been found desirable to match the ding rate) to the respective power level of the satellite. Therefore, the error correction coding rate is a function of the respective power level of the satellite, which coding rate can be changed without directly contacting the receiver. The receiver senses that the error correction code rate has changed at the transmitter side and, in response, changes the coding rate with the error correction used at the receiver.

A decoder device in a data communication system for processing an input signal encoded with information containing information for facilitating error correction in a decoder, the input device receiving the encoded input signal ( 5,24,25), a first decoder means (26) which operates at a first error correction code rate in response to an output signal from the input means, and normal decoding by the first decoder means or Means (28) for providing a first control signal representative of abnormal decoding, the first error correction code rate being responsive to the first control signal as a function of the state of the first control signal. Decoder device consisting of control means (6,22,23) for changing.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, FIG. 1 is a block diagram of a satellite transceiver system including a device according to the invention.

2 is a block diagram of a portion of the receiver of FIG. 1 including a demodulator / forward error correction unit according to the present invention.

FIG. 3 is a flow chart useful for understanding the sequence of events that occur during control of the system shown in FIG.

FIG. 4 is a flow chart useful for understanding another series of events that occur when controlling the apparatus of FIG.

DETAILED DESCRIPTION OF THE DRAWINGS The system of FIG. 1 includes a transmitter 1 that processes data from a signal source 14 (eg, a television signal source) and transmits it to a satellite 13. Satellite 13 receives the signal and broadcasts the signal to receiver 12. The transmitter 1 includes an encoder 2, a modulator / forward error corrector (FEC) 3, and an uplink unit 4. Encoder 2 is the signal source
The signal from 14 is compressed and encoded according to a predetermined standard such as MEPG. MPEG is an International Standards Organization's Moving Picture Experts Group of the Interpretation for the coded representation of videos and associated audio stored on digital storage media.
National Standards Organization) is an international standard developed by. The encoded signal from encoder 2 is a modulator / forward error corrector (FEC) 3
, And the modulator / forward error corrector 3 encodes the signal with the error correction data. And Quaternary Phase Shifted Key (QPS
K)) modulates the encoded signal and places it on a carrier. Both convolutional coding and RS block coding are performed by the block of the modulator / forward error corrector 3.

The uplink unit 4 transmits the compressed, encoded signal towards a satellite 13, which broadcasts the signal towards a selected geographical reception area. In this embodiment, the satellite 13 operates in two modes, a compromise between channel capacity and transmit power. In the first mode, the satellite
13 transmits, for example, 16 channels at 120 watts each.
In the second mode, satellite 13 transmits eight channels at 240 watts each.

The signals transmitted from the satellites 13 are received by a so-called set-top type receiver 12, for example an antenna 5 which is coupled to the input of an interface device mounted on the television receiver 11. The receiver 12 includes a demodulator / forward error correction (FEC) decoder 7 for demodulating a signal and decoding error correction data, and the demodulator / FEC decoder 7
It includes a microprocessor 6 that interacts with and a transport 8 that transports the signal to a suitable decoder in a decoder unit 9 depending on the content of the signal, ie audio or video information. The transport 8 receives the packets of corrected data from the demodulator / FEC decoder 7 and more rigorously checks each packet to determine its destination. The decoder in the decoder unit 9 decodes the signal and removes the added transport data if used. The NTSC encoder 10 encodes the decoded signal into a format suitable for use in the signal processing circuitry in a standard NTSC home television receiver 11.

Referring to FIG. 2, the demodulator / FEC decoder 7 receives, demodulates and decodes the data signal received by the antenna 5. The demodulator / FEC decoder unit 7 is of a conventional design, and has a tuner 24 arranged as shown in the figure,
4-phase shift keyed (QPSK) demodulator 25, Viterb
i) Tatami also includes a decoder 26, a deinterleaver 27, and a Reed-Solomon (RS) decoder 28.

The tuner 24 receives an input signal from the antenna 5.
Based on the channel selection by the user, the control unit 6, for example a microprocessor, sends a frequency signal to the tuner 24. This signal tunes the tuner 24 to the appropriate channel and converts the received signal to a lower frequency in response to the tuning frequency sent from the microprocessor 6 to the tuner 24. The output signal from the tuner 24 is
It is supplied to the QPSK demodulator 25.

QPSK demodulator 25 locks to the tuning channel,
The modulated signal is demodulated and a signal representative of the quality of the demodulated signal is generated. The demodulator 25 demodulates the input data signal modulated regardless of the error correction code rate of the received data signal. The phase locked loop circuit in demodulator 25 synchronizes the operation of demodulator 25 to the input signal using well known techniques. The demodulator 25 generates a demodulator lock output control signal indicating whether the demodulator 25 is synchronized with the input signal and supplies this signal to the storage register of the microprocessor 6. The output demodulated data signal from the demodulator 25 is supplied to the Viterbi decoder 26. The demodulator 25 also produces a quality signal of the output signal. This signal represents the received signal quality of the signal transmitted by the satellite and is related to the signal-to-noise ratio of the received signal. Various noise sources adversely affect the received signal quality as well as rain fading. A suitable QPSK demodulator for use as demodulator 25 is a fuse in Germantown, Maryland, USA.
Hughes Network System
As an integrated circuit from Model No. 1016212 and in the United States San Diego, California, Comstream Corporation
Commercially available as model number CD2000.

Decoder 26 uses a Viterbi algorithm to decode and correct bit errors in the demodulated signal from demodulator 25. Decoder 26 includes internal circuitry for synchronizing its operation with the incoming demodulated signal, as is well known, in order to effectively decode the demodulated signal.

The decoder 26 has one of two error correction decoding rates corresponding to the error correction coding rate given by the transmitter.
One works. When the satellite 13 is operating in low power mode, the transmitted signal uses a rate 2/3 error correction code. When satellite 13 is operating in high power mode,
The transmitted signal uses a rate 6/7 error correction code. The code rate control signal generated by the control unit 22 in the microprocessor 6 indicates which error correction code rate the decoder 26 should use. The code rate control signal has one logic level indicating that the code rate used in the decoder 26 should remain unchanged, and another logic level that causes the decoder 26 to switch to another programmed code rate. May be a binary signal. The code rate control signal is provided by the control unit 22 in response to the output signal from the digital comparator 23. Comparator 23
Gives the output logic state as a function of the logic state of the input control signal, such as signal quality and block error, which will be described later. These signals are provided to a storage register which is monitored by the comparator 23. After the decoder 26 decodes the demodulated data signal and performs error correction,
The decoded data signal is supplied to the deinterleaver 27. The deinterleaver 27 returns the order of the data signals to their original sequence and forms Reed-Solomon blocks (RS blocks) according to well known techniques. To this end, the deinterleaver 27 relies on the 8-bit sync word inserted by the encoder at the start of each RS block,
This synchronizes the RS block. The deinterleaved signal is provided to a Reed-Solomon (RS) decoder 28.

The RS decoder 28 decodes the RS block using a decoding rate of 130/146, for example, and corrects errors in bytes within the block. The 8-bit sync byte word added to each Reed-Solomon block is
The start of the block can be easily located. 13
The effective RS decoding rate of 0/147 is due to the use of this added sync word. This 8-bit sync byte word is removed by the deinterleaver 27 prior to Reed-Solomon decoding, so 14 bits per block
Only 6 bytes are RS decoded.

The RS decoder 28 also performs error detection when the number of errors in the block exceeds the RS code correction capacity. For example,
The RS decoder 28 can correct an error of up to 8 bytes in the block. If more than 8 bytes of error are detected, the RS decoder 28 will generate an output block error signal with a binary signal having a high logic level indicating, for example, that there are more than a correctable number of errors. . Uncorrectable
The RS block is discarded and not used. If the RS block is RS-decodeable within a predetermined 8-byte parameter, the decoded signal is supplied to the transport 8. The illustrated combination of a Viterbi algorithm convolutional decoder followed by an RS decoder provides very good error detection / correction results, especially in the error rate and signal / noise environments normally associated with satellite transmission. I knew that.

The transmitter (unit 3 in FIG. 1) can change the error correction code rate at any time without notifying the demodulator / decoder 7 of the receiver of the change. In this example, the system maintains two (Viterbi) and RS error correction code rates, 2/3 × 130/147 at low satellite power and 6/7 × 130/147 at high satellite power. is doing. When the power mode is switched, the error correction code rate is also switched. Since the error correction code rate of the RS decoder 28 in the receiver is a constant value (130/147), only the error correction decoding rate of the Viterbi decoder is different from the programmed rate (2/3 to 6 / 7 to 7 or vice versa 6/7 to 2
It is changed by switching to / 3). Viterbi decoder
The error correction decoder rate used at 26 is modified using the code rate control signal provided by the microprocessor 6. Microprocessor 6 sets the state of the code rate signal in response to the state of the block error signal from RS decoder 28. The microprocessor 6 also determines the state of the code rate signal in response to the signal from the demodulator 25 as will be described later.

Various conditions can make the error correction decoding rate of the receiver uncertain. For example, when the system is operating with one error correction decoding rate, that rate may be switched at the transmitter, or the channel may be changed to a channel with an unknown error correction rate. . According to the present invention, the use of an incorrect error correction decoding rate is detected and the error correction decoding rate is changed. This is accomplished by analyzing the result of decoding by the RS decoder 28 indicated by the block error signal. This is also achieved by analyzing the quality of the data signal determined by the QPSK demodulator 25 with respect to the result of the RS decoding determined by the block error signal from the RS decoder 28. In either case, demodulator 25 is itself synchronized with the input data signal. The power level and error correction code rate of the received satellite signal can pass through the demodulator 25 as it is (tr
ansparent: transparent). Therefore, the demodulator 25 always attempts to demodulate the received data signal and also supplies the demodulated signal to the Viterbi decoder 26.

The decoded signal from the Viterbi decoder 26 is supplied to the RS decoder 28 via the deinterleaver 27. The deinterleaver 27 and the Reed-Solomon decoder 28 operate normally when the decoder 26 uses an appropriate error correction decoding rate to decode the data signal. In such a case, the block error signal exhibits a predetermined state, eg, a logic "low" level indicating normal decoding.
If the decoder 26 uses an incorrect error correction code for a given input signal, the decoder 28 may not provide a normal output. In such a case, the block error signal exhibits a different state, eg, a logical "high" level indicating an abnormal output from the S decoder 28. In either case, the block error signal is analyzed to determine if the error correction code used by Viterbi decoder 26 should be modified.

FIG. 3 is a flow chart showing a sequence of events that occur at the receiver when, for example, the error correction code rate is changed at the transmitter. This modification causes the modulator to switch to a new error correction code rate, which causes fluctuations in the transmitted data signal. Swing can also be caused by rain fading or tuning to a new channel. Such fluctuations cause the QPSK demodulator in the receiver to lose synchronization with the data signal.

Referring to FIG. 3 in conjunction with FIG. 2, when the demodulator 25 loses synchronization (lock) with the data signal, the logic circuitry in the demodulator 25 may be, for example, a high logic level demodulator indicating loss of synchronization. A lock signal is generated (step 31). Demodulator 25 attempts to resynchronize with the input data signal until the data signal is strong enough for proper reception (step 32).
And 33). When demodulator 25 regains synchronism, the demodulator lock signal exhibits a low logic level indicating that synchronism has been secured. The Viterbi decoder 26 is then set to the default error correction code rate by the microprocessor 6 using the code rate signal (step 34). The default code rate is a preprogrammed one of the available code rates.

If the demodulator 25 loses synchronization with the data signal, the synchronization circuit associated with the Viterbi decoder 26 will generally not be able to synchronize to the signal from the output of the demodulator. as a result,
Wrong information is supplied to the core of the Viterbi decoder 26, and the Viterbi decoder 26 outputs an abnormal signal. In such a case, the deinterleaver 27 cannot locate and dominate the 8-bit sync word inserted to align the RS blocks. Therefore, the RS decoder 28 cannot properly decode the output signal from the Viterbi decoder 26, and the level of the block error signal indicates an inappropriate decoding by the RS decoder 28.

Microprocessor 6 checks the block error signal for a preset period after demodulator 25 has regained synchronism (step 35). If the block error signal state (low) indicates normal decoding, it is assumed that the error correction code rate used by the Viterbi decoder 26 corresponds to the transmitted code rate (step 3).
9). Conversely, if the block error signal indicates another condition (high) indicating abnormal decoding, the Viterbi decoder 26
It is assumed that the error correction code rate of is not correct. this is,
This is because if the Viterbi decoder 26 uses an incorrect error correction code rate, the RS decoder 28 will not be able to perform correct RS block decoding. Therefore, the microprocessor 6 supplies a code rate signal having a state indicating that the error correction code rate of the Viterbi decoder 26 should be changed (step 37).

The block error signal is checked by the comparator 23 of the microprocessor 6 for a predetermined period. The Viterbi error correction code rate is switched between the available error correction codes until the block error signal exhibits a condition indicating that the data signal is successfully decoded.

Tuning to a new channel does not necessarily result in demodulator 25 losing synchronization. If synchronization is lost during a channel change, steps 35, 37 and 39
The above process including is repeated.

As another example, to determine if the wrong error correction code rate is being used at the Viterbi decoder 26, the QP
The signal quality signal from SK demodulator 25 may be used. FIG. 4 (see also FIG. 2) shows the sequence of events that occur in this case. Steps 44, 45 and 49 in FIG. 4 correspond to steps 34, 35 and 39 in FIG. 3, respectively. FIG. 4 differs in that steps 46, 47 and 48 are added.

If the QPSK demodulator 25 is initially locked to the data signal, the Viterbi decoder 26 is set to the default code rate as previously described (step 44). Viterbi decoder 26 then attempts to synchronize itself with the demodulated data signal. If synchronized, deinterleaver 27 and RS decoder 28 will receive a decodable signal. The RS decoder 28 then produces a low level block error signal indicating proper decoding. Microprocessor 6 senses this low level block error signal and determines whether the Viterbi decoder is using the proper error correction code rate (step 49).

On the contrary, if the Viterbi decoder 26 cannot synchronize with the data signal, the deinterleaver 27 and the RS decoder 28 receive the non-decodable data signal from the Viterbi decoder 26. Then Deinterleaver 27
And RS decoder 28 will not be able to operate properly on the data signal and RS decoder 28 will generate a high level block error signal representative of this condition. Microprocessor 6 senses the signal quality signal provided by QPSK (via comparator 23) (step 46). The high level of the signal quality signal indicates that the RS decoder 28 was able to decode the data signal and the microprocessor 6 sends a code rate signal which instructs the Viterbi decoder 26 to switch the error correction code rate. Occurs (step
47).

If the signal quality signal is low, it indicates that the RS decoder 28 cannot produce a fully decoded signal, even though the Viterbi decoder 26 is using the proper error correction code rate. , Microprocessor 6
Does not change the error correction code rate of the Viterbi decoder 26. This condition occurs, for example, as a result of rain fading. At this time, the microprocessor 6 waits for a specified period before sampling the block error signal (step 48), giving the decoder 26 time to synchronize to the error correction code rate at that time. If the block error signal remains high (indicating incorrect decoding), the microprocessor 6 again samples the signal quality signal. The microprocessor 6 samples the block error signal several times during a predetermined period until proper decoding is instructed by the block error signal. As shown in FIG. 4, the microprocessor 6 continues to sample both the block error signal and the signal quality signal and instructs the Viterbi decoder 26 to change the error correction code rate, or the block error signal is correct. Wait for a specified period of time before indicating a low level indicating decoding.

The following table summarizes the above states for possible states (levels) of signal quality signals and block error control signals.

The Viterbi decoder 26 can operate in response to more than two error correction code rates based on the requirements of the particular system. Similarly, the control signals described above can indicate a particular state or value with a high or low logic level. Viterbi decoder and read-
Encoder and decoder circuitry other than Solomon decoders may be used in the apparatus making up the present invention.

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-5-175915 (JP, A) JP-A-4-10723 (JP, A) JP-A-63-172536 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04L 1/00 H04L 27/22 H04B 7/26

Claims (18)

(57) [Claims] 1. A decoder device in a data communication system for processing an input signal encoded with information including information facilitating error correction in a decoder, the input receiving the encoded input signal. Means, first decoder means operating at a first error correction code rate in response to an output signal from the input means, and first decoder means representing normal decoding or abnormal decoding by the first decoder means. A decoder comprising: means for supplying a control signal; and control means for changing the first error correction code rate in response to the first control signal as a function of the state of the first control signal. apparatus. 2. The first control signal modifies the first error correction rate when the first control signal represents abnormal decoding by the first decoder means. Decoder device. 3. A decoder device according to claim 1, wherein said data communication system is a satellite broadcasting system transmitting signals at various power levels respectively associated with various error processing code rates. 4. The means for providing the first control signal comprises second decoder means responsive to an output signal from the first decoder means and secondly operating at an error correction code rate. Decoder device according to range 1. 5. The input means includes means for generating a second control signal indicating that the decoder device is synchronized with the input signal, the control means comprising the first and second control signals. The decoder device according to claim 1, wherein the first code rate is changed in response to the above. 6. The decoder device according to claim 5, wherein said input means includes means for demodulating said input signal, and said second control signal represents synchronization with said input signal of said demodulation means. . 7. When the second control signal indicates that the demodulation means is in an asynchronous state, the control means controls the first control signal.
7. The decoder device according to claim 6, wherein the code rate is changed. 8. The first code rate when the control means is responsive to a second control signal representative of the signal quality of the input signal to indicate an unacceptable signal quality value of the second control signal. The decoder device according to claim 1, wherein: 9. The first code rate when the control means is responsive to a third control signal representative of the signal quality of the input signal to indicate an unacceptable signal quality value of the third control signal. The decoder device according to claim 5, wherein 10. The first code rate when the control means is responsive to a third control signal representative of the signal quality of the input signal to indicate an unacceptable signal quality value of the third control signal. The decoder device according to claim 6, wherein 11. The decoder device according to claim 1, wherein said first decoder means is a convolutional decoder. 12. The decoder device according to claim 11, wherein the convolutional decoder is a Viterbi decoder. 13. The decoder device according to claim 4, wherein said second decoder means is a block decoder. 14. The decoder device according to claim 13, wherein the block decoder is a Reed-Solomon decoder. 15. A decoder device in a data communication system for processing an input signal encoded with information including information for facilitating error correction in a decoder, the input receiving the encoded input signal. Means, a means for decoding the output signal from the input means using a variable error correction code rate, and a means for generating a control signal representative of synchronization of the encoded data signal of the decoder device, Decoder apparatus comprising: a control means for changing the code rate as a function of the state of the control signal in response to the control signal. 16. The decoder device according to claim 15, wherein said control means changes said code rate when an asynchronous state exists, and said data communication system is a satellite communication system. 17. A decoder device in a data communication system for processing an input signal encoded with information including information for facilitating error correction in a decoder, the output signal from said input means being changeable. Means for decoding using such an error correction code rate, means for generating a control signal representative of the signal quality of the input signal, and changing the code rate in response to the control signal as a function of the state of the control signal. And a control device for controlling the decoder device. 18. The decoder device according to claim 17, wherein said control means changes said code rate when said control signal indicates an unacceptable signal quality.