JPH11252189A - Digital signal demodulator, its method and served medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To strengthen much more durability of a transmission multiplexing configuration control TMCC signal against a transmission line error. SOLUTION: A read Solomon RS decoding circuit 12 corrects an error in a TMCC signal and outputs a flag corresponding to the correction result to a date selector 32 of a protection circuit 31. When the flag denotes a correction enabled state, the date selector 32 selects and outputs the TMCC signal outputted from the RS decoding circuit 12, and the data selector 32 selects and outputs the TMCC signal stored in a register 33 when the flag indicates a correction disabled state. A TMCC decoder 8 receives the TMCC signal outputted from the data selector 32 of the protection circuit 31 and decodes it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal demodulating apparatus and method, and a providing medium, and more particularly to a BS (Br)
The present invention relates to a digital signal demodulation apparatus and method suitable for application to processing of a received signal using a transmission control signal by a digital broadcast receiver, and a providing medium.

[0002]

2. Description of the Related Art In Japan, digital multi-channel broadcasting using a communication satellite (hereinafter referred to as CS) has been in full swing and various services have been started.
It has already been reported by the Radio Control Council that broadcasting satellites (hereinafter referred to as BSs) will provide digital broadcasting services with BS4 (trademark), which is scheduled to be launched in the future.

[0003] Since the power of BS is larger than that of CS, QPSK (Quadrature Phase Shift K) conventionally performed in CS is used.
Eying) Use of a modulation scheme having higher transmission efficiency than that of the modulation scheme is being studied. The bit stream to be transmitted is MPEG (Moving Picture Experts Group) from the viewpoint of compatibility with other media such as CS, terrestrial broadcasting, and cable.
It has been proposed to use a so-called transport stream (hereinafter referred to as TS) defined in p) 2 as a basis. This TS is composed of a packet of 188 bytes including a synchronization byte of 1 byte. However, in CS digital multi-channel broadcasting, terrestrial digital broadcasting, cable digital broadcasting, etc., this TS includes 16 bytes of error correction. Since a parity is added or a Reed-Solomon code (hereinafter, referred to as an RS code) is used, it is proposed to perform RS coding of (204, 188) on a TS even in BS digital broadcasting. .

[0004] Against such a background, the already published document "Maximum transmission capacity in satellite ISDB and application to satellite broadcasting plan": IEICE Transactions B-II Vol.J79-B
-II No.7, "Study of satellite ISDB transmission method": In the Technical Report of the Institute of Image Information and Television Engineers, Vol.21 BCS-97-12, (20
4,188), a convolution-encoded BPSK (Binary Phase Shift Keying) signal or a QPSK (Queen)
adrarure Phase Shift Keying) or trellis-coded 8PSK (Phase Shift Keying), and transmission information such as modulation scheme and coding rate (hereinafter referred to as TMCC (Transmissi
A method of transmitting multiplexing configuration control (hereinafter referred to as information) as a BPSK signal using a TS synchronization unit has been proposed.

[0005] In particular, when so-called pragmatic TC (Trellis-Coded) 8PSK is used as trellis-encoded 8PSK, an encoding circuit and a decoding circuit similar to the conventional convolutional code can be used. , QPSK, 8PSK, etc., when decoding with a receiving device, the same Viterbi decoder can be used when demodulating any of the signals, which is an advantageous system in terms of hardware configuration.

FIG. 6 is a block diagram showing a configuration of a satellite digital broadcast receiver 1 as an example of a receiving apparatus employing the method introduced in the above-mentioned literature.
The BPSK-modulated broadcast signal from the BS is captured by the antenna 2, and the received broadcast signal is frequency-converted to an intermediate frequency by a frequency conversion circuit (not shown) built in the antenna 2 and supplied to the tuner 3. You. When the tuner 3 receives the broadcast signal from the BS by controlling the antenna 2, the tuner 3 reads a signal of a specified program from a user via an input unit (not shown) such as a remote controller, and further reads the read signal. The BPSK signal, which has been frequency-converted to the second intermediate frequency, is supplied to the second intermediate frequency circuit 4. The second intermediate frequency circuit 4 converts the frequency from the tuner 3 to the second intermediate frequency.
When the BPSK signal is supplied, the spectrum of the signal is shaped and a predetermined signal is amplified. The spectrum is shaped and the amplified BPSK signal is supplied to the multipliers 13 and 14 of the quadrature demodulation circuit 5.

The multipliers 13 and 14 of the quadrature demodulation circuit 5 receive the supply of the spectrum-shaped and amplified BPSK signal from the second intermediate frequency circuit 4 and are reproduced from the input BPSK signal from the carrier wave reproduction circuit 9. In addition, it receives supply (feedback) of two carriers whose phases are orthogonal to each other. The multipliers 13 and 14 perform predetermined multiplication processing on the above-mentioned two input signals supplied from the second intermediate frequency circuit 4 and the carrier recovery circuit 9, and perform low-pass filters 15 and 16 of the quadrature demodulation circuit 5. Respectively. The low-pass filters 15 and 16 allow the BPSK signal having a frequency equal to or lower than a predetermined frequency in the input signal to pass therethrough and supply the BPSK signal to an error correction circuit 6 including a Viterbi decoder, a unique word detection circuit 7, and a carrier recovery circuit 9. I do. The unique word detection circuit 7 detects a frame synchronization signal (unique word),
Output to the control circuit 10.

The control circuit 10 controls the whole operation of the satellite digital broadcast receiver 1 according to a predetermined computer program stored therein. The control circuit 10 controls the error correction circuit 6 on the basis of the frame synchronization signal supplied from the unique word detection circuit 7 to execute a metric generation setting process for a signal portion that subsequently arrives. The error correction circuit 6 Viterbi-decodes the input signal with a built-in Viterbi decoder according to the setting under the control of the control circuit 10 and supplies the input signal to the RS decoding circuits 11 and 12. Upon receiving the Viterbi-decoded signal supplied from the error correction circuit 6, the RS decoding circuit 11 corrects the transmission path error of the main signal and outputs a composite signal (received stream) to the outside.
When the RS decoding circuit 12 receives the supply of the Viterbi-decoded signal from the error correction circuit 6, the RS decoding circuit 12 corrects the transmission path error of the TMCC signal and supplies the corrected TMCC signal to the TMCC decoder 8.

[0009] The TMCC decoder 8 outputs
When the supply of the TMCC signal with the transmission path error corrected is received, the input TMCC signal is decoded, and the composite signal is output to the outside. The TMCC information including the transmission parameters such as the modulation scheme and coding rate of the subsequent main signal section is transmitted to the control circuit 10.
Supplied to The control circuit 10 outputs from the TMCC decoder 8
Upon receiving the supply of the decoding result, the Viterbi decoder of the error correction circuit 6 is controlled based on the supplied transmission parameters, and the metric generation is set so as to correspond to the subsequently supplied main signal portion.

That is, when each circuit of the satellite digital broadcast receiver 1 processes a received broadcast signal, a feed forward system including a unique word detection circuit 7 and a control circuit 10 controls the error correction circuit 6 to control the carrier wave. , A unique word (sync signal) is detected from the RS decoding circuit 12,
A feedback system including the TMCC decoder 8 and the control circuit 10 extracts TMCC information based on the synchronization signal, and causes the error correction circuit 6 to process a subsequently arriving main signal by feedback of the information. Further, the carrier recovery circuit 9 receives the supply of the phase error of the pilot carrier scattered for synchronous recovery from the unique word detection circuit 7 which has detected the frame synchronization signal, generates a carrier based on the supply, and generates a carrier based on the carrier. Feedback to 5

In the above-described TMCC system, the signal configuration information (TMCC information) of the entire transmission signal is transmitted to the satellite digital broadcast receiver 1, and the control circuit 10 of the satellite digital broadcast receiver 1 transmits the signal configuration information. Since each circuit of the satellite digital broadcast receiver 1 is controlled based on the TMCC information,
The reliability of transmission of TMCC information needs to be sufficiently high. Therefore, a transmission signal of TMCC information (hereinafter, referred to as a TMCC signal) is modulated by BPSK, and its error correction code is a concatenated code of a convolutional code and an RS code.

[0012]

When a signal stream encoded by a convolutional code is Viterbi-decoded by a Viterbi decoder inside an error correction circuit 6 of the satellite digital broadcast receiver 1, a burst-like signal is output at the output of the Viterbi decoder. It is known that various errors occur. In this case,
Normally, interleave processing is performed before signal information is subjected to convolutional coding and after Viterbi decoding, and this burst error is spread and supplied to the next RS decoding circuit, so that error correction in the RS decoding circuit is not possible. It is controlled not to be possible. However, in the transmission of the TMCC information, the interleave processing is not performed because the interleave processing causes a delay in the TMCC signal, which is not preferable for operation. Therefore, although there is a very low probability, there is a problem that the satellite digital broadcast receiver 1 malfunctions when there is an error in the TMCC signal.

The present invention has been made in view of such a situation, and enables, for example, to perform stable reception / decoding control even when an error occurs in a TMCC signal.

[0014]

According to a first aspect of the present invention, there is provided a digital signal demodulation device for storing an error correcting means for correcting an error of an input signal and a signal corresponding to the input signal corrected by the error correcting means. And a control unit for controlling updating of the storage of the storage unit in accordance with the correction result by the error correction unit.

According to a sixth aspect of the present invention, there is provided a digital signal demodulation method, comprising: an error correction step for correcting an error in an input signal; a storage step for storing a signal corresponding to the input signal corrected in the error correction step; And a control step of controlling updating of the storage in the storage step in accordance with the correction result in the correction step.

According to a seventh aspect of the present invention, there is provided the medium, wherein the error correcting step corrects an error in the input signal, the storing step stores a signal corresponding to the input signal corrected in the error correcting step, and the error correcting step. A program for causing the digital signal demodulation device to execute a process including a control step of controlling updating of the storage in the storage step in accordance with the correction result in the step (a).

A digital signal demodulator according to claim 1,
In the digital signal demodulating method according to the sixth aspect and the providing medium according to the seventh aspect, an error of an input signal is corrected, a signal corresponding to the corrected input signal is stored, and a correction result is stored. Then, updating of the memory is controlled.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below. In order to clarify the correspondence between each means of the invention described in the claims and the following embodiments, each means is described. When the features of the present invention are described by adding the corresponding embodiment (however, an example) in parentheses after the parentheses, the result is as follows. However, of course, this description does not mean that each means is limited to those described.

The digital signal demodulation device according to the first aspect of the present invention provides an error correction means for correcting an error in an input signal.
Steps S3 and S4 in FIG. 2), storage means for storing a signal corresponding to the input signal corrected by the error correction means (for example, register 33 in FIG. 1), and a correction result corresponding to the error correction means. The control means for controlling the updating of the storage of the storage means (for example, steps S22 to S2 in FIG. 3)
4).

The digital signal demodulation device according to a second aspect is characterized by further comprising decoding means (for example, the TMCC decoder 8 in FIG. 1) for decoding the input signal corrected by the error correction means.

An embodiment of a digital satellite broadcast receiver to which the digital signal demodulator of the present invention is applied will be described below with reference to the drawings. FIG. 1 shows an RS decoding circuit 1 in the conventional satellite digital receiver 1 shown in FIG.
2 is an example in which a flag corresponding to each of the cases where a transmission path error (hereinafter, referred to as an error) can or cannot be corrected is output and a received signal is controlled using this flag. FIG. The RS decoding circuit 12 RS-decodes the input TMCC signal,
When error correction of the CC signal is possible or impossible, corresponding flags are generated, and both are output to the protection circuit 31. When receiving the flag from the RS decoding circuit 12, the data selector 32 of the protection circuit 31 selects either the TMCC signal from the RS decoding circuit 12 or the TMCC signal from the register 33 in accordance with the flag. Then, the data is output to the TMCC decoder 8 and the register 33 as appropriate. Other configurations are the same as those in FIG.

Next, the error correction processing by the RS decoding circuit 12 will be described with reference to the flowchart of FIG. First, in step S1, the RS decoding circuit 12 waits until the Viterbi-decoded TMCC signal is supplied from the error correction circuit 6. Upon receiving the supply of the TMCC signal, the process proceeds to step S2, where the RS decoding circuit 12 performs RS decoding of the TMCC signal. The RS code of the TMCC signal is (64, 48) and 64
When an error of 9 bytes or more exists in the RS code of a byte, the code cannot be corrected. In step S3, the RS decoding circuit 12 determines whether or not the RS-decoded signal has 9 bytes or more of error data (error correction is not possible). If it is determined that the error data has less than 9 bytes (error correction is possible), the process proceeds to step S4 to correct the error data. Further, in step S5, the RS decoding circuit 12 outputs, to the data selector 32 of the protection circuit 31, the error-corrected TMCC information and a flag indicating that error correction has been enabled in accordance with the information.

On the other hand, if it is determined in step S3 that the RS-decoded TMCC information contains error data of 9 bytes or more (error correction is impossible), the process proceeds to step S6, where the RS decoding circuit 12 The uncorrectable TMCC information and the flag indicating that the error correction was impossible are output to the data selector 32 of the protection circuit 31 in accordance with the information.

After the processing of steps S5 and S6 is completed,
Proceeding to step S7, the RS decoding circuit 12
It is determined whether all CC signals have been completed. TM supplied
If it is determined that all CC signals have not been completed yet,
Returning to step S1, the RS decoding circuit 12 performs the subsequent processing. When it is determined that all the supplied TMCC signals have been completed, the RS decoding circuit 12 ends all the processes.

Next, the data selector 32 of the protection circuit 31
Will be described with reference to the flowchart of FIG. First, in step S21, the data selector 32 outputs, from the RS decoding circuit 12, the RS-decoded TMCC signal (output in step S5 or S6 in FIG. 2) and the corresponding TMCC information error. It waits until a flag indicating presence / absence is received. TMCC
When the signal and the corresponding flag are supplied, the process proceeds to step S22, and the data selector 32 determines that the received flag is a flag indicating that error correction is impossible (the flag output in step S6 in FIG. 2). ) Is determined.

If it is determined in step S22 that the received flag is a correctable flag (the flag output in step S5 in FIG. 2), the process proceeds to step S22.
Proceeding to 24, the data selector 32 responds to this (indicating that there is no error in the data) flag and
Supply TMCC signal to register 33 and store it (update)
And outputs it to the TMCC decoder 8.

If it is determined that the received flag is an error-correctable flag, the process proceeds to step S23, where the data selector 32 does not output the received TMCC signal to the register 33 in accordance with the flag. The error-free TMCC information (stored in step S24) stored in the register 33 is output to the TMCC decoder 8 and supplied to the register 33 to be stored again.

After the processing of steps S23 and S24 is completed, the process proceeds to step S25, where the data selector 32 determines whether or not all the supplied data has been completed. If it is determined that all the supplied data has not been completed, the process returns to step S21, and the data selector 32 executes the subsequent processing. When it is determined that all the supplied data has been completed, the data selector 32 ends all the processing.

FIG. 4 is a block diagram showing a configuration example in the case where the data selector 32 of the protection circuit 31 is removed and the register 33 is replaced with a register 34 having an enable function in the digital satellite broadcast receiver 1 shown in FIG. It is. When an error-correctable flag is supplied from the RS decoding circuit 12 to the enable terminal EN of the protection circuit 31, the register 34 of the protection circuit 31 holds the TMCC information output from the RS decoding circuit 12 internally and disables error correction. When flags are supplied,
Do not update TMCC information. Other configurations and operations are the same as those in FIG.

FIG. 5 is a block diagram showing a configuration example in the case where the protection circuit 31 is relocated to the output position of the TMCC decoder 8 in the digital satellite broadcast receiver 1 shown in FIG. The RS decoding circuit 12 outputs the RS-decoded TMCC information to the TMCC decoder 8 and outputs a flag corresponding to the error correction result of the TMCC information to the data selector 32 of the protection circuit 31.

The data selector 32 of the protection circuit 31
When receiving the supply of the decoded TMCC information from the CC decoder 8 and the supply of the corresponding flag from the RS decoding circuit 12, either the TMCC information or the TMCC information from the register 33 is transmitted in accordance with the flag. And outputs it to the register 33, the control circuit 10, and the outside. Other configurations are the same as those in FIG. That is, in the embodiment of FIG. 1, TMCC information before decoding is held, but in this embodiment, TMCC information after decoding is held.

In the present specification, a providing medium for providing a user with a computer program for executing the above-mentioned processing includes an information recording medium such as a magnetic disk and a CD-ROM, and a network such as the Internet and a digital satellite. Transmission media is also included.

[0033]

As described above, according to the digital signal demodulation device according to the first aspect, the digital signal demodulation method according to the sixth aspect, and the providing medium according to the seventh aspect, the error of the input signal can be reduced. Correction and control of updating the storage of the signal corresponding to the input signal in accordance with the correction result, so that the robustness of the input signal to transmission line errors is further enhanced and stable reception / decoding control is performed. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a digital signal demodulator to which the present invention is applied.

FIG. 2 is a flowchart illustrating an operation of the RS decoding circuit 12 of FIG. 1;

FIG. 3 is a flowchart illustrating an operation of a data selector 32 of FIG. 1;

FIG. 4 is a block diagram showing a configuration of a main part of another embodiment of a digital signal demodulator to which the present invention is applied.

FIG. 5 is a block diagram showing a configuration of another embodiment of a digital signal demodulation device to which the present invention is applied.

FIG. 6 is a block diagram illustrating a configuration example of a conventional satellite digital broadcast receiver.

[Explanation of symbols]

1 satellite digital broadcasting receiver, 2 antenna, 3
Tuner, 4 second intermediate frequency circuit, 5 quadrature demodulation circuit, 6 error correction circuit, 7 unique word detection circuit, 8 TMCC decoder, 9 carrier recovery circuit,
10 control circuit, 11, 12 RS decoding circuit, 13,
14 multiplier, 15, 16 low-pass filter, 3
1 protection circuit, 32 data selectors, 33, 34
register

Claims (7)

[Claims] 1. A digital signal demodulator for demodulating a digitally modulated input signal, comprising: an error correction unit for correcting an error of the input signal; and a signal corresponding to the input signal after being corrected by the error correction unit. A digital signal demodulation device, comprising: a storage unit for storing the data; and a control unit for controlling updating of the storage of the storage unit in accordance with a correction result by the error correction unit. 2. The digital signal demodulation device according to claim 1, further comprising decoding means for decoding said input signal corrected by said error correction means. 3. The digital signal demodulator according to claim 2, wherein said storage means stores a signal corresponding to said input signal before being decoded by said decoding means. 4. The digital signal demodulator according to claim 2, wherein said storage means stores a signal corresponding to said input signal after being decoded by said decoding means. 5. The digital signal demodulator according to claim 1, wherein the input signal is an auxiliary signal including information used for decoding a main signal. 6. A digital signal demodulation method for demodulating a digitally modulated input signal, comprising: an error correction step of correcting an error of the input signal; and a signal corresponding to the input signal after being corrected in the error correction step. A digital signal demodulation method, comprising: a storage step of storing the data; and a control step of controlling updating of the storage in the storage step in accordance with a correction result in the error correction step. 7. A digital signal demodulator for demodulating a digitally modulated input signal, comprising: an error correction step of correcting an error of the input signal; and a signal corresponding to the input signal corrected in the error correction step. Providing a program for executing a process including: a storage step of storing, and a control step of controlling updating of storage in the storage step in accordance with a correction result in the error correction step. Medium.