JP2009100370A - Transfer control information processing circuit and receiving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transfer control information processing circuit for actualizing stable reception, and to provide a receiving device having the same. <P>SOLUTION: The transfer control information processing circuit comprises a demodulating circuit 10 for demodulating transfer control information to identify a transfer system for digital signals in accordance with transfer signals transferred frame by frame and for outputting demodulated transfer control information, a buffer circuit 11 for holding the demodulated transfer control information for at least one frame, a multiplex circuit 12 for periodically multiprocessing the demodulated transfer control information from the demodulating circuit 10 and the demodulated transfer control information held by the buffer circuit 11 and for outputting the multiprocessed multiplex transfer control information, an error detecting and correcting circuit 18 for detecting and correcting an error of the demodulated transfer control information and/or the multiplex transfer control information, and a selecting circuit 16 for selecting the demodulated transfer control information or the multiplex transfer control information depending on information for the error detected by the error detecting and correcting circuit 18. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a transmission control information processing circuit for receiving a digital broadcast signal and a receiving apparatus having the transmission control information processing circuit.

  In recent years, digital transmission has been developed in order to transmit and receive high-quality audio and video signals. For example, digital transmission using an OFDM (Orthogonal Frequency Division Multiplexing) system is standardized in digital television broadcasting. In the OFMD system, modulation and demodulation are performed by assigning data to a plurality of carriers orthogonal to each other. An inverse fast Fourier transform (IFFT) process is performed on the transmission side, and a fast Fourier transform (FFT) process is performed on the reception side. In particular, in digital TV broadcasting in Japan, the transmitter can use any modulation method, so transmission control (TMCC: Transmission and Multiplexing Configuration Control) that identifies the transmission method such as the modulation method of the digital broadcast signal A signal (hereinafter referred to as “TMCC signal”) is added to the digital broadcast signal. The receiving apparatus demodulates and detects the received transmission control information (hereinafter referred to as “TMCC information”), and demodulates the digital broadcast signal according to the demodulated TMCC information.

  Here, digital broadcast signals are time-interleaved, that is, transmission data in the direction of the time axis as a countermeasure against transmission errors during transmission, for example, fading errors that are likely to occur during high-speed reception in a car or train. It is transmitted in a distributed manner. Further, the digital broadcast signal is encoded by an outer code RS (Reed-Solomon) code and further encoded by a convolutional code which is an inner code. For this reason, the digital broadcast signal is excellent in fading resistance.

  On the other hand, since the TMCC signal needs to be processed at a high speed, time interleaving is not used, and only a differential cyclic code is used as an error correction code. For this reason, even if the digital broadcast signal can be processed without any problem, the TMCC signal may not be processed due to an error.

  Here, since the same information is repeatedly transmitted in the TMCC signal, a time interleave similarity effect can be substantially obtained by using signal multiplexing processing. For example, Japanese Patent Laid-Open No. 2007-36730 discloses a receiving apparatus that multiplexes TMCC signals in units of frames.

However, in a receiving device that multiplexes TMCC signals, if there is a sudden large noise, the effect remains by performing multiplexing processing, and correct TMCC information cannot be acquired over a long period of time. There was a case. Also, in the case of emergency broadcasts that notify earthquakes, tsunamis, etc., or when the reception state is switched from TV reception to radio reception, the TMCC information is changed because the transmission parameters used are different. In such emergency broadcast reception and reception mode switching, the current information and next information of TMCC information are different, so if TMCC signal multiplexing processing is performed, correct TMCC information cannot be obtained, and malfunction of the receiving device There was a cause.
JP 2007-36730 A

  An object of the present invention is to provide a transmission control information processing circuit capable of stable reception and a receiving apparatus having the transmission control information processing circuit.

  A transmission control information processing circuit according to an aspect of the present invention includes a demodulation circuit that demodulates transmission control information that identifies a transmission method of a digital signal based on a transmission signal transmitted in units of frames and outputs demodulated transmission control information; A buffer circuit that holds the demodulated transmission control information for one frame, the demodulated transmission control information from the demodulator circuit, and the demodulated transmission control information held by the buffer circuit are periodically multiplexed, and the multiplexed processing is performed. A multiplexing circuit that outputs the multiplexed transmission control information, an error detection and correction circuit that detects and corrects errors in the demodulated transmission control information and / or the multiplexed transmission control information, and error information detected by the error detection and correction circuit. And a selection circuit for selecting any one of the demodulation transmission control information and the multiplex transmission control information.

  A receiving apparatus according to another aspect of the present invention includes the transmission control information processing circuit described above.

  The present invention provides a transmission control information processing circuit capable of stable reception and a receiving apparatus having the transmission control information processing circuit.

Embodiments of the present invention will be described below with reference to the drawings.
<First Embodiment>
FIG. 1 is a block diagram of a receiving apparatus 1 according to the first embodiment of the present invention, and FIG. 2 is a block diagram of a TMCC signal processing circuit 26 of the receiving apparatus 1.

  As shown in FIG. 1, a receiving apparatus 1 according to the present embodiment includes an antenna 20, a tuner 21, an analog / digital (A / D) converter 22, a quadrature detection circuit 23, an FFT circuit 24, and a main signal demodulation circuit 25. , A TMCC signal processing circuit 26 and an output circuit 27 are provided. Here, the main signal demodulating circuit 25 means a circuit for demodulating main signals such as video and audio, excluding at least the TMCC signal from the digital broadcast signal.

  The broadcast radio wave W from the broadcasting station B is received by the antenna 20, and the received high frequency band broadcast signal is converted from a signal of a predetermined channel to an intermediate frequency band by a tuner 21, and is converted to a digital signal by an A / D converter 22. Is converted to The digital signal from the A / D converter 22 is converted into a complex baseband signal by the quadrature detection circuit 23. The FFT circuit 24 converts the transmission signal on the time axis into data on the frequency axis by FFT calculation with respect to the complex baseband signal, separates it into a TMCC signal component and other main signal components, and outputs the result. The demodulating circuit 25 demodulates the main signal after the FFT operation according to the TMCC signal information from the TMCC signal processing circuit 26 and removes distortion components caused by the transmission path characteristics, and then various processes are performed by the output circuit 27. Finally, it is output in the form of sound or video.

  As shown in FIG. 2, the TMCC signal processing circuit 26 according to the present embodiment includes a demodulation circuit 10, a buffer circuit 11, a multiplexing circuit 12, an error detection and correction circuit 18, a selection circuit 16, and a control circuit 19. The demodulation circuit 10 demodulates the TMCC signal transmitted in frame units, and supplies the demodulated TMCC signal (hereinafter referred to as “demodulation signal”) to the error detection and correction circuit 18, the multiplexing circuit 12, and the buffer circuit 11. The error detection / correction circuit 18 corrects whether or not there is an error in the TMCC signal, and if there is an error. The buffer circuit 11 holds at least TMCC information for one frame period. The multiplexing circuit 12 periodically multiplexes the demodulated TMCC information demodulated by the demodulation circuit 10 and the TMCC information held by the buffer circuit 11 in units of frames, and a multiplexed TMCC signal (hereinafter, “multiplexed signal”) that has been multiplexed. Is supplied to the error detection and correction circuit 18.

Note that an infinite impulse response (IIR) calculation process may be used as a multiplexing method in the multiplexing circuit 12. The IIR process is not a simple synchronous addition, but is a process of adding 1 / n at a time as in the following equation. That is, if the demodulated TMCC signal from the demodulating circuit 10 is Tin, the TMCC signal held by the buffer circuit is D (t−1), and the multiplexed signal output from the multiplexing circuit 12 is D (t),
D (t) = D (t−1) × (n−1) / n + Tin / n
It becomes. In addition, as n, the value of about 1-30, Preferably about 7-15 is suitably selected by the receiving condition or the reliability of a receiving device. For example, when n = 8 is selected, every time one frame is processed, 1/8 of the multiplexed TMCC signal is replaced with a new demodulated TMCC signal.

  The selection circuit 16 selects either TMCC information of demodulated TMCC information or multiplexed TMCC information according to the information of the error detection / correction circuit 18, and outputs the selected TMCC information to the main signal demodulation circuit 25 shown in FIG. The TMCC information output from the TMCC signal processing circuit 26 is used in the main signal demodulation circuit 25 to determine the multiplexing mode, modulation scheme, interleave length, coding rate, etc. of the main signal.

  The control circuit 19 controls the entire TMCC signal processing circuit. Further, the countdown detection circuit 15 is not involved in the operation of the present embodiment.

  Next, the flow of signal processing in the TMCC signal processing circuit 26 of the present embodiment will be described with reference to FIG. FIG. 3 is a flowchart showing a processing flow of the TMCC signal processing circuit 26 according to the present embodiment.

<Step S10>
Processing of the TMCC signal processing circuit 26 is started by signal input from the FFT circuit 24. The TMCC demodulated signal demodulated by the demodulation circuit 10 is supplied to the error detection and correction circuit 18, the buffer circuit 11, and the multiplexing circuit 12.

<Step S11>
The error detection / correction circuit 18 detects whether there is an error in the TMCC demodulated signal, and corrects the error if there is an error. However, the number t of errors that can be corrected by the error detection / correction circuit 18 is defined when the error correction code is generated. For this reason, when the number of errors N is larger than t, all errors in the TMCC demodulated signal may not be corrected.

<Step S12>
It is determined whether or not error correction of the TMCC demodulated signal has been performed.
If all errors of the TMCC demodulated signal have been corrected (Yes), the demodulated signal after error correction is selected by the selection circuit 16 and transmitted to the main signal demodulation circuit 25 in step S13. Even if there is no error in the TMCC demodulated signal, it is determined in step S12 that error correction is possible, the demodulated signal is selected, and the TMCC demodulated signal that has not been subjected to error correction processing is mainly displayed as shown in step S18. It is transmitted to the signal demodulation circuit 25.

<Step S14>
In step S12, if all errors in the TMCC demodulated signal cannot be corrected (No), in step S14, it is detected whether there is an error in the multiplexed signal. If there is an error, the error is corrected.

<Step S15>
It is determined whether or not error correction of the TMCC multiplexed signal has been performed.
If all the errors of the TMCC multiplexed signal can be corrected (Yes), the multiplexed signal after error correction is selected by the selection circuit 16 in step S16 and transmitted to the main signal demodulation circuit 25 as shown in step S18. Is done.

<Step S17>
In step S15, if all errors of the TMCC multiplexed signal cannot be corrected (No), the TMCC signal used in the previous frame is selected and transmitted to the main signal demodulation circuit 25.
Alternatively, it is possible not to perform main signal processing for one frame without transmitting to the main signal demodulating circuit 25.

  As described above, in the TMCC signal processing circuit 26 according to the present embodiment, when the error of the demodulated TMCC signal can be corrected, the error correction process of the multiplexed TMCC signal is not performed. Is good. In addition, when the error of the demodulated TMCC signal cannot be corrected, the multi-TMCC signal is used, so that fading resistance is excellent. In addition, because demodulated TMCC signals are used preferentially over multiplexed TMCC signals, they are not affected by multiple TMCC signals that have been greatly deteriorated due to sudden noise and can be acquired for a long period of time. Enable reception.

  For this reason, the receiving apparatus 1 having the TMCC signal processing circuit 26 of the present embodiment can perform stable reception.

<Second Embodiment>
Next, the TMCC signal processing circuit 26B and the receiving device 2 including the TMCC signal processing circuit 26B according to the second embodiment of the present invention will be described.
FIG. 4 is a flowchart showing a process flow of the TMCC signal processing circuit 26B according to the present embodiment.

  The basic configuration of receiving apparatus 2 and TMCC signal processing circuit 26B in the present embodiment is the same as that of the first embodiment shown in FIGS. However, the signal processing of the TMCC signal processing circuit 26B in the present embodiment differs from the TMCC signal processing circuit 26 in that the multiplexed signal is given priority over the demodulated signal and transmitted to the main signal modulation circuit. Hereinafter, only different points from the first embodiment will be described.

  That is, as shown in the flowchart of FIG. 4, in the TMCC signal processing circuit 26B according to the present embodiment, it is first determined in step S22 whether an error of the multiplexed signal can be corrected. If the error of the multiplexed signal cannot be corrected, it is determined whether the error of the demodulated signal can be corrected in the subsequent step S25. In each of steps S22 and S25, if error correction is possible (Yes), the multiplexed TMCC signal and the demodulated TMCC signal are selected and supplied to the main signal demodulation circuit 25 as in step S28.

  Depending on the reception environment of the receiving device 2, for example, it is foreseen that an uncorrectable error will occur in the TMCC demodulated signal with a high probability, such as when moving in a valley of a building by a train or the like. In such a case, the TMCC signal processing 26B of the present embodiment that first selects a multiplexed signal having excellent fading resistance is more efficient than the TMCC signal processing of the first embodiment. Further, in the TMCC signal processing circuit 26B according to the present embodiment, when a multiplex signal is deteriorated due to sudden noise or the like, a demodulated signal can be selected in a subsequent step.

As described above, in the TMCC signal processing circuit 26B of the present embodiment, when the error of the multiplexed TMCC signal can be corrected, the error correction process of the demodulated TMCC signal is not performed, and thus the efficiency of the TMCC signal processing circuit is improved. good. In addition, since a demodulated TMCC signal can be selected, correct TMCC information can be obtained and stable reception can be obtained without being affected by multiple TMCC signals that have been greatly deteriorated due to sudden noise. .
For this reason, the receiving apparatus 2 having the TMCC signal processing circuit 26B of the present embodiment can perform stable reception.

  Note that the TMCC signal processing circuit 26 of the first embodiment and the TMCC signal processing circuit 26B of the present embodiment are configured in advance, automatically according to the reception state, or by the operation of the receiver. It is preferable to use by switching. The receiving apparatus 3 that switches between the TMCC signal processing circuit 26 of the first embodiment and the TMCC signal processing circuit 26B of the present embodiment can perform stable reception.

<Third Embodiment>
Next, the TMCC signal processing circuit 26C and the receiving device 4 having the TMCC signal processing circuit 26C according to the third embodiment of the present invention will be described.
As described above, TMCC information may be changed in order to change the transmission parameters used in the case of emergency broadcasts that notify an earthquake or tsunami. In this case, since the current information and the next information of the TMCC information are different, if the TMCC signal multiplexing process is performed, the TMCC signal cannot be correctly recognized, which may cause a malfunction.

  When changing the transmission parameter, a countdown signal is transmitted from the sender on the TMCC signal from 15 frames before. Here, the countdown signal is a signal that informs the countdown information, and among the transmission parameters, when changing parameters (carrier modulation, convolutional code coding rate, time interleave length, number of segments) that can be indicated by the TMCC information, This refers to changing the transmission parameter switching index in units of OFDM frames.

  The basic configuration of receiving apparatus 4 and TMCC signal processing circuit 26C in the present embodiment is the same as that of the first embodiment shown in FIGS. However, the countdown detection circuit 15 shown in FIG. 2 is an indispensable component. That is, as shown in FIG. 5, the TMCC signal processing circuit 26C according to the present embodiment has a countdown detection circuit 15 that detects countdown information. While the countdown detection circuit 15 is detecting countdown information, the selection circuit 16 The demodulated TMCC signal after error correction is selected and transmitted to the main signal demodulation circuit 25.

Therefore, when the countdown signal is received, the TMCC signal processing is changed to a demodulated TMCC signal. FIG. 5 is a flowchart for explaining the flow of processing in the TMCC signal processing circuit 26C of the present embodiment.
As shown in FIG. 5, in the TMCC signal processing circuit 26C of the present embodiment, it is determined No in step S31 until the countdown signal is received, and the flowchart (I) of the first or second embodiment. That is, the processing from FIG. 3 (I) or FIG. 4 (I) is performed.

  However, when the countdown signal is received, that is, when the countdown detection circuit 15 detects the countdown information, Yes is determined in step S31, and error correction of the demodulated signal is performed in step S32. The error detection / correction circuit 18 detects whether there is an error in the demodulated signal, and corrects the error if there is an error. If all errors of the demodulated signal can be corrected in step S33 (Yes), the demodulated signal after error correction is selected by the selection circuit 16 in step S34, and the main signal demodulation circuit 25 is selected in step S36. Sent to. Even if there is no error in the TMCC demodulated signal, it is determined in step S33 that error correction is possible, the demodulated signal is selected, and the TMCC demodulated signal not subjected to error correction processing is transmitted to the main signal demodulating circuit 25. Is done.

If all errors of the TMCC demodulated signal cannot be corrected in step S33 (No), the TMCC signal of the previous frame is selected in step S35. Alternatively, it is possible not to perform main signal processing for one frame without transmitting to the main signal demodulating circuit 25.
As described above, in the TMCC signal processing circuit 26C of the present embodiment, when the countdown signal is received, the multiplexed TMCC signal is not used even if the error of the demodulated TMCC signal cannot be corrected. Therefore, the TMCC signal processing circuit 26C of the present embodiment can acquire correct TMCC information and enables stable reception.

  For this reason, the receiving device 4 having the TMCC signal processing circuit 26C of the present embodiment can perform stable reception.

<Fourth embodiment>
Next, a TMCC signal processing circuit 26D and a receiving apparatus 5 including the TMCC signal processing circuit 26D according to the fourth embodiment of the present invention will be described.
As described above, at least one frame period of TMCC signal is subjected to multiplex processing, and in the IIR processing, a longer period of TMCC signal is subjected to multiplex processing. For this reason, even after the countdown signal is no longer received, the previous TMCC signal information for which the countdown signal is being received is stored in the buffer circuit 11.

  The basic configuration of receiving apparatus 5 and TMCC signal processing circuit 26D in the present embodiment is the same as that of the third embodiment shown in FIG. However, as shown in FIG. 6, the TMCC signal processing circuit 26D of the present embodiment selects the demodulated TMCC signal after error correction as the TMCC information for a certain period after the countdown detection circuit 15 detects the countdown information. That is, the TMCC signal processing circuit 26D changes the TMCC signal processing to the demodulated TMCC signal for a certain period of time even when the countdown signal is not being received or not. FIG. 6 is a flowchart for explaining the flow of processing in the TMCC signal processing circuit 26D of the present embodiment.

  As shown in FIG. 6, in the TMCC signal processing circuit 26D of the present embodiment, it is determined No in step S41 until the countdown signal is received, and the timer described later is 0. In step S48, Yes is determined, and the processing of the flowchart (I) of the first or second embodiment, that is, the processing from FIG. 3 (I) or FIG. 4 (I) is performed.

  On the other hand, in the TMCC signal processing circuit 26D of the present embodiment, when the countdown signal is received, Yes is determined in step S41, and the initial value K is input to the timer in step S42. During reception of the countdown signal, in principle, the demodulated signal is transferred to the main signal demodulating circuit 25 by the same processing (steps S43 to S47) as the TMCC signal processing circuit 26C of the third embodiment shown in FIG. Sent. During this time, the timer value t is always K.

  In the TMCC signal processing circuit 26D, when the countdown signal is not received, it is determined No in step 41. However, in step S48, the timer value t is not 0, but is K. The processing of the flowchart (I) of the first or second embodiment is not performed. That is, in step S49, the process of subtracting 1 from the timer value K is performed, and then the process of step S43 and subsequent steps is performed. In principle, the demodulated signal is transmitted to the main signal demodulating circuit 25.

  Then, after the countdown signal is not received, it becomes a K frame, and when the value of the timer t becomes 0, in step S48, the process of the flowchart (I) of the first or second embodiment, that is, the multiplexed signal It switches to the processing which may select.

  That is, it is possible to set a certain period in which the multiplexed TMCC signal is not used, specifically, K, which is the number of frames set in the timer t. Here, the K value is selected so that the influence of the TMCC signal before receiving the countdown signal is reduced to such an extent that it does not affect the multiplexed signal processing of the new TMCC information. For this reason, the K value differs depending on the multiplexing method, and is generally n when using an infinite impulse response (IIR) operation process in which 1 / n is added. That is, in the TMCC signal processing circuit 26D having a multiplexing circuit that performs 1 / n addition IIR processing, the multiplexed TMCC signal is not used for n frame periods after the countdown signal is received and completed. For example, when the countdown signal is transmitted for 15 frame periods, from when the countdown signal is received, that is, after the countdown detection circuit detects the countdown, until the process switches to a process that may select a multiplexed signal. The fixed period is (15 + n) frame periods.

As described above, in the TMCC signal processing circuit 26D according to the present embodiment, not only when the countdown signal is received, but also when the error of the demodulated TMCC signal cannot be corrected for a certain period after it is not received, Multiple TMCC signals are not used. Therefore, the TMCC signal processing circuit 26D according to the present embodiment can acquire correct TMCC information and enables stable reception.
For this reason, the receiving apparatus 5 having the TMCC signal processing circuit 26D of the present embodiment can perform stable reception.

<Fifth embodiment>
Next, a TMCC signal processing circuit 26E and a receiver 6 having a TMCC signal processing circuit 26E according to a fifth embodiment of the present invention will be described.
FIG. 7 is a flowchart showing a process flow of the TMCC signal processing circuit 26E according to the present embodiment.

  The basic configuration of receiving apparatus 6 and TMCC signal processing circuit 26E in the present embodiment is the same as that of the first embodiment shown in FIGS. However, the signal processing of the TMCC signal processing circuit 26E in the present embodiment is different in that the demodulated signal processing and the multiple signal processing are performed in parallel. Hereinafter, only different points from the first embodiment will be described.

  As shown in FIG. 7, the signal from the FFT circuit is directly transmitted to the error detection / correction circuit 18 as a demodulated signal via the demodulation circuit 10 and simultaneously transmitted to the multiplexing circuit 12 and multiplexed. The multiplexed signal is transmitted to the error detection and correction circuit 18. Since the TMCC signal processing circuit 26E performs parallel processing simultaneously with the demodulated signal processing (steps S51 to S53) and the multiple signal processing (steps S54 to S56), the TMCC signal of the first embodiment is sequentially processed. Compared with the processing circuit 26, the processing speed is high. However, in the TMCC signal processing circuit 26E, two circuits capable of performing error detection / correction processing at the same time are required in the error detection / correction circuit 18, so that the error detection / correction circuit 18 may be complicated and large. .

In other words, the TMCC signal processing circuit 26 of the first embodiment that sequentially performs the processing of the demodulated signal processing and the multiplexed signal processing in time series uses one error detection and correction circuit 18 in common. Therefore, the error detection and correction circuit 18 can be relatively simple and downsized.
The present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the scope of the present invention.

It is a block diagram of the receiver concerning a 1st embodiment of the present invention. 1 is a block diagram of a TMCC signal processing circuit according to a first embodiment of the present invention. FIG. It is a flowchart which shows the flow of a process of the TMCC signal processing time concerning the 1st Embodiment of this invention. It is a flowchart which shows the flow of a process of the TMCC signal processing time concerning the 2nd Embodiment of this invention. It is a flowchart which shows the flow of a process of the TMCC signal processing time concerning the 3rd Embodiment of this invention. It is a flowchart which shows the flow of a process of the TMCC signal processing time concerning the 4th Embodiment of this invention. It is a flowchart which shows the flow of a process of the TMCC signal processing time concerning the 5th Embodiment of this invention.

Explanation of symbols

1, 2, 3, 4, 5, 6, 7, receiving device, 10, demodulating circuit, 11, buffer circuit, 12, multiplexing circuit, 15, countdown detection circuit, 16, selection circuit, 18, error detection and correction circuit, DESCRIPTION OF SYMBOLS 19 ... Control circuit, 20 ... Antenna, 21 ... Tuner, 22 ... A / D converter, 23 ... Quadrature detection circuit, 24 ... FFT circuit, 25 ... Main signal demodulation circuit, 26, 26B, 26C, 26D, 26E ... TMCC Signal processing circuit, 27 ... output circuit

Claims (5)

A demodulation circuit that demodulates transmission control information for identifying a transmission method of a digital signal based on a transmission signal transmitted in frame units and outputs demodulated transmission control information;
A buffer circuit for holding the demodulated transmission control information for at least one frame;
A multiplexing circuit that periodically multiplexes the demodulation transmission control information from the demodulation circuit and the demodulation transmission control information held by the buffer circuit, and outputs the multiplexed transmission control information;
An error detection and correction circuit for detecting and correcting an error in the demodulation transmission control information and / or the multiplex transmission control information;
A transmission control information processing circuit comprising: a selection circuit that selects transmission control information of the demodulated transmission control information and the multiplex transmission control information according to error information detected by the error detection and correction circuit . The selection circuit includes:
The transmission control information processing circuit according to claim 1, wherein the demodulation transmission control information is selected when an error correction of the demodulation transmission control information is possible. It has a countdown detection circuit that detects countdown information,
The transmission control information processing circuit according to claim 1, wherein the selection circuit selects the demodulated transmission control information after the error correction while the countdown detection circuit is detecting the countdown information.   4. The transmission control information processing circuit according to claim 3, wherein the selection circuit selects the demodulated transmission control information after the error correction for a certain period after the countdown detection circuit detects the countdown information. 5. A receiving apparatus comprising the transmission control information processing circuit according to claim 1.

Images