CN101414993A - Transmission control information processing circuit and receiving apparatus - Google Patents
Transmission control information processing circuit and receiving apparatus Download PDFInfo
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- CN101414993A CN101414993A CNA2008101709058A CN200810170905A CN101414993A CN 101414993 A CN101414993 A CN 101414993A CN A2008101709058 A CNA2008101709058 A CN A2008101709058A CN 200810170905 A CN200810170905 A CN 200810170905A CN 101414993 A CN101414993 A CN 101414993A
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Abstract
The invention provides a transmission control information processing circuit capable of performing stable reception and a receiver having the transmission control information processing circuit. The transmission control information processing circuit comprises a demodulating circuit (10) for demodulating the transmission control information and outputting the demodulated transmission control information based on the transmission mode that transmits a signal recognition digital signal transmitted according to the frame unit, a multiplexing circuit (12) for periodically multiplexing the demodulated transmission control information from the demodulating circuit (10) and maintained by a buffer circuit (11), and outputting the multiplexed transmission control information, an error detection and correction circuit (18) for detecting and correcting the errors of the demodulated transmission control information and/or the multiplexed transmission control information, and a selection circuit (16) for selecting one of the demodulated transmission control information and the multiplexed transmission control information according to the error information detected by the error detection and correction circuit (18).
Description
Technical field
The present invention relates to the receiving system that is used for the transmission control information processing circuit of receiving digital broadcast signal and has this transmission control information processing circuit.
Background technology
In recent years, receive high-quality sound and vision signal, carried out the exploitation of digital delivery in order to send.For example, in digital television broadcasting, standardization is carried out in the digital delivery of using OFDM (OFDM) mode.In the OFDM mode, to mutually orthogonal a plurality of allocation of carriers data and carry out modulation and demodulation.Carry out inverse fast fourier transform (IFFT) at transmitter side and handle, carry out fast Fourier transform (FFT) at receiver side and handle.Especially, in the digital television broadcasting of Japan, because the sender can use modulation system arbitrarily, therefore, the transmission of the load modes such as modulation system of discriminating digit broadcast singal control (TMCC) signal (hereinafter referred to as " TMCC signal ") is attached on the digital broadcast signal.Receiving system carries out demodulation to the communicating control information (hereinafter referred to as " TMCC information ") that is received and detects, and according to the TMCC information of institute's demodulation, carries out the demodulation of digital broadcast signal.
At this, as the transmission mistake in transmitting, for example because the countermeasure that incidental decay makes a mistake in the reception in automobile or electric car etc. are mobile at a high speed, digital broadcast signal is by time-interleaved, that is, make and transmit that data are dispersed in time-axis direction and the mode that transmits transmits.Further, after RS (Read-Solomon) sign indicating number of digital broadcast signal sign indicating number outside using was encoded, the convolution code that further is used as ISN was encoded.Therefore, digital broadcast signal excellence aspect anti-decay.
Relative therewith, because therefore TMCC signal demand high speed processing, does not interweave service time, error correcting code is also only used the difference set cyclic code.Therefore, even digital broadcast signal carries out signal processing no problemly, also there is the situation that can not carry out signal processing owing to error in the TMCC signal.
At this,, therefore,, in fact can access time-interleaved similar effect by using the multiplexing process of signal because the TMCC signal repeats to transmit same information.For example, open in the 2007-36730 communique, disclose the multiplexing receiving system that carries out the TMCC signal with frame unit the spy.
But in carrying out the multiplexing receiving system of TMCC signal, when paroxysmal big interference etc. had taken place, by carrying out multiplexing process, its influence was remaining, had the situation that can not obtain correct TMCC information for a long time.In addition, under situations such as urgent broadcast such as notice earthquake or tsunami, perhaps accepting state is being switched to from television reception under the situation such as broadcast reception, because the difference of using that passes a parameter, therefore, TMCC information is changed.Under the situation that this urgent broadcast receives or receiving mode switches, because the current information of TMCC information is different with next information, therefore, if carry out the multiplexing process of TMCC signal, then can not obtain correct TMCC information, thereby become the reason of receiving system misoperation.
[patent documentation 1] spy opens the 2007-36730 communique
Summary of the invention
The object of the present invention is to provide a kind of receiving system that can carry out the transmission control information processing circuit of stable reception and have this transmission control information processing circuit.
The transmission control information processing circuit of a form of the present invention, it is characterized in that having: the communicating control information based on the load mode of the transmission signal discriminating digit signal that transmits with frame unit is carried out demodulation and exports the demodulator circuit of demodulation communicating control information; The buffer circuits of the above-mentioned demodulation communicating control information of the amount of maintenance at least 1 frame; Periodically the demodulation communicating control information that demodulation communicating control information and above-mentioned buffer circuits from above-mentioned demodulator circuit are kept carries out the multiplex circuit of the multiplexing communicating control information of multiplexing process and this multiplexing process of output process; The error detection that detects the wrong of above-mentioned demodulation communicating control information and/or above-mentioned multiplexing communicating control information and correct is corrected circuit; And correct the error message of electric circuit inspection according to above-mentioned error detection, select the selection circuit of any one communicating control information of above-mentioned demodulation communicating control information and above-mentioned multiplexing communicating control information.
In addition, the receiving system of another form of the present invention has above-mentioned transmission control information processing circuit.
The invention provides a kind of receiving system that can carry out the transmission control information processing circuit of stable reception and have this transmission control information processing circuit.
Description of drawings
Fig. 1 is the block diagram according to the receiving system of the 1st execution mode of the present invention.
Fig. 2 is the block diagram according to the TMCC signal processing circuit of the 1st execution mode of the present invention.
Fig. 3 is the flow chart that illustrates according to the handling process of the TMCC signal processing circuit of the 1st execution mode of the present invention.
Fig. 4 is the flow chart that illustrates according to the handling process of the TMCC signal processing circuit of the 2nd execution mode of the present invention.
Fig. 5 is the flow chart that illustrates according to the handling process of the TMCC signal processing circuit of the 3rd execution mode of the present invention.
Fig. 6 is the flow chart that illustrates according to the handling process of the TMCC signal processing circuit of the 4th execution mode of the present invention.
Fig. 7 is the flow chart that illustrates according to the handling process of the TMCC signal processing circuit of the 5th execution mode of the present invention.
Symbol description
1,2,3,4,5,6: receiving system; 10: demodulator circuit; 11: buffer circuits; 12: multiplex circuit; 15: testing circuit counts down; 16: select circuit; 18: error detection is corrected circuit; 19: control circuit; 20: antenna; 21: tuner; The 22:A/D converter; 23: orthogonal demodulation circuit; The 24:FFT circuit; 25: the main signal demodulator circuit; 26,26B, 26C, 26D, 26E:TMCC signal processing circuit; 27: output circuit.
Embodiment
Below, with reference to the description of drawings embodiments of the present invention.
＜the 1 execution mode 〉
Fig. 1 is the block diagram according to the receiving system 1 of the 1st execution mode of the present invention, and Fig. 2 is the block diagram of the TMCC signal processing circuit 26 of receiving system 1.
As shown in Figure 1, the receiving system 1 of present embodiment possesses: antenna 20, tuner 21, analog/digital (A/D) converter 22, orthogonal demodulation circuit 23, fft circuit 24, main signal demodulator circuit 25, TMCC signal processing circuit 26 and output circuit 27.At this, main signal demodulator circuit 25 is meant the circuit that main signals such as the video of removing the TMCC signal in the digital broadcast signal at least or sound are carried out demodulation.
Receive with antenna 20 from the broadcasting wave W of broadcasting station B, the broadcast singal of the high frequency band that is received is intermediate frequency band by tuner 21 with the signal transformation of specified channel, and is transformed to digital signal by A/D converter 22.Digital signal from A/D converter 22 is transformed to a plurality of baseband signals by orthogonal demodulation circuit 23.24 pairs of a plurality of baseband signals of fft circuit, calculating the transmission signal transformation on the time shaft by FFT is data on the frequency axis, and is separated into the component of the component of TMCC signal and main signal in addition and exports.Demodulator circuit 25 is according to the TMCC signal message from TMCC signal processing circuit 26, after main signal after FFT is calculated is carried out demodulation and is removed the distortion component that is caused by the transfer path characteristic, carry out various processing by output circuit 27, and finally become the form output of sound or video.
As shown in Figure 2, the TMCC signal processing circuit 26 of present embodiment possesses demodulator circuit 10, buffer circuits 11, multiplex circuit 12, error detection correction circuit 18, selects circuit 16 and control circuit 19.10 pairs of TMCC signals that transmit with frame unit of demodulator circuit carry out demodulation, and demodulation TMCC signal (hereinafter referred to as " restituted signal ") is offered error detection correction circuit 18, multiplex circuit 12 and buffer circuits 11.Error detection is corrected circuit 18 when the TMCC signal is whether wrong and wrong, carries out this error correcting.Buffer circuits 11 keeps the TMCC information of the amount of 1 image duration at least.Multiplex circuit 12 carries out multiplexing process with frame unit period ground to the demodulation TMCC information of demodulator circuit 10 demodulation and the TMCC information of buffer circuits 11 maintenances, and the multiplexing TMCC signal (hereinafter referred to as " multiplexed signals ") after the multiplexing process is offered error detection correction circuit 18.
In addition, as the multiplex mode of multiplex circuit 12, also can utilize the computing of infinite impulse response (IIR).It not is merely to carry out synchronous addition that IIR handles, but shown in following formula, be the processing that every 1/n carries out addition.That is, if will be made as Tin from the demodulation TMCC signal of demodulator circuit 10, the TMCC signal that buffer circuits is kept is made as D (t-1), and the multiplexed signals that multiplex circuit 12 is exported is made as D (t), then
D(t)＝D(t-1)×(n-1)/n+Tin/n
In addition,, select 1～30 degree aptly according to reliability of reception situation or receiving system etc. as n, preferably, the value of 7～15 degree.For example, when selecting n=8, for the processing of each 1 frame, 1/8 of multiplexing TMCC signal is changed into new demodulation TMCC signal.
The information of selecting circuit 16 to correct circuit 18 according to error detection is selected any one TMCC information of demodulation TMCC information and multiplexing TMCC information, and is outputed to main signal demodulator circuit 25 shown in Figure 1.The TMCC information of TMCC signal processing circuit 26 outputs is used for the judgement of multiplexer mode, modulation system, weaving length and the encoding rate etc. of main signal in main signal demodulator circuit 25.
In addition, control circuit 19 carries out the control of TMCC signal processing circuit integral body.In addition, the testing circuit 15 that counts down does not participate in the action of present embodiment.
Then with reference to Fig. 3, the flow process of signal processing of the TMCC signal processing circuit 26 of present embodiment is described.Fig. 3 is the flow chart that illustrates according to the handling process of the TMCC signal processing circuit 26 of present embodiment.
＜step S10 〉
According to signal input from fft circuit 24, the processing of beginning TMCC signal processing circuit 26.TMCC restituted signal by demodulator circuit 10 demodulation is provided for error detection correction circuit 18, buffer circuits 11 and multiplex circuit 12.
＜step S11 〉
Error detection is corrected circuit 18 and is detected whether there is not mistake in the TMCC restituted signal, when wrong, carries out the correction of this mistake.But the quantity t of the mistake that error detection correction circuit 18 can be corrected stipulates when error correcting code generates.Therefore, when the quantity N of mistake than t for a long time, the situation that also has whole mistakes of TMCC restituted signal not correct.
＜step S12 〉
Judge the error correcting that whether has carried out the TMCC restituted signal.
In the time can correcting whole mistake of TMCC restituted signal (being), in step S13,, send to main signal demodulator circuit 25 by selecting the restituted signal after circuit 16 is selected error correctings.In addition, even when in the TMCC restituted signal, not having mistake, also in step S12, be judged as and carry out error correcting, select restituted signal, will not carry out TMCC restituted signal that error correcting handles and shown in step S18, send to main signal demodulator circuit 25.
＜step S14 〉
In step S12, in the time can not correcting TMCC restituted signal whole wrong (denying), in step S14, detect whether wrongly in multiplexed signals, when wrong, carry out the correction of this mistake.
＜step S15 〉
Judge the error correcting that whether has carried out the TMCC multiplexed signals.
In the time can correcting TMCC multiplexed signals whole wrong (being), in step S16, by selecting the multiplexed signals after circuit 16 is selected error correctings, and shown in step S18, send to main signal demodulator circuit 25.
＜step S17 〉
In step S15, in the time can not correcting whole mistake of TMCC multiplexed signals (denying), be chosen in the TMCC signal that uses in the former frame, and send to main signal demodulator circuit 25.
Perhaps, also can not send to main signal demodulator circuit 25, thereby the main signal of not carrying out the amount of 1 frame is handled.
As mentioned above, in the TMCC of present embodiment signal processing circuit 26, in the time can correcting demodulation TMCC signal wrong, handle owing to do not carry out the error correcting of multiplexing TMCC signal, therefore, the efficient height of TMCC signal processing circuit.And, when the mistake of demodulation TMCC signal can not be corrected, owing to use multiplexing TMCC signal, therefore, excellence aspect anti-decay.In addition, owing to more preferably use demodulation TMCC signal than multiplexing TMCC signal, therefore, can not be subjected to causing the influence of the multiplexing TMCC signal that deteriorates significantly for a long time owing to the interference of burst, correct TMCC information can be obtained, thereby stable reception can be carried out.
Therefore, the receiving system 1 with TMCC signal processing circuit 26 of present embodiment can carry out stable reception.
＜the 2 execution mode 〉
Below, illustrate according to the TMCC signal processing circuit 26B of the 2nd execution mode of the present invention and receiving system 2 with TMCC signal processing circuit 26B.
Fig. 4 is the flow chart that illustrates according to the handling process of the TMCC signal processing circuit 26B of present embodiment.
The basic comprising of the receiving system 2 of present embodiment and TMCC signal processing circuit 26B is identical with the 1st execution mode illustrated in figures 1 and 2.But, in the signal processing of the TMCC of present embodiment signal processing circuit 26B, compare with restituted signal, more preferably use multiplexed signals, different with TMCC signal processing circuit 26 to main signal modulation circuit transmission this point.Below, the place different with the 1st execution mode only is described.
That is, shown in the flow chart of Fig. 4, in the TMCC of present embodiment signal processing circuit 26B,, judge whether to correct the mistake of multiplexed signals at first at step S22.Then, when the mistake of multiplexed signals can not be corrected, in the step S25 of back segment, judge whether to correct the mistake of restituted signal.In step S22 and S25, in the time can carrying out error correcting (being), select multiplexing TMCC signal and demodulation TMCC signal respectively, and providing to main signal demodulator circuit 25 shown in step S28.
According to the reception environment of receiving system 2, for example, in moving between building as electric car etc., predict the mistake that generation can not be corrected in the TMCC restituted signal high probability.In this case, be chosen in the side of TMCC signal processing 26B of present embodiment of the multiplexed signals of anti-decay aspect excellence at first, higher than the TMCC signal processing efficiency of the 1st execution mode.In addition, in the TMCC of present embodiment signal processing circuit 26B, when interference etc. owing to burst having taken place cause the deterioration of multiplexed signals, can in the step of back segment, select restituted signal.
As mentioned above, in the TMCC of present embodiment signal processing circuit 26B, in the time can correcting multiplexing TMCC signal wrong, handle owing to do not carry out the error correcting of demodulation TMCC signal, therefore, the efficient height of TMCC signal processing circuit.In addition, owing to can select demodulation TMCC signal, therefore, can not be subjected to for a long time because the interference of burst and the influence of the multiplexing TMCC signal of deterioration greatly can obtain correct TMCC information, thereby can carry out stable reception.
Therefore, the receiving system 2 with TMCC signal processing circuit 26B of present embodiment can carry out stable reception.
In addition, the TMCC signal processing circuit 26B of the TMCC signal processing circuit 26 of the 1st execution mode and present embodiment preferably, in advance or according to accepting state, automatically or according to recipient's operation switches the use circuit.So the receiving system 3 of the TMCC signal processing circuit 26 of switching use the 1st execution mode and the TMCC signal processing circuit 26B of present embodiment can carry out stable reception.
＜the 3 execution mode 〉
The following describes according to the TMCC signal processing circuit 26C of the 3rd execution mode of the present invention and receiving system 4 with TMCC signal processing circuit 26C.
As previously mentioned, under situations such as urgent broadcast such as notice earthquake or tsunami, owing to change employed passing a parameter, therefore, TMCC information also is changed.In this case, because the current information of TMCC information is different with next information, therefore, carries out the multiplexing process of TMCC signal and can not discern correct TMCC information, thereby become the reason of misoperation.
When change passed a parameter, before 15 frames, the signal person of being sent out that counts down was carried on the TMCC signal and is sent.At this, the signal that counts down is a signal of notifying the information that counts down, when being meant the parameter (encoding rate of carrier modulation, convolution code, time-interleaved length, segments) of the enough TMCC information indications of energy among change passes a parameter, change the switching index that passes a parameter with OFDM frame unit.
The basic comprising of the receiving system 4 of present embodiment and TMCC signal processing circuit 26C is the same with the 1st execution mode illustrated in figures 1 and 2.But the testing circuit 15 that counts down shown in Figure 2 becomes indispensable inscape.Promptly, as shown in Figure 5, the TMCC signal processing circuit 26C of present embodiment has the testing circuit 15 that counts down that detects the information that counts down, detect in the information that counts down at the testing circuit 15 that counts down, selection circuit 16 is selected the demodulation TMCC signal behind the error correctings and is sent to main signal demodulator circuit 25.
Therefore, when reception counts down signal, the TMCC signal processing is changed into demodulation TMCC signal.Fig. 5 is the flow chart of handling process that is used to illustrate the TMCC signal processing circuit 26C of present embodiment.
As shown in Figure 5, in the TMCC of present embodiment signal processing circuit 26C, till reception counts down signal, in step S31, be judged as not, carry out the processing of the flow chart (I) of the 1st or the 2nd execution mode, that is, and from the processing of Fig. 3 (I) or Fig. 4 (I) beginning.
But when having received when counting down signal, that is, when the testing circuit 15 that counts down detects when counting down information, being judged as in step S31 is in step S32, to carry out the error correcting of restituted signal.Error detection is corrected circuit 18 and is detected whether there is not mistake in restituted signal, when wrong, carries out the correction of this mistake.Then, in step S33, in the time can correcting whole mistake of restituted signal (being), in step S34,, in step S36, send to main signal demodulator circuit 25 by selecting the restituted signal after circuit 16 is selected error correctings.In addition,, also in step S33, be judged as and carry out error correcting, select restituted signal, and will not carry out the TMCC restituted signal that error correcting handles and send to main signal demodulator circuit 25 even when in the TMCC restituted signal, not having mistake.
In step S33, in the time can not correcting whole mistake of TMCC restituted signal (denying), in step S35, select the TMCC signal of former frame.Perhaps, also can not send to main signal demodulator circuit 25, thereby the main signal of not carrying out the amount of 1 frame is handled.
As mentioned above, in the TMCC of present embodiment signal processing circuit 26C, when having received when counting down signal, even when the mistake of demodulation TMCC signal can not be corrected, also do not use multiplexing TMCC signal.Therefore, in the TMCC of present embodiment signal processing circuit 26C, can obtain correct TMCC information, thereby can carry out stable reception.
Therefore, the receiving system 4 with TMCC signal processing circuit 26C of present embodiment can carry out stable reception.
＜the 4 execution mode 〉
Below explanation is according to the TMCC signal processing circuit 26D of the 4th execution mode of the present invention and the receiving system 5 with TMCC signal processing circuit 26D.
As mentioned above, multiplexed signals carries out multiplexing process to the TMCC signal of the amount of at least 1 image duration, and in IIR handled, further the TMCC signal to long-standing amount carried out multiplexing process.Therefore, after not receiving the signal that counts down, the former TMCC signal message in the signal that also reception counted down is stored in the buffer circuits 11.
The basic comprising of receiving system 5 in the present embodiment and TMCC signal processing circuit 26D is the same with the 3rd execution mode shown in Figure 3.But, as shown in Figure 6, the TMCC signal processing circuit 26D of present embodiment after the testing circuit 15 that counts down detects the information of counting down, the demodulation TMCC signal behind the TMCC Information Selection error correcting during certain.That is, much less TMCC signal processing circuit 26D, begins even never receive signal in reception counts down signal, also during necessarily, the TMCC signal processing is transformed to demodulation TMCC signal.Fig. 6 is the flow chart of handling process that is used to illustrate the TMCC signal processing circuit 26D of present embodiment.
As shown in Figure 6, in the TMCC of present embodiment signal processing circuit 26D, till reception counts down signal, in step S41, be judged as not, in addition, the timer of explanation becomes 0 later on, therefore, being judged as in step S48 is to carry out the processing of the flow chart (I) of the 1st or the 2nd execution mode, that is, from the processing of Fig. 3 (I) or Fig. 4 (I) beginning.
Relative therewith, in the TMCC of present embodiment signal processing circuit 26D, if receive the signal that counts down, then being judged as in step S41 is in step S42, to import initial value K to timer.Then, in reception counted down signal, (step S43～S47), in principle, restituted signal was sent to main signal demodulator circuit 25 by the processing the same with the TMCC signal processing circuit 26C of the 3rd execution mode shown in Figure 5.In addition, during this period, the value t of timer is K all the time.
Then, in TMCC signal processing circuit 26D, if do not receive the signal that counts down, then in step S41, be not judged as not, and in step S48, because the value t of timer is not 0 but K, therefore, do not carry out the processing of the flow chart (I) of the 1st or the 2nd execution mode.That is, in step S49, carried out deducting 1 processing from the value K of timer after, carry out the later processing of step S43, in principle, restituted signal is sent to main signal demodulator circuit 25.
Then, never receive the signal that counts down and begin to become the K frame,, then in step S48, switch to the processing of the flow chart (I) of the 1st or the 2nd execution mode, that is, select the situation of multiplexed signals in addition if the value of timer t becomes 0.
That is, can set as during not using multiplexing TMCC signal certain, specifically the K of the number of the frame that in timer t, is provided with.At this, the K value so that the little mode of handling affected degree to the multiplexed signals that does not make new TMCC information of the influence of the TMCC signal of the signal that counts down before receiving select.Therefore, the K value is because multiplex mode and difference, when utilizing every 1/n to carry out the computing of infinite impulse response (IIR) of addition, roughly becomes n.That is, in having the TMCC signal processing circuit 26D that carries out the multiplex circuit that 1/n addition IIR handles, after reception counts down signal ended, do not use multiplexing TMCC signal image duration at n.In addition, count down signal when for example be sent out 15 image durations, from having received the signal that counts down, promptly, detect from the testing circuit that counts down and to count down, during certain till the processing that switches to the situation of selecting multiplexed signals in addition, become (15+n) image duration.
As mentioned above, in the TMCC of present embodiment signal processing circuit 26D, under reception counts down the situation of signal certainly much less, after not receiving necessarily during, even under the situation of the mistake that can not correct demodulation TMCC signal, do not use multiplexing TMCC signal yet.Therefore, in the TMCC of present embodiment signal processing circuit 26D, can obtain correct TMCC information, thereby can carry out stable reception.
Therefore, the receiving system 5 with TMCC signal processing circuit 26D of present embodiment can carry out stable reception.
＜the 5 execution mode 〉
Then explanation is according to the TMCC signal processing circuit 26E and the receiving system 6 with TMCC signal processing circuit 26E of the 5th execution mode of the present invention.
Fig. 7 is the flow chart that illustrates according to the handling process of the TMCC signal processing circuit 26E of present embodiment.
The basic comprising of the receiving system 6 of present embodiment and TMCC signal processing circuit 26E is the same with the 1st execution mode illustrated in figures 1 and 2.But, in the signal processing of the TMCC of present embodiment signal processing circuit 26E, handle on this point different with multiplexed signals in the parallel demodulation signal processing of carrying out.Below, the difference with the 1st execution mode only is described.
As shown in Figure 7, via demodulator circuit 10, directly send to error detection as restituted signal and correct circuit 18, send to multiplex circuit 12 simultaneously, and send to error detection as the multiplexed signals after multiplexing and correct circuit 18 from the signal of fft circuit.In TMCC signal processing circuit 26E, owing to parallelly simultaneously carry out demodulation signal processing (step S51～S53) and multiplexed signals handled (step S54～S56), therefore, compare with the TMCC signal processing circuit 26 of the 1st execution mode of sequentially handling, processing speed is fast.But, in TMCC signal processing circuit 26E, correct 2 circuit handling owing to need to carry out simultaneously error detection in the inside of error detection correction circuit 18, therefore, error detection is corrected circuit 18 complexity and is maximized.
On the contrary, sequentially carry out the TMCC signal processing circuit 26 of the 1st execution mode of the processing that demodulation signal processing and multiplexed signals handle according to time series, correct circuit 18 owing to can use 1 error detection jointly, therefore, error detection correction circuit 18 can compare simple and miniaturization.
The present invention is not limited to above-mentioned execution mode, in the scope that does not break away from purport of the present invention various changes, change etc. can be arranged.
Claims (5)
1. transmission control information processing circuit is characterized in that having:
Demodulator circuit, it carries out demodulation to the communicating control information based on the load mode of the transmission signal discriminating digit signal that transmits with frame unit, and output demodulation communicating control information;
Buffer circuits, it keeps the above-mentioned demodulation communicating control information of the amount of at least 1 frame;
Multiplex circuit, it periodically carries out multiplexing process to the demodulation communicating control information that demodulation communicating control information and above-mentioned buffer circuits from above-mentioned demodulator circuit keep, and output is through the multiplexing communicating control information of this multiplexing process;
Error detection is corrected circuit, and it detects the wrong of above-mentioned demodulation communicating control information and/or above-mentioned multiplexing communicating control information and corrects; And
Select circuit, it corrects the error message of electric circuit inspection according to above-mentioned error detection, selects any one communicating control information of above-mentioned demodulation communicating control information and above-mentioned multiplexing communicating control information.
2. transmission control information processing circuit according to claim 1 is characterized in that:
Above-mentioned selection circuit is selected above-mentioned demodulation communicating control information in the time can carrying out the error correcting of above-mentioned demodulation communicating control information.
3. transmission control information processing circuit according to claim 1 is characterized in that:
Have the testing circuit that counts down that detects the information that counts down,
Above-mentioned selection circuit detects in the information that counts down at the above-mentioned testing circuit that counts down, and selects the demodulation communicating control information behind the above-mentioned error correcting.
4. transmission control information processing circuit according to claim 3 is characterized in that: above-mentioned selection circuit during certain, is selected the demodulation communicating control information behind the above-mentioned error correcting after the above-mentioned testing circuit that counts down detects the information that counts down.
5. a receiving system is characterized in that: have any described transmission control information processing circuit of claim 1 to claim 4.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007271632A JP2009100370A (en) | 2007-10-18 | 2007-10-18 | Transfer control information processing circuit and receiving device |
| JP271632/2007 | 2007-10-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101414993A true CN101414993A (en) | 2009-04-22 |
| CN101414993B CN101414993B (en) | 2011-11-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101709058A Expired - Fee Related CN101414993B (en) | 2007-10-18 | 2008-10-16 | Transmission control information processing circuit and receiving apparatus |
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| JP (1) | JP2009100370A (en) |
| CN (1) | CN101414993B (en) |
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| CN113302858A (en) * | 2019-01-22 | 2021-08-24 | 索尼半导体解决方案公司 | Demodulation circuit, demodulation method, and transmission device |
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| JP6164965B2 (en) * | 2013-07-26 | 2017-07-19 | 京セラ株式会社 | Receiving apparatus and receiving method |
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| JP2007116322A (en) * | 2005-10-19 | 2007-05-10 | Victor Co Of Japan Ltd | Channel search method of digital broadcast receiver |
| JP4680809B2 (en) * | 2006-03-17 | 2011-05-11 | 富士通株式会社 | OFDM demodulator |
| JP4772550B2 (en) * | 2006-03-24 | 2011-09-14 | 富士通株式会社 | OFDM demodulator |
-
2007
- 2007-10-18 JP JP2007271632A patent/JP2009100370A/en active Pending
-
2008
- 2008-10-16 CN CN2008101709058A patent/CN101414993B/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102447967A (en) * | 2010-09-10 | 2012-05-09 | 索尼公司 | Receiver, reception method and program |
| CN102447967B (en) * | 2010-09-10 | 2016-12-21 | 索尼公司 | Receptor, method of reseptance and reception system |
| CN113302858A (en) * | 2019-01-22 | 2021-08-24 | 索尼半导体解决方案公司 | Demodulation circuit, demodulation method, and transmission device |
| CN113302858B (en) * | 2019-01-22 | 2024-01-23 | 索尼半导体解决方案公司 | Demodulation circuit, demodulation method, and transmitter |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2009100370A (en) | 2009-05-07 |
| CN101414993B (en) | 2011-11-16 |
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