JP2000004409A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a receiver to accurately reproduce information modulated in plural modulation systems at plural coding rates by optimizing the amplitude or the power of an input signal for each transmission system. SOLUTION: In the case of receiving and demodulating a signal in which a modulation wave modulated in plural modulation system by a BS antenna 2 is time-divided and multiplexed, a BER measurement circuit 8 measures or estimates a bit error rate in the each modulation system and a gain control circuit 9 optimizes the amplification rate of a variable gain amplifier circuit 3 based on the result of the measurement or the estimation for the every modulation system. Then the modulated wave is demodulated/decoded while the performance at the time of carrying out Viterbi decoding or trellis decoding by a trellis/Viterbi decoding circuit 7 is not deteriorated and an HDTV 19 reproduces the contents of a program sent from a transmitter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for measuring or estimating a bit error rate (BER) of each transmission system when receiving and demodulating a broadcast wave including a plurality of transmission systems. The present invention relates to a receiving apparatus that optimizes a demodulated signal level for each time so that performance in Viterbi decoding or trellis decoding is not deteriorated.

[Summary of the Invention] [0002] The present invention relates to a receiving apparatus used in digital broadcasting and the like, in which data to be transmitted has a frame structure and a plurality of modulation schemes are switched in one frame section for transmission. When receiving and demodulating a broadcast wave transmitted from a transmission device of a transmission system, measure or estimate a bit error rate of each transmission system, optimize a demodulation signal level for each transmission system, and perform Viterbi decoding or trellis decoding. This is to prevent the performance when performing the operation from deteriorating.

[0003]

2. Description of the Related Art When a digitally modulated wave is received, an RF (high frequency) band received signal obtained from an antenna is frequency-converted into an IF (intermediate frequency) band signal, and the amplitude or power of the signal is converted. A method of controlling an AGC (automatic gain control) amplifier so that the signal becomes equal to a reference value, or a method of performing frequency conversion to convert an IF band signal into a base band signal. And I signal obtained by quadrature detection of the IF band signal while optimizing the input signal level using any of the methods of controlling the AGC amplifier so that this is equal to the reference value. Viterbi decoding or trellis decoding of the Q signal,
In many cases, program information included in a received signal is reproduced.

[0004]

However, in a digital broadcasting system using such a digitally modulated wave, the coding rate for error correction in one frame,
In digital broadcasting systems that transmit program information by dynamically switching the modulation method, etc., the optimum input signal level differs depending on the coding rate and modulation method, so that the input signal level during one frame period is kept constant. However, when each coding rate and each modulation scheme are switched, the performance of Viterbi decoding or trellis decoding is not sufficiently utilized, and there is a possibility that the program information included in the received signal may not be accurately reproduced. there were.

In view of the above circumstances, the present invention optimizes the amplitude or power of an input signal for each modulation scheme and accurately reproduces information modulated by a plurality of coding rates and a plurality of modulation schemes. It is an object of the present invention to provide a receiving device capable of performing the above.

[0006]

In order to achieve the above object, according to the present invention, in one aspect, encoding is performed by a plurality of transmission schemes comprising a combination of an error correction encoding scheme and a modulation scheme during one frame period. A receiving apparatus that receives a modulated wave including a modulated signal and reproduces a signal for each transmission method included in the modulated wave when reproducing each signal included in the modulated wave; A BER measurement circuit for measuring a bit error rate for each signal transmission method, and a power or amplitude of the modulated wave for each transmission method based on the bit error rate for each transmission method output from the BER measurement circuit. And a variable gain control circuit that adjusts

According to the above arrangement, a modulated wave including a signal modulated by a plurality of transmission systems is received during one frame period, and a signal for each transmission system included in the modulated wave is reproduced. In this case, the bit error rate is measured for each transmission method of each signal, and based on the measurement result, the power or amplitude of the modulated wave is adjusted for each transmission method. The power is optimized to accurately reproduce information modulated by a plurality of coding rates and a plurality of transmission schemes.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <Description of Digital Broadcasting System>
First, prior to the detailed description of the receiving device according to the present invention,
The frame structure of multiplexed data, the structure of a modulated wave, the structure of a transmitting device, and the like used in a digital broadcasting system will be briefly described.

<Frame Structure of Multiplexed Data> First, in the present invention, a frame synchronization W1 indicating the beginning of a frame in one frame period, a TMCC signal (transmission multiplexing configuration control signal) including information on a transmission method of a main signal, and the like. , A superframe synchronization W2 (or a superframe synchronization W3) indicating the first frame in a superframe, and a transmission method including a combination of a plurality of error correction coding methods and modulation methods in response to a request from a broadcaster. In a digital transmission system that performs transmission using a modulated wave composed of a main signal obtained by time-division multiplexing a modulated signal, the gain of the AGC amplifier is set for each transmission system so that the bit error rate of each transmission system is minimized. Control.

For example, in a digital transmission system for satellite digital broadcasting using BS satellites (broadcasting satellites), the transmitting device side displays video and audio signals in a format conforming to the MPEG2 standard as shown in FIG. And a TS consisting of 188 bytes in which each digital data is multiplexed
A (transport stream) packet is generated.

At this time, the Reed-Solomon code [RS (204, 188)] is stored in the 16 bytes following each TS packet.
Are added to form one slot, and 48 slots are combined to form one frame. Also, the first byte of each TS packet is originally a 1-byte packet synchronization code (47 in hexadecimal).
However, in the present invention, at the time when a frame is formed, the frame synchronization signal W1 is set to 2 at this point.
Byte (16 bits), 8 bytes (64 bits) as a control signal called a TMCC signal, superframe synchronization signal W2 (or superframe synchronization signal W3)
It is assumed that a total of 12 bytes (96 bits) of 2 bytes (16 bits) is overwritten.

Here, for example, even when only one packet in one frame is transmitted by a certain transmission method,
In order to perform interleaving of a sufficient depth (depth of 8 or more) necessary to bring out the capability of the error correction code, a superframe is configured with eight frames as one unit. Interleaving is performed by grouping eight slots at a position. At this time, since it is necessary to identify the top frame position in the superframe, if the superframe synchronization is the superframe synchronization W2, it is determined to be the top frame in the superframe. If the superframe synchronization is W3, the superframe synchronization is determined. By determining that the frame is another frame, the position of each super frame is identified.

In each slot position, a transmission system desired by the carrier occupying the slot is specified. For example, as shown in FIG. 8, designation is made such that the first eight slots are transmitted by the first transmission method and the second half 40 slots are transmitted by the second transmission method.

[0014] Further, information on the correspondence between each slot position and the transmission method is described in the TMCC signal. In the example shown in FIG. 8, the frame structure after one superframe is indicated by the contents described in the TMCC signal.
The contents of the TMCC signal are changed two superframes before the switching time.

<Modulated Wave Structure> Based on the multiplexed data having the above-described frame structure, the transmitting apparatus generates a modulated wave having the structure shown in FIG.

As shown in FIG. 1, in this modulated wave, a frame synchronization W1 composed of 32 symbols, a TMCC signal composed of 128 symbols, and a super A total of 192 symbols with the frame synchronization W2 (or superframe synchronization W3) are modulated and multiplexed by a two-phase shift keying (BPSK) modulation method.

Here, the number of these symbols is twice the number of bits of the portion corresponding to the frame synchronization W1, the TMCC signal, and the superframe synchronization W2 (or the superframe synchronization W3) in the multiplexed data shown in FIG. The reason for this is that, for these, convolutional coding is performed at a coding rate of 、, and the data amount is increased by the same number of redundant bits as the original data amount. .

Following these header portions, eight slots serving as main signals are modulated by the first transmission system, and 40 slots are modulated by the second transmission system and multiplexed.

In this main signal section, a random BPSK modulation wave (phase reference burst symbol) composed of 4 symbols is inserted for every 203 symbols used for transmission of the main signal, and a low C / N ratio is obtained. Up to career regeneration is possible.

Further, on the receiving device side, after capturing the frame synchronization, demodulation and decoding of the TMCC signal portion are performed, and after extracting information on the transmission system of the subsequent main signal portion, demodulation and decoding of the main signal are started. , Even if you change the transmission method,
The transmission method of each slot can be dynamically switched in units of a superframe.

<Structure of Transmitter> Next, referring to a block diagram shown in FIG. 10, multiplexed data having the above-described frame structure is converted into a modulated wave having the above-described structure.
The structure of the transmitting device for transmitting to each receiving device will be described. In the following description, for 36 packets,
Transmission using TC8PSK, and for 7 packets, a transmission system combining error correction coding by a convolutional code with a coding rate of 7/8 and a quadrature phase shift keying (QPSK) modulation system (hereinafter, this transmission system) QPS
K (referred to as r = 7/8)) and 3
For the packet, a transmission method combining error correction coding by a convolutional code with a coding rate of 3/4 and a QPSK modulation method (hereinafter, this transmission method is referred to as QPSK (r = 3 /
4)).

A transmitting apparatus 101 shown in FIG. 1 includes an energy spreading circuit 102, an interleaving circuit 103,
(64, 48) encoding circuit 104, energy spreading circuit 105, switch 106, trellis / convolutional encoding circuit 107, puncturing circuit 108, BP
SK phase reference burst circuit 109, BPSK / QPS
K / 8PSK mapper circuit 110 and quadrature modulation circuit 111
And a multiplexing device (not shown) modulates a signal in which one frame in which a plurality of video signals, audio signals, and data services are multiplexed has 48 slots,
A modulated wave having the above-described structure is generated and transmitted to each receiving device.

Here, if all data is transmitted by TC8PSK having the highest frequency use efficiency among transmission systems assumed in the present system, data for 48 slots is transmitted in one frame period. However, when transmitted by QPSK (r = 7/8) as in this example, the efficiency is 7/8 of TC8PSK, and when transmitted by QPSK (r = 3/4), the efficiency is Is T
Since it is 3/4 of C8PSK, data that cannot be transmitted in one frame occurs.

Therefore, in this example, QPSK (r = 7 /
8), one slot is inserted as a packet (dummy packet) that is not actually transmitted in the seven slots transmitted in one slot, and one slot is inserted in three packets transmitted in QPSK (r = 3/4). By inserting dummy slots, the number of slots per frame is kept constant even if the modulation scheme is different.

Data randomization is performed by the energy spreading circuit 102 on the portion 112 and the portion 113 obtained by removing the leading byte of each slot from this signal.
The interleave circuit 103 performs block byte interleaving with a depth of eight. Next, trellis coding (r = ２) is performed on the data portion transmitted by TC8PSK by trellis / convolution coding circuit 107, and QPSK (r = 7/8) and QPSK (r =
3/4), the convolutional coding (r
= 1/2) is performed. Note that these encoding processes are
It is performed by the same circuit.

In addition, QPSK (r = 7/8) and QP
For the part transmitted by SK (r = 3/4), the puncturing circuit 108 sets the coding rate to 7
/ 8 and 3/4, and data thinning is performed so that the head of each packet is the starting point of thinning.

On the other hand, regarding the TMCC signal portion, RS
After the error correction code is added by the (64, 48) circuit 104 and the data is randomized by the energy spreading circuit 105, the trellis / convolutional coding circuit 1
07 performs convolutional coding (r = 1/2).

The read-only memory (RO) constituting the BPSK / QPSK / 8PSK mapper circuit 110
M), the frame synchronization W1, the TMCC signal, and the frame synchronization W2 are mapped on the BPSK mapper shown in FIG. 11C, and the portion transmitted by TC8PSK is shown in FIG. (A) is mapped on the 8PSK mapper, and the QPSK (r = 7/8) part and the QPSK (r = 3 /
4) is mapped onto the QPSK mapper shown in FIG. 11B, and each mapping result is converted into an I signal and a Q signal (each 8 bits).

As a result, for example, if the signal of the portion transmitted by TC8PSK is "010", it is mapped on the 8PSK mapper shown in FIG.
, And a Q signal indicating "+90".

Next, the BPSK / QPSK / 8PS
The output of the K mapper circuit 110 is quadrature-modulated by the quadrature modulation circuit 111 to generate a modulated wave shown in FIG.
This is transmitted to each receiving device.

<< Description of Embodiment >> Next, a receiving apparatus for demodulating and decoding a modulated wave transmitted from the above-described transmitting apparatus to reproduce the contents of a program will be described with reference to the drawings.

FIG. 1 is a block diagram showing an example of a receiving apparatus to which an embodiment of the receiving apparatus according to the present invention is applied.

The receiving apparatus 1 shown in FIG. 1 includes a BS antenna 2, a variable gain amplifying circuit 3, a channel selection frequency converting circuit 4, a quadrature detecting circuit 5, a depuncturing circuit 6,
A trellis / Viterbi decoding circuit 7, a BER measuring circuit 8,
Gain control circuit 9, switch 10, energy despreading circuit 11, RS (64, 48) decoding circuit 12, gate signal generating circuit 13, deinterleave circuit 14, energy despreading circuit 15, RS ( 204, 188) a decoding circuit 16, a desired TS separation circuit 17, an MP @ HL decoding circuit 18, and an HDTV 19, and the data to be transmitted has a frame structure. When receiving and demodulating the modulated wave transmitted from the transmitting device of the digital transmission system that switches and transmits the modulated signal, the bit error rate of each modulation method is measured or estimated and demodulated for each transmission method. The signal level is optimized so that the performance when performing Viterbi decoding or trellis decoding is not degraded, and the modulated wave is demodulated and decoded and transmitted from the transmitting device. The contents of the the program HDTV19
To play.

In this case, the BS antenna 2 receives a 12 GHz band broadcast wave (modulated wave) relayed by a broadcasting satellite and generates a reception signal, and a reception signal obtained by the reception operation of the antenna. (Outdoor unit) that converts the frequency of the received signal, receives the broadcast wave of the 12 GHz band relayed by the broadcast satellite, converts the frequency of the received signal obtained by this reception operation, and converts the frequency of the received signal to the 1 GHz band. One intermediate frequency signal is generated and supplied to the variable gain amplifier circuit 3.

The variable gain amplifier 3 has an amplification factor corresponding to the control signal input to the control terminal.
A variable gain amplifier for amplifying the first intermediate frequency signal output from the S antenna 2, and having an amplification factor corresponding to the control signal input to the control terminal, After amplifying the intermediate frequency signal to a specified power or amplitude, the signal is supplied to the channel selection frequency conversion circuit 4.

The channel selection frequency conversion circuit 4 adjusts the local oscillation frequency according to the contents of the channel specification, converts the frequency of the first intermediate frequency signal output from the variable gain amplifier circuit 3, and adjusts the frequency of the specified channel. To generate a second intermediate frequency signal of 479.5 MHz, which is supplied to the quadrature detection circuit 5.

The quadrature detection circuit 5 synchronously detects the second intermediate frequency signal output from the channel selection frequency conversion circuit 4 and, based on the synchronous detection result, an I signal on a complex plane,
A Q signal is generated, and the Q signal is
It is supplied to the measurement circuit 8.

The depuncturing circuit 6 converts the I signal and the Q signal output from the quadrature detection circuit 5 into frame synchronizations W1 and TM.
CC signal, frame synchronization W2 (or frame synchronization W2)
When the I signal and the Q signal correspond to the portion 3), the I signal and the Q signal are passed through as they are, supplied to the trellis / Viterbi decoding circuit 7, and output from the quadrature detection circuit 5, When the Q signal is an I signal or a Q signal corresponding to the main signal, the I signal and the Q signal are subjected to depuncture processing, and the obtained I signal and the Q signal are supplied to the trellis / Viterbi decoding circuit 7. I do.

The trellis / Viterbi decoding circuit 7 includes a Viterbi decoder 22 shown in FIG. 6 and a trellis decoder 20 shown in FIG.
And a Viterbi decoder 21 shown in FIG.

In the trellis / Viterbi decoding circuit 7, based on the gate signal output from the gate signal generation circuit 13, the I signal and the Q signal output from the depuncturing circuit 6 are converted into a frame synchronization W 1, a TMCC signal, and a frame synchronization W 2
(Or frame synchronization W3), these are Viterbi decoded by the Viterbi decoder 22. The decoded data obtained by the Viterbi decoder 22 is supplied to the BER measuring circuit 8 and also to the energy despreading circuit 11 via the switch 10. When the I signal and the Q signal output from the depuncturing circuit 6 are main signals, the trellis decoder 20 outputs the TC8P signal of the main signal.
The SK part is trellis decoded. The decoded data obtained by the trellis decoder 20 is supplied to the BER measurement circuit 8 and is also supplied to the deinterleave circuit 14 via the switch 10. Further, the QPSK (r = 7/8) portion of the main signal is Viterbi decoded (r = 7/8) by the Viterbi decoder 21, and the QPSK (r = 3/4) portion is Viterbi decoded (r = 3/4). The decoded data thus obtained is supplied to the BER measuring circuit 8 and also supplied to the deinterleave circuit 14 via the switch 10.

The energy despreading circuit 11 includes a switch 10
Frame synchronization W1, TMCC signal supplied via
The decoded data of the frame synchronization W2 (or frame synchronization W3) is subjected to energy despreading in the reverse procedure to the randomization performed by the transmitting device, and the signal obtained by this is RS (64, 48) decoded. Supply to circuit 12.

The RS (64, 48) decoding circuit 12 converts the signal output from the energy despreading circuit 11 into an RS (64, 48) signal.
48) Decode and reproduce the frame synchronization W1, the TMCC signal, and the frame synchronization W2 (or the frame synchronization W3), and supply them to the gate signal generation circuit 13.

The gate signal generation circuit 13 outputs RS (64,
48) The frame synchronization W1 output from the decoding circuit 12,
Based on the frame synchronization W2 (or the frame synchronization W3), the carrier is reproduced, the contents of the TMCC signal are identified, and a gate signal necessary for controlling each unit of the receiving device 1 is generated. 1 to each part,
These control the operation.

Further, the deinterleave circuit 14 takes in the decoded data of the main signal portion supplied via the switch 10 and performs a depth 8 book byte deinterleave on the decoded data. The signal is supplied to the energy despreading circuit 15.

The energy despreading circuit 15 fetches the signal output from the deinterleave circuit 14 and performs energy despreading in the same procedure as when the transmitter randomizes the signal. (20
4, 188) to the decoding circuit 16.

The RS (204, 188) decoding circuit 16
The signals output from the energy despreading circuit 15 are fetched, and 47
(Hexadecimal number) is complemented, RS (204, 188) decoding is performed, and the signal (multiplexed signal) obtained by this is supplied to the desired TS separation circuit 17.

The desired TS separation circuit 17 outputs the RS (204,
188) The multiplexed signal output from the decoding circuit 16 is taken in, and based on the correspondence between the slot position notified from the transmitter to the receiver by the TMCC signal and the TS identifier, the broadcaster desired by the viewer. Is extracted, separated from other TSs, and supplied to the MP @ HL decoding circuit 18.

The MP @ HL decoding circuit 18 decodes information of the MPEG2 standard included in the time slot output from the desired TS separation circuit 17 to reproduce a video signal, an audio signal, a service, etc. To display the contents of the program.

Further, the BER measuring circuit 8 uses TC8PSK
Measurement circuit 23 for TC8PSK measuring BER
(See FIG. 2) and QPSK for measuring the BER of QPSK
BER measurement circuit 24 (see FIG. 4) and BE of BPSK
And a BER measuring circuit 25 for BPSK (see FIG. 6) for measuring R. The BE for TC8PSK is provided for each modulation method of the modulated wave received by the BS antenna 2.
R measurement circuit 23, BER measurement circuit 24 for QPSK, BP
By operating the SK BER measurement circuit 25, the BER of the I signal and the Q signal output from the quadrature detection circuit 5 is measured, and the measurement result is supplied to the gain control circuit 9.

In this case, the BER measuring circuit 23 for TC8PSK, as shown in FIG.
When the I signal and the Q signal of the PSK portion are output, the I signal and the Q signal are fetched, and the I signal and the Q signal are obtained by using each area of the hard decision table 26 shown in FIG. TC8PSK hard decision of signal is performed and "000" ~
A TC8PSK hard-decision decoder 27 that generates 3-bit decoded data of any of “111” is provided. Also, the I signal, Q
When the signal is output and the decoded data of 2 bits per symbol period is output from the trellis decoder 20 of the trellis / Viterbi decoding circuit 7, the decoded data is the same as the trellis encoding performed on the transmission device side. There is provided a trellis encoder 28 which performs trellis encoding to generate 3-bit encoded data to which redundant bits for error correction are added. Further, the encoded data output from the trellis encoder 28 and the TC8PSK hard decision decoder 27
And a counter 30 that counts the comparison result output from the bit comparator 29 to obtain an approximate value of the transmission error rate of 8PSK before trellis decoding. Have.

In the TC8PSK BER measuring circuit 23, the I signal, Q
When a signal is output, for these I signal and Q signal,
The TC8PSK hard decision is made to generate 3-bit decoded data of any of "000" to "111", and the trellis decoder 20 of the trellis / Viterbi decoding circuit 7
Performs trellis coding processing on the decoded data output from to generate 3-bit coded data, further compares these decoded data with coded data by bit, counts the comparison result, and The obtained approximate value of the transmission error rate of 8PSK before trellis decoding is supplied to the gain control circuit 9.

At this time, while the decoded data side output from the 8PSK hard decision decoder 27 is not corrected at all, the code data side output from the trellis encoder 28 is trellis-decoded by the trellis decoder 20. When the C / N is performed, the data becomes almost error-free with a normal C / N.
When the error rate is reduced and the trellis encoder 28 further performs trellis encoding processing,
Since the error rate becomes almost zero, the decoded data and the coded data are compared with each other, and when the comparison result is counted, an approximate value of the transmission error rate of 8PSK before trellis decoding is obtained. It is supplied to the control circuit 9.

The BER measuring circuit for QPSK 24
As shown in FIG. 4, when the quadrature detection circuit 5 outputs the I signal and the Q signal of the QPSK portion, the I signal and the Q signal are fetched and separated by the dotted line of the hard decision table 31 shown in FIG. A QPSK hard-decision decoder 32 that performs QPSK hard-decision of the I signal and the Q signal using each area to generate 2-bit decoded data of any of “00” to “11”. In addition, the quadrature detection circuit 5 outputs Q
When the I signal and the Q signal of the PSK portion are output and the decoded data is output from the Viterbi decoder 21 of the trellis / Viterbi decoding circuit 7, the decoded data is the same as the convolutional coding performed on the transmission device side. A convolutional encoder 33 that performs convolutional encoding to generate 2-bit encoded data to which redundant bits for error correction are added. Further, a puncturing device 34 that performs the same puncturing process as the puncturing process performed on the transmission device side on the encoded data output from the convolutional encoder 33, and an output from the puncturing device 34 A bit comparator 35 that compares the encoded data with the decoded data output from the QPSK hard-decision decoder 32, and counts the comparison result output from the bit comparator 35 to count the QPSK transmission error before Viterbi decoding. And a counter 36 for obtaining an approximate value of the rate.

Then, the BER measuring circuit 2 for QPSK
4, the quadrature detection circuit 5 outputs the I signal, Q
When a signal is output, the I signal and the Q signal are fetched, and QPSK hard decision is performed on the I signal and the Q signal to generate 2-bit decoded data that is any one of "00" to "11". At the same time, convolutional coding processing and puncturing processing are performed on the decoded data output from the Viterbi decoder 21 of the trellis / Viterbi decoding circuit 7 to generate 2-bit coded data. Is compared with the coded data, the comparison result is counted, and the obtained approximate value of the transmission error rate of QPSK before Viterbi decoding is supplied to the gain control circuit 9.

At this time, while the decoded data output from the QPSK hard decision decoder 32 is not error-corrected at all, the encoded data output from the puncturing device 34 is subjected to Viterbi decoding by the Viterbi decoder 21. At the point of time, the data becomes almost error-free with the normal C / N, and even when the C / N deteriorates, the data becomes the data with a reduced error rate to some extent. Since the error rate becomes almost zero at the time of the processing, the decoded data and the coded data are compared with each other, and when the comparison result is counted, the QPSK transmission error rate before Viterbi decoding is approximated. The value is obtained and supplied to the gain control circuit 9.

Also, the BER measurement circuit 25 for BPSK
As shown in FIG. 6, when the I signal and the Q signal of the BPSK portion are output from the quadrature detection circuit 5, the I signal and the Q signal are fetched and separated by a dotted line of the hard decision table 37 shown in FIG. A BPSK hard-decision decoder 38 is provided that performs BPSK hard-decision of the I signal and the Q signal using each area and generates 1-bit decoded data of either “0” or “1”. In addition, the BPS
When the I signal and the Q signal of the K portion are output and the decoded data is output from the Viterbi decoder 22 of the trellis / Viterbi decoding circuit 7, the decoded data is the same as the convolutional coding performed on the transmission device side. A convolutional encoder 39 is provided for performing convolutional encoding to generate 2-bit encoded data to which redundant bits for error correction have been added. Further, a puncturing device 40 that performs the same puncturing process as the puncturing process performed on the transmission device side with respect to the encoded data output from the convolutional encoder 39, and an output from the puncturing device 40. P to generate P / S conversion (parallel / serial conversion) of encoded data to generate encoded data in a serial signal format
/ S converter 41 and a bit comparator 42 that performs a bit comparison between encoded data output from P / S converter 41 and decoded data output from BPSK hard decision decoder 38.
And a counter 43 for counting the comparison result output from the bit comparator 42 and obtaining an approximate value of the BPSK transmission error rate before Viterbi decoding.

The BER measurement circuit 2 for BPSK
5, the quadrature detection circuit 5 outputs the I signal of the BPSK portion,
When a signal is output, the I signal and the Q signal are taken in, and a BPSK hard decision is performed on the I signal and the Q signal to generate 1-bit decoded data that becomes either "0" or "1". At the same time, convolutional encoding processing, puncturing processing, and the like are performed on the decoded data output from the Viterbi decoder 22 of the trellis / Viterbi decoding circuit 7.
P / S conversion processing is performed to generate encoded data in a serial signal format, the decoded data is compared with the encoded data by bits, and the comparison result is counted. Is supplied to the gain control circuit 9.

At this time, while the decoded data output from the BPSK hard decision decoder 38 is not corrected at all, the encoded data output from the P / S converter 41 is Viterbi decoded by the Viterbi decoder 22. At the time of processing, the data is almost error-free with normal C / N.
Further, even when the C / N is deteriorated, the error rate is reduced to some extent, and the error rate becomes almost zero when the convolutional encoding process is performed by the convolutional encoder 39. When the data and the encoded data are compared with each other and the result of the comparison is counted, an approximate value of the BPSK transmission error rate before Viterbi decoding is obtained, and this is supplied to the gain control circuit 9.

The gain control circuit 9 sets the current gain A corresponding to the transmission method of the received signal amplified by the variable gain amplifier circuit 3 to gains A + δ, A−
δ and these gains A + δ and A
A control signal having a value corresponding to −δ is generated and sequentially supplied to the control terminal of the variable gain amplifier circuit 3. When the approximate value BER (+) of the transmission error rate output from the BER measurement circuit 8 when the gain (amplification factor) of the variable gain amplifier circuit 3 is A + δ and the gain of the variable gain amplifier circuit 3 is A−δ Of B
Approximate value BE of transmission error rate output from ER measurement circuit 8
R (-) and each approximate value BER (+), BE
A gain adjuster that compares R (−) and adjusts the value of the gain A for each modulation scheme for each transmission scheme based on the comparison result.

Then, for each modulation method of the received signal amplified by the variable gain amplifier circuit 3, the gain A up to the previous time for each modulation method is switched to gains A + δ and A-δ, and the variable gain amplifier circuit 3 When the gain is switched to A + δ, the approximate value BER (+) of the transmission error rate output from the BER measurement circuit 8 and when the gain of the variable gain amplifier circuit 3 is switched to A−δ, the BER measurement circuit 8
And the approximate values BER (−) of the transmission error rates output from the BERs, and these approximate values BER (+) and BER (−)
If “BER (+)> BER (+)”, the control is repeated to reduce the gain A for this modulation scheme, otherwise to increase the gain A for this modulation scheme, and the variable gain amplification is repeated. The gain A of the circuit 3 is optimized for each modulation scheme, and the approximate value of the transmission error rate for each modulation scheme output from the BER measurement circuit 8 is minimized.

As described above, in this embodiment, the data to be transmitted has a frame structure, and in one frame period,
When receiving and demodulating a modulated wave transmitted from a transmitting device of a digital transmission system that switches and transmits a plurality of modulation methods and relayed by a broadcasting satellite, the bit error rate of each transmission method is measured or estimated, and transmission is performed. While optimizing the demodulated signal level for each system so that the performance when performing Viterbi decoding or trellis decoding is not deteriorated, the modulated wave is demodulated and decoded, and the content of the program transmitted from the transmitting device is converted to HDTV.
19 for playback. Therefore, a frame synchronization W1 indicating the head of a frame in one frame period, a TMCC signal including information on a transmission method of a main signal, and a superframe synchronization W2 (or a superframe synchronization W3) indicating a head frame in a superframe.
When receiving a modulated wave consisting of a main signal modulated by a plurality of transmission schemes according to the program contents and the broadcaster's request and reproducing these signals, the reception signal of each transmission scheme is Optimize power or amplitude to get the respective coding rate,
The amount of deterioration in the modulation scheme can be minimized.

[0062]

As described above, according to the present invention, the amplitude or power of an input signal is optimized for each transmission system, and information modulated by a plurality of coding rates and a plurality of transmission systems is obtained. Can be reproduced accurately.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a receiving device to which the present invention has been applied.

FIG. 2 shows TC8P constituting the BER measurement circuit shown in FIG.
It is a block diagram which shows an example of the BER measurement circuit for SK.

FIG. 3 is an explanatory diagram showing an example of a hard decision table used in the 8PSK hard decision decoder shown in FIG. 2;

FIG. 4 is a diagram showing QPSK constituting the BER measurement circuit shown in FIG. 1;
FIG. 3 is a block diagram showing an example of a BER measurement circuit for use.

5 is an explanatory diagram showing an example of a hard decision table used in the hard decision decoder for QPSK shown in FIG. 4;

FIG. 6 shows BPSK constituting the BER measurement circuit shown in FIG. 1;
FIG. 3 is a block diagram showing an example of a BER measurement circuit for use.

FIG. 7 is an explanatory diagram showing an example of a hard decision table used in the BPSK hard decision decoder shown in FIG. 6;

FIG. 8 is an explanatory diagram illustrating an example of a frame created on the transmitting device side of a satellite digital broadcasting system using a broadcasting satellite.

FIG. 9 is an explanatory diagram showing an example of a modulated wave created on the transmitting device side of a satellite digital broadcasting system using a broadcasting satellite.

FIG. 10 is a block diagram showing a detailed configuration of a transmission device used in a satellite digital broadcasting system using a broadcasting satellite.

FIG. 11 shows BPSK / QPSK / 8PSK shown in FIG.
FIG. 4 is an explanatory diagram illustrating an example of an 8PSK mapper, a QPSK mapper, and a BPSK mapper used in a mapper circuit.

[Explanation of symbols]

 1: Receiving apparatus 2: BS antenna 3: Variable gain amplifier circuit 4: Channel selection frequency conversion circuit 5: Quadrature detection circuit 6: Depuncture circuit 7: Trellis / Viterbi decoding circuit 8: BER measurement circuit 9: Gain control circuit 10: Switch 11: Energy despreading circuit 12: RS (64, 48) decoding circuit 13: Gate signal generation circuit 14: Deinterleave circuit 15: Energy despreading circuit 16: RS (204, 188) decoding circuit 17: Desired TS separation circuit 18 : MP @ HL decoding circuit 19: HDTV 20: Trellis decoder 21, 22: Viterbi decoder 23: BER measurement circuit for TC8PSK 24: BER measurement circuit for QPSK 25: BER measurement circuit for BPSK 26, 31, 37: Hard decision Table 27: TC8PSK hard decision decoder 28: Trellis encoder 29, 35: Bit comparators 30, 36, 43: counter 32: QPSK hard decision decoder 33, 39: convolutional encoder 34, 40: puncturing device 38: BPSK hard decision decoder 41: P / S converter 42: bit Comparator

Claims (1)

[Claims] 1. A modulation wave including a signal coded and modulated by a plurality of transmission systems including a combination of an error correction coding system and a modulation system during one frame period, and received in the modulation wave. A BER measurement circuit for measuring a bit error rate for each transmission method of each signal when reproducing each signal included in the modulated wave; A variable gain control circuit that adjusts the power or amplitude of the modulated wave for each transmission scheme based on the bit error rate for each transmission scheme output from the measurement circuit.