JPH09214479A - Frame synchronization method and transmitter and receiver adopting the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the synchronization performance and to transmit plural kinds of frames including frames without synchronizing bytes. SOLUTION: A transport stream is given to a scramble circuit 2, a reed Solomon coding circuit 5, an interleave circuit 6, in which scramble processing, read Solomon coding processing and interleave processing are conducted and the result is given to a code insert circuit 31. The code insert circuit 31 inserts an inverted FAW to a head frame of a scramble frame and a FAW is inserted to a head of the other frame. An output of the code insert circuit 31 is modulated and outputted. As a frame synchronizing code, the FAW, a SYNC, the inverted FAW and inverted SYNC are used. The frame synchronizing code has high autocorrelation than the SYNC and the inverted SYNC, the synchronization performance at a receiver side is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization method suitable for transmitting an MPEG2 transport stream, and a transmitter and a receiver using the same.

[0002]

2. Description of the Related Art In recent years, digital processing of images has become popular with the establishment of high-efficiency image coding technology. The high-efficiency encoding technique encodes image data at a low bit rate in order to improve the efficiency of digital transmission and recording. High efficiency coding standard MPEG
(Moving Picture Experts Group) 1 (ISO / IEC
11172) has already been used in video CDs, CD-I's and the like. In addition, the standardization of MPEG2, which is a standard corresponding to the image quality comparable to that of current broadcasting, has been completed. Digital broadcasting using high-efficiency coding based on these standards has also been studied.

For example, in Europe, DVB (Digital Video Broadcasting) adopting high efficiency coding is being studied. DVB supports not only the current broadcasting system, but also various broadcasting systems using high-definition television broadcasting satellites, terrestrial waves and cable systems, and experimental broadcasting is scheduled to start from around the end of 1995.

The transmission frame in DVB is MPEG
It uses 2 Transport Streams. The transport stream considers transmission of a plurality of programs in one stream, and a plurality of reference times can be used for each program. The transport stream is composed of 188-byte fixed-length packets (transport packets) containing a 1-byte synchronization signal (hereinafter referred to as SYNC). In DVB, SYNC of MPEG2 is used as it is as a synchronization byte of a transmission frame.

FIG. 21 is a block diagram showing a conventional transmitter adopted in such a DVB, and FIG. 22 is a flowchart showing its operation. Further, FIG. 23 is an explanatory diagram showing a transmission frame obtained by the conventional transmitter of FIG. 21, which is disclosed in “PR est 300 421”.

MPEG2 input through the input terminal 1
The transport stream of is input to the scramble circuit 2. The scramble circuit 2 has a scramble processing circuit 3. The scramble processing circuit 3 scrambles the transport stream in step S1 of FIG. That is, the scramble processing circuit 3
Performs an exclusive OR operation of the input transport stream and the pseudo random number. Thereby, the peak value of the transmission spectrum can be suppressed and the transmission power can be made constant.
Note that no calculation is performed on the leading 1-byte sync byte of each packet.

In DVB, scrambling processing is performed in units of 8 frames created from 8 transport packets. In order to grasp the head position of the scramble frame in units of 8 frames, the sync byte at the head of each scramble frame is inverted by the SYNC inversion circuit 4. SY
NC inversion circuit 4 inverts SYNC every 8 packets
Output SYNC. For example, "4" in hexadecimal as SYNC
When "7" is adopted, inverted SYNC is hexadecimal "B"
8 ". In addition, in the figure below, inverted SYNC is SY
A bar is attached on the NC.

The output of the scramble circuit 2 is applied to the Reed-Solomon encoder 5 and is Reed-Solomon encoded (step S2). The Reed-Solomon encoder 5 has 1
An error correction code of 2t bytes (t indicates a correction capability, and DV = t = 8 in DVB) is added to each transport packet (188 bytes). In this way, as shown in FIG. 23, a transmission frame structure composed of (188 + 2t) bytes is obtained. The output of the Reed-Solomon encoder 5 is given to the interleave circuit 6.

The interleaving circuit 6 performs convolutional interleaving processing on the input data in step S3. That is, the interleave circuit 6
When a continuous burst error occurs during transmission, the data is rearranged so that the error is converted into a plurality of discontinuous random errors on the receiving side. Note that the synchronization bytes have not been rearranged, and as shown in FIG.
The transmission frame structure of has not changed.

Next, in step S4, the output of the interleave circuit 6 is supplied to the inner encoder 7 to which an error correction code is added and then supplied to the mapping and modulation circuit 8. The output of the inner encoder 7 is, for example, QAM-modulated. The mapping and modulation circuit 8 maps the input data on the I (in-phase) axis and Q (quadrature) axis planes,
The mapped data is modulated into a transmission signal and output.
The output of the inner encoder 7 does not have the transmission frame structure shown in FIG. 23, and the output of the mapping and modulation circuit 8 does not have the transmission frame structure either. There is also a transmission method in which the inner coding by the inner encoder 7 is omitted.

On the other hand, on the receiving side, the original data is restored by the reverse processing of the transmitting device. FIG. 24 is a block diagram showing a conventional receiving device. Further, FIG. 25 is a flow chart for explaining the operation.

A received signal is input to the input terminal 11. This received signal is output from the transmitter of FIG. 21 as a transmitted signal to a transmission line (not shown). First, in step S5 of FIG. 25, the received signal is given to the demodulation and demapping circuit 12, demodulated, and then demapped to be returned to the original data. When inner coding is performed on the transmitting side, the output of the demodulation and demapping circuit 12 is given to the inner decoder 13 and is inner decoded.

Next, the synchronizing circuit 14 carries out synchronization pull-in in step S6. That is, the output of the inner decoder 13 is applied to the sync byte detection circuit 15 to detect the sync byte.
On the transmission side, scrambling processing, Reed-Solomon encoding processing, and interleaving processing are performed with the synchronization byte as a reference. By performing synchronization pulling, these processings can be reversed. That is, SYNC and inversion
Frame synchronization is established by detecting SYNC, and scramble synchronization is established by detecting inverted SYNC.

The deinterleave circuit 16 operates in step S7.
, The output of the synchronization circuit 14 is deinterleaved to restore the original data array and the Reed-Solomon decoder
Output to 17. The Reed-Solomon decoder 17 has a redundant bit (parity) added to the last 2t bytes of each packet.
Is used to correct the error, delete the 2t bytes, and output the descramble circuit 18 (step S8).

In the next step S9, the descrambling circuit 18 is descrambled by the descramble processing circuit 19. That is, the descramble processing circuit
19 performs an exclusive OR operation of the input data and the pseudo random number. In this case, no calculation is performed on the sync byte. Furthermore, the descramble circuit 18 is an inverting circuit.
By 20, the inverted SYNC is inverted to return to the original SYNC. In this way, a decoded output obtained by restoring the transport stream on the transmission side is obtained at the output terminal 21.

As described above, in the conventional receiver,
By performing the synchronization pull-in using SYNC and inversion SYNC, the subsequent processing is enabled. However, the sync pull-in by the sync byte is premised on error-free. In a transmission system having noise, there is a problem that a synchronization byte detection error may occur and the synchronization performance may be deteriorated.

Further, in order to perform the synchronization pull-in, it is necessary that the transmission data has SYNC arranged at the beginning of each frame. Therefore, there is a problem that it is not possible to time-division-multiplex and transmit a frame in which SYNC is not arranged at the head of the frame on the same channel.

[0018]

As described above, conventionally, in a transmission system having noise, there has been a problem that the synchronization performance is deteriorated. Further, there is also a problem that a frame in which no synchronization byte is arranged at the head of the frame cannot be time-division multiplexed and transmitted on the same channel.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a frame synchronization method capable of improving the synchronization performance, and a transmitter and a receiver using the same.

It is another object of the present invention to provide a frame synchronization method capable of coexisting a plurality of frame configurations including a transmission system in which a synchronization byte is not arranged at the head of a frame, and a transmitter and a receiver using the same. To do.

[0021]

According to a first aspect of the present invention, there is provided a frame synchronization method, wherein a second synchronization code is added frame by frame to a stream in which a first synchronization code is arranged for transmission. The frame synchronization method according to claim 2, wherein the receiving side performs the synchronization pull-in using the first and second synchronization codes or the synchronization pull-in using the second synchronization code. Transmits a second synchronization code and a predetermined control code added to each stream to a stream in which the first synchronization code is arranged for each frame, and the receiving side transmits the first and second synchronization codes and the above The synchronous pull-in is performed using a predetermined control code, the synchronous pull-in is performed using the second synchronous code, or the synchronous pull-in is performed using the second synchronous code and the predetermined control code, and Identify a given control code According to a third aspect of the present invention, there is provided a transport stream in which a first synchronization code is arranged for each packet, and the transport stream is subjected to predetermined signal processing to perform the packet processing. Signal processing means for outputting in frame units based on
Code inserting means for adding the second synchronizing code to the output of the signal processing means in the frame unit, or adding the second synchronizing code and the predetermined control code in the frame unit, and the output of the code inserting means. According to claim 4 of the present invention, the receiving device according to claim 4 of the present invention comprises data in which the first synchronization code and the second synchronization code are arranged. The received data based on the received data, the synchronous pull-in means for performing synchronous pull-in using the first and second synchronous codes, or the synchronous pull-in for using the second synchronous code, The deletion means deletes the synchronization code No. 2 and outputs it, and the decoding processing means for applying the reverse processing of the signal processing on the transmission side to the output of the deletion means to restore the transport stream. According to a sixth aspect of the present invention, the receiving device receives the received data based on the data in which the first synchronization code, the second synchronization code, and the predetermined control code are arranged in frame units, and receives the first and second Synchronization code and the predetermined control code are used for synchronization, the second synchronization code is used for the synchronization acquisition, or the second synchronization code and the predetermined control code are used for synchronization acquisition. A synchronization pull-in means, an identification means for identifying the predetermined control code, a deletion means for deleting and outputting the second synchronization code and the predetermined control code from the received data, and an output of the deletion means. And decoding processing means for performing reverse processing of signal processing on the transmitting side to restore the transport stream.

In claim 1 of the present invention, at the time of transmission, a second synchronization code is added to each frame in addition to the first synchronization code and transmitted. At the time of reception, synchronization pull-in is performed using at least the second synchronization code. Even if the first synchronization code is deteriorated by noise or the like, the synchronization can be pulled in by the second synchronization code.

In the second aspect of the present invention, a predetermined control code is added in addition to the first and second synchronization codes at the time of transmission. At the time of reception, synchronization performance is improved by performing synchronization pull-in using the first and second synchronization codes and a predetermined control code.

In the third aspect of the present invention, the signal processing means performs predetermined signal processing on the input transport stream and outputs it in frame units. The code insertion means is
The second synchronization code is added to the output of the signal processing means in frame units, or the second synchronization code and a predetermined control code are added. A first and a second sync code or a first sync code,
The output based on the data to which the second synchronization code and the predetermined control code are added in frame units is sent to the transmission line by the sending means.

In claim 4 of the present invention, the sync pull-in means receives the received data based on the data in which the first and second sync codes are arranged in frame units, and receives the first and second sync codes or The sync pull-in is performed using only the sync code of 2. The reception data subjected to the synchronization pull-in is given to the deleting means, and the second synchronization code is removed. The output of the deleting means is given to the decoding processing means to restore the original transport stream.

In claim 6 of the present invention, the synchronization pull-in means uses the first and second synchronization codes and the predetermined control code, only the second synchronization code or the second synchronization code and the predetermined control code. Perform synchronous pull-in. This improves the synchronization performance. The deleting unit deletes the second synchronization code and the predetermined control code from the received data. As a result, the original transport stream can be restored in the decoding processing means.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a transmitting apparatus according to the present invention. FIG.
In FIG. 21, the same components as those in FIG. 21 are designated by the same reference numerals. The present embodiment is applied to DVB using an MPEG2 transport stream.

MPEG2 input through the input terminal 1
The transport stream of is input to the scramble circuit 2. The scramble circuit 2 includes a scramble processing circuit 3 and a SYNC inverting circuit 4. The scramble processing circuit 3 performs an exclusive OR operation of the transport stream and the pseudo-random number in order to make the transmission power constant, and performs the scramble processing on the transport stream. Note that no calculation is performed on the leading 1-byte sync byte of each packet.
The scramble processing circuit 3 is adapted to use 8 transport packets as a scramble frame which is a scramble unit.

The SYNC inversion circuit 4 is given the data scrambled by the scramble processing circuit 3,
Inverted SYNC that is the inverted SYNC at the beginning of the scrambled frame
And output. The output of the SYNC inverting circuit 4 is supplied to the Reed-Solomon encoder 5.

The Reed-Solomon encoder 5 generates, for example, a 2t byte Reed-Solomon code from the input data string, adds it to a 188-byte transport packet, and outputs it. The output of the Reed-Solomon encoder 5 is given to the interleave circuit 6. The interleave circuit 6 rearranges the data so that the burst error can be converted into a random error on the receiving side.
The interleave circuit 6 does not rearrange the sync bytes.

In this embodiment, the output of the interleave circuit 6 is supplied to the code insertion circuit 31. The code insertion circuit 31 receives the input (188 + 2)
t) An nf-bit frame synchronization byte (hereinafter, referred to as FAW (Frame Alinement Word)) or an inverted FAW which is its inversion code is added to the head of the data in bytes. In the present embodiment, FAW and
The frame sync code is configured by SYNC or inverted FAW and inverted SYNC. The code insertion circuit
In the case of 31, the inverted FAW is added to the head of the head frame of each scramble frame, and the FAW is added to the head of other frames.
Is added.

The output of the code insertion circuit 31 is supplied to the inner encoder 7. The inner encoder 7 adds an error correction code to the input data and outputs it to the mapping and modulation circuit 8. The mapping and modulation circuit 8
The input data is mapped onto the I-axis and Q-axis planes, and then modulated into a transmission signal and output. A transmission method in which the inner encoder 7 is omitted may be considered.

Next, the operation of the transmitting apparatus configured as described above will be described with reference to FIGS. FIG. 2 is a flowchart for explaining the operation, and FIG. 3 is an explanatory diagram showing a frame structure. In the following figures, the inverted FAW is shown by adding a bar on the FAW.

The transport stream input via the input terminal 1 is applied to the scramble circuit 2.
The scramble circuit 2 scrambles the transport stream in step S1, and
Invert the SYNC at the beginning of the scrambled frame. In this way, a stream in which inverted SYNC is arranged at the head of the scramble frame and SYNC is arranged at the head of each of the other frames is obtained.

Next, the Reed-Solomon encoder 5 generates and adds the Reed-Solomon code frame by frame in step S2. Then, in step S3,
The interleave circuit 6 performs convolutional interleave processing to rearrange data.

In the present embodiment, the next step S
In 11, the code insertion circuit 31 has the interleave circuit 6
FAW or inverted FAW is added to the output of. That is, an nf-bit inverted FAW is added to the beginning of the scrambled frame, and an nf-bit FA is added to the beginning of each of the other frames.
W is added.

FIG. 3 shows the output of the code insertion circuit 31. As shown in FIG. 3, an inversion F is added at the beginning of each frame.
AW and inverted SYNC are arranged continuously or FAW
Frame sync code is formed by arranging SYNC continuously. The frame length of each frame is (188 + 2t) × 8
+ Nf bits. Improve synchronization performance by selecting FAW or FAW so that the autocorrelation of the frame sync code consisting of FAW and SYNC or the frame sync code consisting of inverted FAW and inverted SYNC is higher than SYNC or inverted SYNC. be able to. For example, hexadecimal display "CA" may be used as FAW. In addition, 'C
A47 'has the maximum autocorrelation in 2 bytes.

The output of the code insertion circuit 31 is given to the inner encoder 7, and the inner encoder 7 adds the inner code in step S4 and outputs it to the mapping and modulation circuit 8. The mapping and modulation circuit 8 maps the input data on the I-axis and Q-axis planes, modulates the mapped data into a transmission signal, and outputs the transmission signal.

As described above, in the present embodiment, FAW or inverted FAW is continuously arranged in SYNC or inverted SYNC as the frame synchronization code. If the bit length of the frame synchronization code is longer than that of the conventional one and an appropriate FAW is selected, autocorrelation becomes high, and sufficient synchronization performance can be obtained even in a transmission system having noise. In addition to SYNC included in the input transport stream,
Since FAW is added as a frame synchronization code, frame synchronization can be performed by FAW even when a stream that does not include SYNC is input. For this reason, it is possible to coexist a plurality of frame configurations that do not include SYNC.

FIG. 4 is a block diagram showing an embodiment of the receiving apparatus according to the present invention. In FIG. 4, the same components as those in FIG. 24 are designated by the same reference numerals. The present embodiment is for receiving a transmission signal from the transmission device of FIG.

The received signal is input to the input terminal 11. This received signal is output from the transmitter of FIG. 1 as a transmitted signal to a transmission line (not shown). The received signal is provided to the demodulation and demapping circuit 12. The demodulation and demapping circuit 12 restores the input data to the original data before mapping by the reverse processing of the modulation and mapping processing performed on the transmission side, and outputs it to the inner decoder 13. The inner decoder 13 performs error correction using the error correction code created by the inner coding process on the transmitting side, and then outputs the error to the synchronization circuit 35. Note that the inner decoder 13 is not necessary when the inner coding process is not performed on the transmitting side.

The synchronizing circuit 35 is a frame synchronizing code detecting circuit.
36 and a frame synchronization byte deletion circuit 37. Since the transmitting side performs the scrambling process, the Reed-Solomon encoding process, and the interleaving process on a frame-by-frame basis, the receiving side performs the synchronization pull-in before the reverse process of these processes. That is, the frame synchronization code detection circuit 36 of the synchronization circuit 35 is
SYNC, inverted SYNC, FAW or inverted FAW is detected. The frame synchronization code detecting circuit 36 establishes frame synchronization by FAW and SYNC, and scramble synchronization by FAW and SYNC inversion. Since not only SYNC or inverted SYNC but FAW or inverted FAW is used for synchronization, reliable synchronization pull-in is possible even when noise is mixed in the transmission path. Also, as a frame synchronization code
Even if the data does not use the SYNC or the inverted SYNC, the sync pull-in can be performed by using the FAW or the inverted FAW.

The frame sync code detection circuit 36 outputs the input data in which the frame sync code is detected to the frame sync byte deletion circuit 37. Frame sync byte deletion circuit 37
Deletes the nf-bit FAW and the inverted FAW from the frame synchronization code and outputs it to the deinterleave circuit 16. This allows FAW or reverse FAW on the sending side.
The data before the addition, that is, the data in which only the synchronization bytes are arranged as the frame synchronization code is returned.

The deinterleave circuit 16 returns the input data to the original data array by the reverse process of the interleave process on the transmitting side and outputs it to the Reed-Solomon decoder 17. The Reed-Solomon decoder 17 performs error correction using the redundant bits of 2t bytes added for each frame. The Reed-Solomon decoder 17 outputs to the descramble circuit 18 188-byte-long frame-unit data.

The descrambling circuit 18 is composed of a descrambling processing circuit 19 and an inverting circuit 20. The descramble processing circuit 19 performs the descramble processing by an exclusive OR operation of the data portion excluding the synchronization byte and the pseudo random number. The data descrambled by the descramble processing circuit 19 is given to the inverting circuit 20. The inversion circuit 20 inverts the beginning of the scrambled frame.
It is designed to invert SYNC and return it to the original SYNC for output.

Next, the operation of the receiving apparatus thus configured will be described with reference to FIG. FIG. 5 is a flow chart for explaining the operation of the receiving device.

The received signal inputted is given to the demodulation and demapping circuit 12. Demodulation and demapping circuit 12
In step S21, demodulation processing and demapping processing are performed to obtain the original data string before the mapping and modulation processing on the transmission side. When inner coding is performed on the transmitting side, the output of the demodulation and demapping circuit 12 is given to the inner decoder 13 and is inner decoded.

Next, in step S22, the synchronizing circuit 35
Synchronous pull-in is performed. The frame sync code detection circuit 36 uses the input data as FAW, SYNC, and inverted FAW.
And reverse sync. Frame sync code detection circuit 36
Acquires frame synchronization by FAW and SYNC included in the input data, and scramble synchronization by FAW and SYNC inversion.

Since the FAW or the inverted FAW is inserted on the transmitting side so that the autocorrelation of the frame synchronization code is high, even if the frame synchronization code is affected by noise in the transmission path, the frame synchronization code is Can be easily detected. Further, even when a frame that does not include SYNC is transmitted, FAW or inverted FAW can be used for frame synchronization and scramble synchronization.

Further, among the detected frame synchronization codes, the FAW and the inverted FAW are output after being deleted by the frame synchronization byte deletion circuit 37. Therefore, the output of the synchronizing circuit 35 has a frame structure of (188 + 2t) byte unit, and the data to which only the synchronizing byte is added as the frame synchronizing code can be obtained.

Data synchronized with the frame and scrambled from the synchronizing circuit 35 is deinterleaved by the deinterleave circuit 16.
Is output to The deinterleave circuit 16 is step S23.
In, convolutional deinterleave processing is performed. As a result, the data is returned in the order of the data before the interleave processing on the transmitting side.

Next, in step S24, the Reed-Solomon decoder 17 performs error correction using the Reed-Solomon code. Even if a burst error has occurred in the transmission line, the burst error is converted into a random error by the deinterleaving process, so that the error can be efficiently corrected by the error correction by the Reed-Solomon decoder 17.

In the next step S25, a transmission descrambling process is performed. The data from the Reed-Solomon decoder 17 is descrambled by the descramble processing circuit 19 of the descramble circuit 18.
Given to. The descramble processing circuit 19 performs an exclusive OR operation of the portion excluding the synchronization byte and the pseudo random number to descramble. Next, the inversion circuit 20 inverts the inversion SYNC at the beginning of the scrambled frame, and
Return to As a result, the transport stream, which is the data before scramble processing on the transmission side, is restored. The transport stream from the descramble circuit 18 is output from the output terminal 18 as a decoded output.

As described above, in the present embodiment, since the synchronization pull-in is performed using the FAW and SYNC or the inverted FAW and the inverted SYNC added on the transmitting side, the synchronization performance is extremely high. Further, since the FAW and the inverted FAW are removed after the synchronization pull-in, the circuit at the previous stage can be the same as the conventional one.

FIG. 6 is a block diagram showing a transmitting apparatus according to another embodiment of the present invention. 6, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

The present embodiment differs from the embodiment of FIG. 1 in that a scramble circuit 41 is adopted instead of the scramble circuit 2. The scramble circuit 41 does not have the SYNC inverting circuit 4 but has only the scramble processing circuit 3. The scramble processing circuit 3 scrambles the input transport stream and outputs it to the Reed-Solomon encoder 5.

Next, the operation of the embodiment thus configured will be described with reference to FIG. FIG. 7 is an explanatory diagram showing the frame structure of the output of the code insertion circuit 31.

The input transport stream is
It is given to the scramble processing circuit 3 of the scramble circuit 41 and scrambled. In the present embodiment, the scrambled data is supplied to the Reed-Solomon encoder 5 as it is. That is, SYNC is not inverted.

The output of the interleave circuit 6 is supplied to the code insertion circuit 31. The code insertion circuit 31 determines the SY of each frame.
Insert FAW or reverse FAW before NC. That is, the code insertion circuit 31 inserts the inverted FAW before the SYNC at the beginning of the scramble frame, and inserts the FAW before the SYNC at the beginning of another frame. In this way, the data having the frame structure shown in FIG. 7 is obtained.

Other functions are similar to those of the embodiment shown in FIG.

By using a code having a higher autocorrelation than SYNC as the frame FAW, the synchronization performance can be improved. For example, as FAW, 16
You may use 2 bytes of "CA1E" by a decimal display. In this case, the number of constituent bits of the frame synchronization code is larger than that of SYNC, and when an appropriate FAW is selected, the autocorrelation of FAW and inverted FAW is higher than that of SYNC.

FIG. 8 is a block diagram showing a receiving apparatus according to another embodiment of the present invention. 8, the same components as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

The present embodiment is for receiving the transmission signal transmitted from the transmission device of FIG. In this embodiment,
4 is different from the embodiment of FIG. 4 in that a synchronous circuit 42 is adopted instead of the synchronous circuit 35 and a descramble circuit 44 is adopted instead of the descramble circuit 18.

The synchronizing circuit 42 is a frame synchronizing code detecting circuit 43.
And a frame synchronization byte deletion circuit 37. The frame sync code detection circuit 43 is FAW or inverted F
Detect AW. The frame sync code detection circuit 43 is
Frame synchronization is obtained by detecting W, and FAW is inverted.
The scrambling synchronization is obtained by detecting. The frame synchronization byte deletion circuit 37 uses the FAW from the data in which the frame synchronization and the scramble synchronization have been achieved.
And the inverted FAW are deleted and output to the deinterleave circuit 16.

The descramble circuit 44 is composed of the descramble processing circuit 19. The descramble processing circuit 19 descrambles the input data.
The output of the descramble processing circuit 19 is the output terminal 21 as it is.
It is designed to be output as a decoded output to.

Next, the operation of the embodiment configured as described above will be described.

The received signal is demodulated and demapped by the circuit 12
Demodulated and demapped by the inner decoder 13
It is given to the synchronizing circuit 42 after being error-corrected by.
The frame synchronization code detection circuit 43 of the synchronization circuit 42 detects FAW and inverted FAW from the input data. The frame synchronization code detection circuit 43 establishes frame synchronization by the detected FAW and scramble synchronization by the inverted FAW. The frame synchronization byte deletion circuit 37 deletes the FAW and the inverted FAW and outputs them.

The synchronized data is deinterleaved by the deinterleave circuit 16, error-corrected by the Reed-Solomon decoder 17, and supplied to the descramble circuit 44. The descramble processing circuit 19 of the descramble circuit 44 descrambles the input data. Since SYNC is not inverted on the transmitting side, the output of the descramble processing circuit 19 is output to the output terminal 21 as it is as a decoded output.

As described above, in the present embodiment, the FAW or inverted FAW having a higher autocorrelation than SYNC is added to the head of the frame on the transmitting side, and F on the receiving side.
Synchronize using AW or FAW inversion. Since the autocorrelation of FAW and inverted FAW is higher than that of SYNC, the synchronization performance is higher than before. Further, since SYNC is not used for the synchronization pull-in, it is possible to mix the data of the frame structure in which the SYNC is not inserted. It is possible to omit the inverting circuit that inverts SYNC or inversion SYNC on the transmitting side and the receiving side, and it is possible to reduce the circuit scale.

FIG. 9 is a block diagram showing a transmitting apparatus according to another embodiment of the present invention. 9, the same components as those in FIG. 6 are designated by the same reference numerals and the description thereof will be omitted. This embodiment is different from the embodiment of FIG. 6 in that a code insertion circuit 51 is provided instead of the code insertion circuit 31. The code insertion circuit 51 inserts FAW before SYNC of each frame, and further FAW
The nc-bit control code (hereinafter, referred to as CON) or the inverted CON that is the inverted CON is inserted before. The code insertion circuit 51 inserts the inverted CON at the beginning of the first frame of the scrambled frame and inserts the CON at the beginning of each of the other frames. Thus, one frame is (188 + 2) from the code insertion circuit 31.
t) × 8 + nf + nc bits, and data in which one scramble frame is composed of 8 frames is output.

Next, the operation of the embodiment thus configured will be described with reference to FIG. FIG. 10 is an explanatory diagram showing an output frame configuration of the code insertion circuit 51. In the following figures, the inverted CON is shown with a bar above CON.

An MPEG2 transport stream, for example, is input to the input terminal 1. The transport stream is subjected to scramble processing, Reed-Solomon encoding processing and interleave processing, and is supplied to the code insertion circuit 51. The data input to the code insertion circuit 51 is
It has a length of (188 + 2t) bytes. In addition, SYNC is arranged at the beginning of each frame. The beginning of the scramble frame is also SYNC.

The code insertion circuit 51 inserts FAW before SYNC arranged at the head of each frame, and further, FAW
Insert the CON or the inverted CON before the. That is, the code insertion circuit 51 inserts the inverted CON at the beginning of the scrambled frame for every eight frames and the CO at the beginning of other frames.
Insert N. In this way, the data having the frame structure shown in FIG. 10 is obtained.

Other functions are similar to those of the embodiment shown in FIG.

In this embodiment, FAW and SYNC
The frame auto-correlation code composed of is higher than SYNC. By using the frame synchronization code composed of FAW and SYNC on the receiving side, it is possible to improve the synchronization performance.

Further, predetermined control information can be transmitted by CON.

FIG. 11 is a block diagram showing a receiving apparatus according to another embodiment of the present invention. 11, the same components as those in FIG. 8 are designated by the same reference numerals and the description thereof will be omitted.

The present embodiment receives a transmission signal from the transmission device shown in FIG. In this embodiment, the synchronization circuit 42
8 is different from the embodiment shown in FIG. 8 in that a synchronizing circuit 55 is used instead. The synchronization circuit 55 is composed of a frame synchronization code detection circuit 56, a control code identification circuit 57 and a deletion circuit 58.

The frame synchronization code detection circuit 56 detects FAW and SYNC from the input data to obtain frame synchronization and outputs it to the control code identification circuit 57. Control code identification circuit
57 detects CON or inverted CON from the input data, identifies the beginning of the scrambled frame by the inverted CON, and achieves scramble synchronization. The output of the control code identification circuit 57 is supplied to the deletion circuit 58. The deletion circuit 58 deletes FAW, CON and inverted CON from the input data and outputs the data to the deinterleave circuit 16.

Next, the operation of the embodiment thus configured will be described with reference to FIG. FIG. 12 shows FIG.
3 is a flowchart for explaining the operation of the first embodiment. The procedure of the operation of this embodiment is almost the same as the procedure of the operation of the embodiment of FIG. 4, and in FIG. 12, the same steps as those in FIG.

The received signal is subjected to demodulation, demapping and inner decoding in step S21. Inner decoder
The data from 13 is supplied to the synchronization circuit 55. Synchronous circuit 55
In step S31, the transmission frame identification and synchronization pull-in shown in step S31 are performed. That is, the frame synchronization code detection circuit 56 of the synchronization circuit 55 obtains frame synchronization by detecting FAW and SYNC. Further, the control code identification circuit 57 detects CON or inverted CON from the input data, and outputs the inverted C
When ON, the beginning of the scramble frame is identified to obtain scramble synchronization. The deletion circuit 58 becomes unnecessary F
AW, CON and inverted CON are deleted from the input data and output to the deinterleave circuit 16.

The data subjected to the deinterleave processing and the error correction processing by the deinterleave circuit 16 and the Reed-Solomon decoder 17 are given to the descramble processing circuit 19 and descrambled. In this case, as in the embodiment of FIG. 8, since the inverted SYNC is not included, the output of the descramble processing circuit 19 is directly output to the output terminal 21 as the decoded output without performing the inversion processing. .

As described above, also in this embodiment, the same effect as that of the embodiment of FIG. 8 can be obtained.

FIG. 13 is a block diagram showing a transmitting apparatus according to another embodiment of the present invention. 13, the same components as those of FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.
The present embodiment is applied to time division multiplex broadcasting.

This embodiment differs from the embodiment of FIG. 1 in that a code insertion circuit 61 is provided instead of the code insertion circuit 31.
The code insertion circuit 61 inserts FAW or inverted FAW before SYNC of each frame. In this embodiment, FAW
FAW1, FAW2, which support multiple channels as
FAW3, ... Is used. An inverted FAW is inserted before the inverted SYNC of the head frame of the scrambled frame, and an FAW is inserted before the SYNC of the head of another frame. For example, when 4 channels are multiplexed and the channel is switched for each frame, the inverted SYNC at the beginning of the scrambled frame
Inserting an inverted FAW1 which is an inversion of FAW1 in front of, for example, FAW2, FAW3, F at the beginning of each frame.
Insert AW4, FAW1, ... Thus, one frame from the code insertion circuit 61 is (188 + 2t) × 8 + nf
In bits, data in which one scramble frame is composed of 8 frames is output.

It should be noted that, as FAW and SYNC or inverted FAW and inverted SYNC, the use of a code having a higher autocorrelation than SYNC or inverted SYNC is the same as in the embodiment of FIG.

Next, the operation of the embodiment thus configured will be described with reference to FIG. FIG. 14 is an explanatory diagram showing an output frame configuration of the code insertion circuit 61.

An MPEG2 transport stream, for example, is input to the input terminal 1. It is assumed that this transport stream is multiplexed with 4-channel data. The transport stream is subjected to scramble processing, SYNC inversion processing, Reed-Solomon coding processing, and interleave processing, and is supplied to the code insertion circuit 61. The data input to the code insertion circuit 61 is (188+
2t) byte length. Also, the beginning of the scrambled frame is inverted SYNC, and the beginning of other frames is SYNC.
Are arranged.

The code insertion circuit 61 has a FAW corresponding to a channel before SYNC arranged at the head of each frame.
1, FAW2, ... Are inserted, and an inverted FAW (inverted FAW1 in FIG. 14) corresponding to the channel is inserted before the inverted SYNC arranged at the beginning of the scrambled frame. In this way, as shown in FIG. 14, a data string in which a frame synchronization code is formed by FAW or inverted FAW and SYNC or inverted SYNC corresponding to each channel is obtained.

Other operations are similar to those of the embodiment shown in FIG.

Also in the present embodiment, FAW and SYNC
Alternatively, it is clear that the synchronization performance can be improved on the receiving side by making the auto-correlation of the frame synchronization code composed of the inverted FAW and the inverted SYNC higher than that of the SYNC or the inverted SYNC.

Also, the channel information of the transmission frame can be transmitted by FAW.

FIG. 15 is a block diagram showing a receiving apparatus according to another embodiment of the present invention. 15, the same components as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

The present embodiment is for receiving a transmission signal from the transmission device of FIG. This embodiment is a synchronous circuit
The difference from the embodiment of FIG. 4 is that a synchronizing circuit 65 is used instead of 35. The synchronization circuit 65 is a frame synchronization code detection circuit 66,
It is composed of a FAW identification circuit 67 and a frame synchronization byte deletion circuit 68.

The frame synchronization code detecting circuit 66 detects FAW (FAW1, FAW2, ...) And SYNC from the input data.
Alternatively, inversion FAW (inversion FAW1, inversion FAW2, ...) And inversion SYNC are detected. The frame sync code detection circuit 66 obtains frame sync by FAW and SYNC, and
And scramble synchronization is obtained by SYNC and FAW.
Output to the identification circuit 67. The FAW identification circuit 67 identifies the FAW or the inverted FAW of the input data,
It is determined which channel each frame corresponds to. The output of the FAW identification circuit 67 is supplied to the frame synchronization byte deletion circuit 68. The frame synchronization byte deletion circuit 68 uses the input data as FAW and inverted FAW.
Are deleted and output to the deinterleave circuit 16.

Next, the operation of the embodiment thus configured will be described.

The received signal is sent to the demodulation and demapping circuit 12
Further, the inner decoder 13 performs demodulation, demapping and inner decoding processing. The data from the inner decoder 13 is supplied to the synchronization circuit 65. The frame synchronization code detection circuit 66 of the synchronization circuit 65 uses FAW and SYNC or inverted FAW and inverted SYNC.
To detect frame synchronization and scramble synchronization. Further, the FAW identification circuit 67 identifies the FAW or the inversion FAW of the input data and determines the channel of each frame. The frame sync byte deletion circuit 68
The unnecessary FAW and inverted FAW are deleted from the input data and output to the deinterleave circuit 16.

Other functions are similar to those of the embodiment shown in FIG.

As described above, the present embodiment has an advantage that the same effect as that of the embodiment of FIG. 1 is obtained and that the channel can be identified by FAW or inverted FAW.

FIG. 16 is a block diagram showing a transmitting apparatus according to another embodiment of the present invention. In FIG. 16, the same components as those in FIG. 9 are designated by the same reference numerals and the description thereof will be omitted.
The present embodiment is an example applied to multiplex transmission of transmission frames of different systems. For example, a transmission frame (hereinafter referred to as an A frame) obtained by performing a scramble process, a Reed-Solomon encoding process, and a convolutional interleave process on an MPEG2 transport stream and an FEC (Forward Error Correlation) different from the A frame.
An example will be described in which a transmission frame subjected to rection) encoding (hereinafter referred to as a B frame) is time-division multiplexed and alternately transmitted for each scramble frame.

The present embodiment differs from the embodiment of FIG. 9 in that a code insertion circuit 71 is provided instead of the code insertion circuit 51.
In this embodiment, at the beginning of the scramble frame
SYNC is not inverted. The code insertion circuit 71 uses (188
+ 2t) bytes, that is, A for each scrambled frame
Alternately read frames and B frames.

The code insertion circuit 71 inserts the inverted FAW before the SYNC at the beginning of the first frame of the scrambled frame and inserts the FAW before the SYNC of other frames.
Further, the code insertion circuit 71 uses the nc-bit C before the FAW.
Insert ON. In the present embodiment, CON is CON1, CON according to the type of transmission frame.
Insert 2, ... For example, when transmitting an A frame and a B frame as transmission frames, a C is added at the beginning of each scramble frame for transmitting the A frame.
The ON1 is inserted, and the CON2 is inserted at the beginning of each frame of the scramble frame for transmitting the B frame.

Thus, the code insertion circuit 71 outputs data in which one frame is composed of (188 + 2t) × 8 + nf + nc bits and one scramble frame is composed of eight frames. As shown in FIG. 17, CON1, FAW and SYNC are arranged in the first frame of the scrambled frame, or CON2, FAW and SYNC are arranged in the first frame, and CON1, FAW and SY are arranged at the head of other frames.
NC is arranged or CON2, FAW and SYNC are arranged.

Also in this embodiment, a code having a higher autocorrelation than SYNC is used as FAW and inverted FAW.

Next, the operation of the embodiment thus configured will be described with reference to FIG. 18 is shown in FIG.
11 is a flowchart for explaining the operation in the sixth embodiment. The operation procedure of the present embodiment is almost the same as the procedure shown by the flowchart of FIG. 2, and in FIG. 18, the same components as those in FIG.

An MPEG2 transport stream, for example, is input to the input terminal 1. The transport stream is subjected to scrambling processing, Reed-Solomon coding processing and interleaving processing in steps S1 to S3, and is supplied to the code insertion circuit 71. The data of the A frame input to the code insertion circuit 71 is (188+
2t) byte length. Also, at the beginning of each frame, SY
NCs are arranged. The beginning of the scramble frame is also SYNC. In this embodiment, the B-frame data is also input to the code insertion circuit 71.

Now, assume that the data of the A frame is transmitted in a predetermined scramble frame. In this case, the code insertion circuit 71 is arranged in the head frame of this scramble frame in step S41.
The inverted FAW is inserted before the SYNC, and the CON1 is inserted before the inverted FAW. In the other frames of this scrambled frame, the code insertion circuit 71 starts the CO
Insert N1 and then FAW.

In the next scrambled frame,
The code insertion circuit 71 uses the SYNC signal arranged in the first frame.
Insert an inversion FAW in front of the
Insert ON2. Other B of this scrambled frame
In the frame, the code insertion circuit 71 has a CON
Insert 2, then FAW. Thus, FIG.
Data of the frame structure shown in is obtained.

Other functions are similar to those of the embodiment shown in FIG.

In the present embodiment, the autocorrelation of the frame synchronization code formed by FAW and inverted FAW is set higher than that of SYNC. Thereby, the synchronization performance can be improved on the receiving side. Also, CON1,
The transmission frame type can also be identified by CON2.

FIG. 19 is a block diagram showing a receiving apparatus according to another embodiment of the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals and description thereof is omitted.

The present embodiment is for receiving a transmission signal from the transmitting apparatus of FIG. This embodiment is a synchronous circuit
11 in that a synchronizing circuit 75 is used instead of 55. The synchronization circuit 75 is a frame synchronization code detection circuit 7
6. The control code identification circuit 77 and the deletion circuit 78 are included.

The frame synchronization code detection circuit 76 detects FAW or inverted FAW from the input data. The frame synchronization detection circuit 76 detects FAW to obtain frame synchronization, detects inverted FAW to obtain scramble synchronization, and outputs the control code identification circuit 77. The control code identification circuit 77 detects CON1, CON2, ... From the input data.
When the data having the frame structure shown in FIG. 17 is input, the control code identification circuit 77 detects that the frame is a scramble frame for transmitting the A frame by CON1, and is a scramble frame for transmitting the B frame by CON2. Detect that. Control code identification circuit 77
Is supplied to the deletion circuit 78. The deletion circuit 78 uses the input data as CON (CON1, CON2, ...), F
Deinterleave circuit 16 with AW and inverted FAW deleted
Output.

Next, the operation of the embodiment thus configured will be described with reference to FIG. FIG. 20 shows FIG.
It is a flow chart for explaining operation of the ninth embodiment. 20, the same steps as those in FIG. 12 are designated by the same reference numerals and the description thereof will be omitted.

The received signal is demodulated and demapped in step S21, further subjected to inner decoding and supplied to the synchronizing circuit 75. The synchronization circuit 75 performs the transmission frame identification and synchronization pull-in shown in step S45.
That is, the frame synchronization code detection circuit 76 of the synchronization circuit 75 is
Frame synchronization and scramble synchronization are obtained by detecting W and inverted FAW. The control code identification circuit 77 detects and identifies CON (CON1, CON2, ...) From the input data.

Now, it is assumed that the A frame is transmitted by a predetermined scramble frame. In this case,
The control code identification circuit 77 detects that the A frame is transmitted by the scramble frame from CON1. The deletion circuit 78 outputs the data in which the CON1, FAW and inverted FAW have been deleted to the deinterleave circuit 16. In this way, the data of the A frame is stored in steps S23 to S25
In, deinterleave processing, Reed-Solomon decoding processing, and descrambling processing are performed to restore the original data.

On the other hand, when the B frame is transmitted by a predetermined scramble frame, the control code identifying circuit 77 detects that the B frame is transmitted from CON2. The deletion circuit 78 is CON2, FAW and inverted F
The AW-deleted data is output to a B-frame processing circuit (not shown). In this case, the processing of steps S23 to S25 is not performed.

As described above, in the present embodiment, FIG.
It is possible to obtain the same effect as that of the first embodiment, and it is possible to identify the type of the transmission frame by the control code even when the transmission frames of different types are multiplexed and transmitted.

In each of the above embodiments, there is an advantage that the transmitter can be constructed by using the conventional circuit other than the code insertion circuit, and the receiver uses the conventional circuit except the synchronizing circuit. There is an advantage that it can be configured.

[0120]

As described above, according to the present invention, it is possible to improve the synchronization performance and to coexist a plurality of frame configurations including a transmission system in which no synchronization byte is arranged at the head of the frame. It has the effect of being able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a transmission device according to the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment of FIG. 1;

FIG. 3 is an explanatory diagram for explaining a frame configuration in the embodiment of FIG. 1.

FIG. 4 is a block diagram showing an embodiment of a receiving apparatus according to the present invention.

5 is a flow chart for explaining the operation of the embodiment of FIG.

FIG. 6 is a block diagram showing another embodiment of the present invention.

7 is a flowchart for explaining the operation of the embodiment of FIG.

FIG. 8 is a block diagram showing another embodiment of the present invention.

FIG. 9 is a block diagram showing another embodiment of the present invention.

FIG. 10 is an explanatory diagram for explaining a frame configuration in the embodiment of FIG.

FIG. 11 is a block diagram showing another embodiment of the present invention.

12 is a flowchart for explaining the operation of the embodiment of FIG.

FIG. 13 is a block diagram showing another embodiment of the present invention.

FIG. 14 is an explanatory diagram for explaining a frame configuration in the embodiment of FIG.

FIG. 15 is a block diagram showing another embodiment of the present invention.

FIG. 16 is a block diagram showing another embodiment of the present invention.

FIG. 17 is an explanatory diagram for explaining a frame configuration in the embodiment of FIG.

18 is a flowchart for explaining the operation of the embodiment of FIG.

FIG. 19 is a block diagram showing another embodiment of the present invention.

20 is a flowchart for explaining the operation of the embodiment of FIG.

FIG. 21 is a block diagram showing a conventional transmitter.

22 is a flow chart for explaining the operation of the conventional example of FIG.

FIG. 23 is an explanatory diagram illustrating a frame configuration in a conventional example.

FIG. 24 is a block diagram showing a conventional receiving device.

25 is a flowchart for explaining the operation of the conventional example of FIG.

[Explanation of symbols]

2 ... scramble circuit, 5 ... Reed-Solomon encoder,
6 ... Interleave circuit, 7 ... Inner encoder, 8 ... Mapping and modulation circuit, 31 ... Code insertion circuit

Claims (6)

[Claims] 1. A stream in which a first synchronization code is arranged for each frame is added with a second synchronization code for each frame for transmission, and synchronization is performed on the receiving side using the first and second synchronization codes. A frame synchronization method, characterized in that the pull-in is performed or the sync pull-in is performed using the second sync code. 2. A stream in which a first synchronization code is arranged for each frame is added with a second synchronization code and a predetermined control code for each frame for transmission, and the first side and the second side are transmitted on the receiving side.
Synchronization code and the predetermined control code are used for synchronization, the second synchronization code is used for the synchronization acquisition, or the second synchronization code and the predetermined control code are used for synchronization acquisition. And a step of identifying the predetermined control code. 3. A signal processing means, which is provided with a transport stream in which a first synchronization code is arranged for each packet, performs predetermined signal processing on the transport stream, and outputs in frame units based on the packet. Code insertion means for adding the second synchronization code to the output of the signal processing means in the frame unit, or adding the second synchronization code and the predetermined control code in the frame unit, and the output of the code insertion means. And a sending means for sending an output based on the above to a transmission path. 4. A first synchronization code and a second synchronization code for each frame.
The received data based on the data in which the synchronization codes are arranged is input, and the synchronization pull-in means performs the synchronization pull-in by using the first and second synchronization codes or the synchronization pull-in by the second synchronization code. A deletion unit for deleting the second synchronization code from the received data and outputting the deletion unit; and a decoding processing unit for performing an inverse process of the signal processing on the transmission side on the output of the deletion unit to restore the transport stream. A receiving device comprising: 5. The received data is data based on data having a frame structure in which the first synchronization code is not arranged or data having no frame structure. The receiving device according to 1. 6. The first synchronization code and the second synchronization code in frame units
The received data based on the data in which the synchronization code and the predetermined control code are arranged is input, and the synchronization pull-in is performed using the first and second synchronization codes and the predetermined control code, or the second synchronization is performed. A synchronization pull-in means for performing synchronization pull-in using a code or a synchronization pull-in using the second synchronization code and the predetermined control code; identification means for identifying the predetermined control code; Deleting means for deleting and outputting the second synchronization code and the predetermined control code; and decoding processing means for performing reverse processing of signal processing on the transmitting side on the output of the deleting means to restore the transport stream. A receiving device comprising: