JP3361061B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device using SiC.

[0002]

2. Description of the Related Art Conventionally, Ni has been widely used as an ohmic electrode of SiC used for a Schottky diode or the like. However, Ni reacts with silicon in SiC to form a silicide, and surplus carbon segregates on the surface of the electrode or at the interface between SiC and the electrode, resulting in a problem of high resistance or deterioration of the ohmic electrode. Further, when carbon is deposited on the surface of the ohmic electrode, when the wiring portion is formed on the surface of the ohmic electrode, the electrode portion and the wiring portion are deteriorated and the resistance is increased.

Further, in a Schottky diode using SiC, a guard ring of a conductivity type opposite to that of the SiC substrate is provided in the peripheral portion of the Schottky electrode in order to obtain a withstand voltage with a reverse voltage. However, when a Schottky electrode for obtaining a Schottky junction and an electrode for a guard ring that requires ohmic contact are formed from the same electrode material, a Schottky junction is obtained but sufficient ohmic contact cannot be obtained. There's a problem.

On the other hand, in SiC, carriers are often trapped in a deep level created by impurities, resulting in a decrease in carrier concentration, and in many crystal defects caused by vacancies, carrier mobility is decreased. There is also a problem that the electrical characteristics of the device are deteriorated.

[0005]

As described above, the semiconductor device using SiC has a problem that the resistance increases in the ohmic electrode region and the like due to the deposition of carbon and the like. In addition, SiC has a problem that carrier concentration and carrier mobility are easily reduced due to traps and crystal defects.

The present invention has been made to solve the above-mentioned conventional problems, and a semiconductor device using SiC has a first object to reduce the resistance in an ohmic electrode region or the like, and has a SiC carrier concentration. The second purpose is to improve carrier mobility.

[0007]

The present invention is a semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region has Si> 0.5.
It is characterized in that it is configured to include an _x C _1-x layer.

A Si _x C _1-x layer with x> 0.5 is Si
The bandgap is narrower than that of C (which is simply referred to as SiC in the present specification, unless otherwise specified, usually means Si _0.5 C _0.5 ). Therefore, according to the present invention, by providing a Si _x C _1-x layer in which x> 0.5, metal / metal
The energy barrier height at the semiconductor interface can be lowered, and ohmic contact resistance can be reduced.

The present invention is also a semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region is a Si _x C _1-x layer and a carbide in which x> 0.5. It is characterized by including a layer made of a carbide of the first element having a negative enthalpy of formation.

In the present invention, since the carbide formation enthalpy of the first element has a negative value, the carbon in the SiC region and the first
Element reacts to form a carbide of the first element, and a Si _x C _1-x layer with x> 0.5 is formed.
With this Si _x C _1-x layer, ohmic contact resistance can be reduced as in the previous invention. In addition, due to the action of the first element having a negative enthalpy of carbide formation,
Problems such as high resistance and deterioration of the electrode caused by carbon deposition can be prevented.

Further, the present invention is a semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region is S heavily doped with impurities.
It is characterized in that it is configured to include an iC layer.

According to the present invention, by providing a highly doped SiC layer, when a metal layer or the like is formed thereon, carriers can tunnel the SiC region / metal layer interface, and ohmic contact can be achieved. The resistance can be reduced. In addition, the SiC layer referred to here includes Si
_In addition to the _0.5 C _0.5 layer, a Si _x C _1-x layer with x> 0.5 is also included.

The present invention is also a semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region is a carbide of a first element having a negative carbide formation enthalpy. And a layer of a silicide of a second element having a negative suicide formation enthalpy, or a carbide of a first element having a negative carbide formation enthalpy. It is characterized by including a layer in which a region and a region of the silicide of the second element having a negative enthalpy of formation of silicide are mixed.

In the present invention, since the silicide formation enthalpy of the second element has a negative value, the silicon in the SiC region and the second
Element reacts to form a second element silicide, which provides good ohmic contact to the SiC region. Further, since the carbide formation enthalpy of the first element has a negative value, carbon in the SiC region reacts with the first element to easily form the carbide of the first element, and the precipitation of carbon accompanying the formation of the silicide. It is possible to prevent problems such as high resistance and deterioration of the electrode caused by the above.

Further, the present invention is a semiconductor device having an n-type SiC region and an electrode region formed on the n-type SiC region, wherein the electrode region has a first carbide formation enthalpy having a negative value. A layer of a carbide of the element, a layer of a silicide of the second element and a layer of a nitride of the second element having a negative silicide formation enthalpy, or a carbide A layer in which a carbide region of the first element having a negative enthalpy of formation, a silicide region of a second element having a negative enthalpy of formation of silicide, and a nitride region of the second element are mixed. It is characterized in that it is configured to include.

In the present invention, similar to the above-mentioned invention, good ohmic contact is obtained by the silicide of the second element, and the precipitation of carbon can be suppressed by forming the carbide of the first element. In addition to the effect, the action of the nitride of the second element prevents nitrogen, which is an n-type dopant in the n-type SiC region, from being extracted from the n-type SiC region, and can prevent a decrease in doping concentration. The effect that the ohmic contact resistance can be reduced can be obtained.

The present invention also provides a semiconductor device having a p-type SiC region and an electrode region formed on the p-type SiC region, wherein the electrode region has a first carbide formation enthalpy having a negative value. A layer made of a carbide of an element, a layer made of a silicide of a second element having a negative silicide formation enthalpy, and a layer containing a third element of Group 2 or Group 3, Alternatively, a layer in which a region of carbide of the first element having a negative value of carbide formation enthalpy and a region of a second element silicide having a negative value of silicide formation enthalpy are mixed, and a group 2 or 3 group It is characterized in that it is configured to include a layer containing a third element.

In the present invention, as in the previous invention, good ohmic contact is obtained with the silicide of the second element, and the precipitation of carbon can be suppressed by forming the carbide of the first element. In addition to the effect, a layer containing the third element (usually SiC doped with the third element as an impurity (Si _0.5 C _0.5 or Si _{x with} x> 0.5)
C _1-x )) can be tunneled by the carrier, so that the ohmic contact resistance can be reduced.

The present invention also provides a semiconductor device having a p-type SiC region and an electrode region formed on the p-type SiC region, wherein the electrode region has a negative enthalpy of carbide formation and negative enthalpy of formation of silicide. A layer of a carbide of a fourth element having a value, a layer of a silicide of the fourth element, and a layer containing a third element of Group 2 or Group 3, or an enthalpy of carbide formation And a layer in which a carbide region of the fourth element having a negative enthalpy of formation of silicide and a region of the silicide of the fourth element are mixed, and 2
It is characterized by including a layer containing a third element of Group 3 or Group 3.

In the present invention, the carbide formation enthalpy and the silicide formation enthalpy of the fourth element are both negative, and the first element and the second element in the above invention are the same element. Therefore, similar to the above invention, good ohmic contact can be obtained by the silicide of the fourth element, and the formation of the carbide of the fourth element can suppress the precipitation of carbon. Tunneling of the carrier through the layer containing the third element has the effect of reducing ohmic contact resistance.

Further, the present invention is a semiconductor device having a SiC region, an electrode portion formed on this SiC region, and a wiring portion formed on this electrode portion, and the material used for the wiring portion is predetermined. It is characterized in that the metal contains silicon and carbon.

It is preferable that the predetermined metal contains silicon and carbon at a concentration equal to or higher than the solid solution limit for the metal.

According to the present invention, since the metal of the wiring portion contains carbon in addition to silicon, deterioration of the electrode portion and the wiring portion and an increase in resistance caused by the deposition of carbon from the SiC region can be prevented. Can be prevented.

[0024] The present invention is a semiconductor device having a SiC region and the electrode region formed on the SiC region, the electrode region is Ge concentration 10 ²¹ cm ^-3 or more Si _1-xy C It is characterized in that it is configured to include an _x Ge _y layer.

The band gap of Si _1-xy C _x Ge _y is narrower than that of SiC. Therefore, according to the present invention, S
By providing the i _1-xy C _x Ge _y layer, the energy barrier height at the metal / semiconductor interface can be lowered when the metal layer or the like is formed thereon, and the ohmic contact resistance can be reduced. Si _1-xy C _x Ge
_{The y} layer may be doped with an element serving as an impurity. By introducing Ge and impurities by making them amorphous by ion implantation or the like, it is possible to dramatically improve the doping concentration of the impurities and further reduce the resistance. The range of x is preferably 0 <x ≦ 0.5, and the range of y is preferably 0 <y ≦ 0.3.

Further, according to the present invention, a first conductivity type SiC region, an electrode portion Schottky-bonded to the first conductivity type SiC region, and an electrode portion in a region corresponding to an outer peripheral portion of the electrode portion. A semiconductor device having a second-conductivity-type SiC region sandwiched between the first-conductivity-type SiC region and a Ge concentration of 10 ^{21 at} a boundary portion between the electrode portion and the second-conductivity-type SiC region. cm ^-3 or higher Si _1-xy C _x Ge _y
It is characterized in that a layer is formed.

According to the present invention, S having a predetermined Ge concentration is formed at the boundary between the electrode portion and the second conductivity type SiC region serving as the guard ring.
i _1-xy C _x Ge _y layer (0 <x ≦ 0.5, 0 <y ≦ 0.
3 is preferably formed), it is possible to obtain a sufficiently low ohmic contact between the electrode portion and the guard ring.

The semiconductor device according to the present invention is characterized by having a SiC region containing oxygen or hydrogen of 1 × 10 ¹⁸ cm ^-3 or less. The oxygen concentration is also 1
It is preferably × 10 ¹⁸ cm ⁻³ or less.

In the present invention, the deep level created by the non-dopant impurity can be compensated by containing hydrogen in SiC, and the crystal defect can be relaxed by containing oxygen in SiC. The carrier concentration and carrier mobility can be increased.

[0030]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view showing an example of an electrode structure according to a first embodiment of the present invention.
As shown in FIG. 1, Si _x C _{1-x is formed} on the SiC substrate 101.
The layer 102 and the metal layer 103 are formed in layers.

The Si _x C _1-x layer has X> 0.5, and the band cap is narrower than that of SiC. Further, the ratio of Si continuously increases from the SiC / Si _x C _1-x interface in the metal layer direction, and the band gap continuously narrows in the metal layer direction. Therefore, the energy barrier at the semiconductor / metal interface is low,
Ohmic contact resistance can be reduced. In addition, the SiC substrate 1
It is also possible to improve the adhesion to the upper layer side by forming the Si _x C _1-x layer 102 on 01.

FIG. 2 is a sectional view showing another example of the electrode structure according to this embodiment. The basic structure of the electrode structure is
This is similar to the example shown in FIG. The difference from the example of FIG. 1 is that
The point is that the Si _x C _1-x layer 102 is buried in the SiC substrate 101. The position of the Si _x C _1-x layer 102 may change as in this example depending on the method of manufacturing the electrode.
It is possible to obtain the same effect as in the above example.

(Second Embodiment) FIG. 3 is a sectional view showing an example of an electrode structure according to a second embodiment of the present invention.
As shown in FIG. 3, a poly-SiC layer 120 and a metal layer 103 are formed in layers on a SiC substrate 101.

The poly-SiC layer 120 is the SiC substrate 101.
Impurities are doped so as to have the same conductivity type as the above, and the doping concentration of the poly-SiC layer 120 is 10 ¹⁸ cm.
^-3 or more. Highly doped poly S
By sandwiching iC layer 120 between SiC substrate 101 and metal layer 103, carriers tunnel the SiC substrate 101 / metal layer 103 interface, so that ohmic contact resistance can be reduced. In addition, the SiC substrate 10
By forming the poly-SiC layer 120 on the first layer 1, it is possible to improve the adhesion with the upper layer side.

(Third Embodiment) FIG. 4 is a sectional view showing an example of an electrode structure according to a third embodiment of the present invention.
As shown in FIG. 4, Si _x C _{1-x is formed} on the SiC substrate 101.
The layer 102, the first element carbide layer 105, and the first element layer (metal layer) 104 are formed in layers.

An element having a negative enthalpy of carbide formation is used as the first element, and specifically, Ta, Zr, N is used.
b, Ti, Th, Be, V, Cr, Al, B, Ce,
It is selected from W, Mn, Ca and the like.

Similar to the first embodiment, the Si _x C _1-x layer has X> 0.5, and the proportion of Si increases from the SiC / Si _x C _1-x interface toward the upper layer side. Therefore, the ohmic contact resistance can be reduced. In addition, SiC
Since the Si _x C _1-x layer 102 is formed on the substrate 101, the adhesion can be improved.

FIG. 5 is a process sectional view showing an example of a manufacturing method for manufacturing the electrode structure having the structure shown in FIG.

As shown in FIG. 5A, the SiC substrate 10
After forming the first element layer 104 in a layered manner on the first layer 1, heat treatment is performed to form a structure as shown in FIG. Since the first element is an element having a negative carbide formation enthalpy, it reacts with carbon in the SiC substrate 101 to form the first element carbide layer 105. At that time, the SiC substrate 101
Since carbon escapes from the surface, the Si _x C _1-x layer 102, which is a Si-rich region, is formed. As described above, in this example, the carbon in the SiC substrate 101 reacts with the first element, so that the problem of carbon deposition does not occur.

FIG. 6 is a process sectional view showing another example of the manufacturing method for manufacturing the electrode structure having the structure shown in FIG.

As shown in FIG. 6A, the SiC substrate 10
After forming the poly-Si layer 106 and the first element layer 104 in layers on the first layer 1, heat treatment is performed. Since the first element is an element whose enthalpy of carbide formation has a negative value, the SiC substrate 10
6 reacts with carbon in 1 to form a first element carbide layer 105 as shown in FIG. 6 (b). In addition, the SiC substrate 10
The carbon in 1 also reacts with the poly-Si layer 106,
Since carbon escapes from the surface of the C substrate 101, a Si-rich Si _x C _1-x layer 102 is formed. In addition, poly-Si
If the layer 106 is heavily doped with impurities so that it has the same conductivity type as the SiC substrate 101, the ohmic contact resistance can be further reduced.

FIG. 7 is a process sectional view showing another example of the manufacturing method for manufacturing the electrode structure having the structure shown in FIG.

As shown in FIG. 7A, the SiC substrate 10
1. After forming a poly-Si layer 106 in layers on the
Ion implanting dopant on layer 106. The SiC substrate 101 and the poly-Si layer 106 have the same conductivity type, and the dopant element to be ion-implanted is a Group 5 element if the SiC substrate 101 is n-type, specifically N, P, As, Sb, B.
SiC substrate 10 which is one or more elements selected from i
If 1 is p-type, a Group 3 element or a Group 2 element, specifically B, Al, Ga, In, Tl, Zn, Cd, Hg, S
It is one or more elements selected from c, Y, Be, Mg, Ca, Sr, Ba and Ra. Figure 7 shows the result of ion implantation.
As shown in (b), the poly-Si layer 106 becomes a doped poly-Si layer 107, and the SiC substrate 101 under the doped poly-Si layer 107 is also ion-implanted to become an amorphous region 108.

Next, as shown in FIG. 7C, a first element layer 104 is formed on the doped poly-Si layer 107 and heat treatment is performed. Since the first element is an element having a negative value for the enthalpy of carbide formation, as shown in FIG.
The elemental carbide layer 105 is formed, and the doped poly-Si layer 1 is formed.
07 also reacts with carbon to form the Si _x C _1-x layer 102. Amorphous region is recrystallized by heat treatment, but since there are characteristics of SiC as prone to 3C-SiC crystal structure when amorphized SiC is recrystallized by heat treatment, the Si _x C _1-x layer 102 crystal The structure has a large proportion of 3C. 3C-SiC is 4H-S
Since the bandgap is narrower than that of iC or 6H—SiC, the ohmic contact resistance can be further reduced.

(Fourth Embodiment) Eighth is a process sectional view showing an example of an electrode structure according to a fourth embodiment of the present invention and a manufacturing method thereof.

As shown in FIG. 8A, the SiC substrate 10
1. After forming a poly-SiC layer 109 in a layered form on
A dopant is ion-implanted on the iC layer 109. SiC
The substrate 101 and the poly-SiC layer 109 have the same conductivity type.
The dopant element to be ion-implanted is the same as that described in FIG. 7. Figure 8 shows the result of ion implantation.
As shown in (b), the poly-SiC layer 109 becomes a doped poly-SiC layer 110, and the doped poly-SiC layer 110 is formed.
The underlying SiC substrate 101 is also ion-implanted to become the amorphous region 111.

Next, as shown in FIG. 8C, after the metal layer 112 is laminated on the doped poly SiC layer 110, heat treatment is performed. Before stacking the metal layer 112, heat treatment is performed.
After that, the metal layer 112 may be laminated. This allows
As shown in FIG. 8D, a carbide layer 113 is formed,
The doped poly SiC layer 110 is recrystallized to form Si _x C
_{A 1-x} layer 102 is formed. Amorphized SiC
Has the characteristic of SiC that when it is recrystallized by heat treatment, it tends to have a 3C-SiC crystal structure.
The crystal structure of the _x C _1-x layer 102 has a large proportion of 3 C.
Therefore, the ohmic contact resistance can be reduced for the same reason as described in FIG.

(Fifth Embodiment) FIG. 9 is a sectional view showing an example of an electrode structure according to a fifth embodiment of the present invention.
As shown in FIG. 9, the second element silicide layer 124, the second element layer 123, and the first element carbide layer 12 are formed on the SiC substrate 101.
The second and first element layers 121 are formed in layers.

The first element is an element having a negative value for the enthalpy of carbide formation, and specifically, Ta, Zr, N.
b, Ti, Th, Be, V, Cr, Al, B, Ce,
It is selected from W, Mn, Ca and the like. The second element is an element whose enthalpy of formation of silicide has a negative value, and specifically, Ca, Ti, Ni, Th, Ta, Co, Mo,
It is selected from Cr, Mn, Nb, Fe, Re and the like.

FIG. 10 is a process sectional view showing an example of a method of manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 10 (a), the second element layer 123 and the first element layer 121 are formed in layers, and heat treatment is performed, so that the second element silicide layer 12 is formed as shown in FIG. 10 (b).
4 and the first element carbide layer 122 are formed.

It has been conventionally known that ohmic contact can be obtained by forming a silicide on SiC, but since the formation of a carbide layer does not cause segregation of excess carbon due to the formation of a silicide, the ohmic contact can be prevented. The resistance of the electrode can be further reduced.

(Sixth Embodiment) FIG. 11 shows a sixth embodiment of the present invention.
FIG. 4 is a cross-sectional view showing an example of an electrode structure according to the embodiment. As shown in FIG. 11, a mixed layer 125 in which a region made of the first element, a region made of the second element, a region made of the first element carbide, and a region made of the second element silicide are mixed is formed on SiC substrate 101. Has been done.

The first element is an element having a negative value for the enthalpy of carbide formation, and the same element as in the fifth embodiment is used. The second element is an element having a negative silicide formation enthalpy, and the same element as in the fifth embodiment is used.

FIG. 12 is a process sectional view showing an example of a method for manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 12A, a mixed layer 126 in which the first element and the second element are mixed is formed on the SiC substrate 101,
By performing the heat treatment, the mixed layer 125 is formed as shown in FIG.

In this example, in addition to the ohmic contact with SiC being obtained by the silicide in the mixed layer 125, the mixed layer 125
There is no segregation of excess carbon due to the formation of silicide due to the formation of carbide therein, so that the resistance of the ohmic electrode can be further reduced. Further, in the present embodiment, as compared with the fifth embodiment, only one layer needs to be deposited, so that the manufacturing method is simplified.

FIG. 13 is a sectional view showing another example of the electrode structure according to this embodiment. That is, the cap layer 127 is formed on the mixed layer 125. Cap layer 12
The material of No. 7 is preferably selected from metal elements such as Pt, Au, Pd, and Ni that are difficult to react with oxygen. By forming the cap layer 127, it is possible to prevent the electrode from reacting with oxygen in the air to deteriorate.

(Seventh Embodiment) FIG. 14 shows a seventh embodiment of the present invention.
FIG. 4 is a cross-sectional view showing an example of an electrode structure according to the embodiment. As shown in FIG. 14, on the n-type SiC substrate 130,
The second element silicide layer 134, the second element nitride layer 133, the first element carbide layer 132, and the first element layer 131 are formed.

The first element is an element having a negative value for the enthalpy of carbide formation, and the same element as in the fifth embodiment is used. The second element is an element having a negative silicide formation enthalpy, and the same element as in the fifth embodiment is used.

FIG. 15 is a process sectional view showing an example of a method of manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 15A, the n-type SiC substrate 130
A second element nitride layer 133 and a first element layer 131 are formed thereon in a layered form, and a heat treatment is performed, so that the second element silicide layer 134 and the first element carbide are formed as shown in FIG. 15B. The layer 132 is formed.

Since the ohmic contact is obtained by forming the silicide on the SiC, there is no segregation of excess carbon due to the formation of the silicide by forming the carbide layer.
The resistance of the ohmic electrode can be further reduced. Further, since the second element nitride is used, n-type S
Nitrogen, which is a dopant in iC, is not extracted from SiC, and a high concentration can be maintained, so that the ohmic contact resistance can be further reduced.

(Eighth Embodiment) FIG. 16 shows an eighth embodiment of the present invention.
FIG. 4 is a cross-sectional view showing an example of an electrode structure according to the embodiment. As shown in FIG. 16, a mixture of a region made of the first element, a region made of the second element nitride, a region made of the first element carbide, and a region made of the second element silicide on the n-type SiC substrate 130. The layer 135 is formed.

The first element is an element having a negative value for the enthalpy of carbide formation, and the same element as in the fifth embodiment is used. The second element is an element having a negative silicide formation enthalpy, and the same element as in the fifth embodiment is used.

FIG. 17 is a process sectional view showing an example of a method for manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 17A, the n-type SiC substrate 130
Mixed layer 136 on which first element and second element nitride are mixed
And a heat treatment is performed to form a mixed layer 135 as shown in FIG.

In this example, the silicide in the mixed layer 135 provides ohmic contact with SiC and the mixed layer 135.
There is no segregation of excess carbon due to the formation of silicide due to the formation of carbide therein, so that the resistance of the ohmic electrode can be further reduced. Further, due to the second element nitride, the dopant nitrogen in the n-type SiC is changed to SiC.
The ohmic contact resistance can be further reduced without being pulled out from the substrate. Further, in the present embodiment, as compared with the seventh embodiment, only one layer is required to be deposited, so that the manufacturing method is simplified.

FIG. 18 is a sectional view showing another example of the electrode structure according to this embodiment. That is, the cap layer 137 is formed on the mixed layer 135 shown in FIG.
The material of the cap layer 137 and the effect of the cap layer are
It is similar to the example of the cap layer shown in FIG.

(Ninth Embodiment) FIG. 19 shows a ninth embodiment of the present invention.
FIG. 4 is a cross-sectional view showing an example of an electrode structure according to the embodiment. As shown in FIG. 19, on the p-type SiC substrate 140,
A third element high concentration layer 145, a second element silicide layer 144, and a second element layer 14 in which impurities are heavily doped in SiC.
3, the first element carbide layer 142 and the first element layer 141 are formed.

The first element is an element having a negative value for the enthalpy of carbide formation, and the same element as in the fifth embodiment is used. The second element is an element having a negative silicide formation enthalpy, and the same element as in the fifth embodiment is used. A Group 3 element or a Group 2 element is used as the third element, and specifically, B, Al, Ga, In, T
l, Sc, Y, Be, Mg, Ca, Sr, Ba, Ra,
It is selected from Zn, Cd, Hg and the like.

FIG. 20 is a process sectional view showing an example of a method for manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 20A, p-type SiC substrate 140
As shown in FIG. 20B, the third element layer 146, the second element layer 143, and the first element layer 141 are layered on top of each other, and the third element high concentration layer 145 and the third element high concentration layer 145 are formed by heat treatment. A two-element silicide layer 144 and a first-element carbide layer 142 are formed.

In this example, by forming the high-concentration layer 145 containing the third element as a dopant, carriers are tunneled through the high-concentration layer 145, so that the ohmic contact resistance can be reduced.

(Tenth Embodiment) FIG. 21 is a sectional view showing an example of an electrode structure according to the tenth embodiment of the present invention. As shown in FIG. 21, on the p-type SiC substrate 140, a third element high-concentration layer 152 in which SiC is doped with a high concentration of impurities, a region including the first element, a region including the second element, and a third region A mixed layer 151 in which a region made of an element, a region made of a one-element carbide, and a region made of a second-element silicide are mixed is formed in a layered manner. The same elements as in the ninth embodiment are used for the first element, the second element, and the third element.

FIG. 22 is a process sectional view showing an example of a method of manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 22A, p-type SiC substrate 140
The mixed layer 153 in which the first element, the second element, and the third element are mixed is formed thereover, and heat treatment is performed, whereby FIG.
As shown in (b), the third element high-concentration layer 152 and the mixed layer 151 in which SiC is heavily doped with impurities are formed.

Also in this example, by forming the high concentration layer 152 containing the third element as a dopant, the ohmic contact resistance can be reduced as in the ninth embodiment.

FIG. 23 is a sectional view showing another example of the electrode structure according to this embodiment. That is, the cap layer 154 is formed on the mixed layer 151 shown in FIG.
The material of the cap layer 154 and the effect of the cap layer are as follows.
It is similar to the example of the cap layer shown in FIG.

FIG. 24 is a process sectional view showing an example of a method of manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 24A, the second element and the third element are ion-implanted on the p-type SiC substrate 140, and FIG.
An amorphous region 155 is formed as shown in FIG. Subsequently, as shown in FIG. 24C, a mixed layer of the first element, the second element, and the third element is formed, and heat treatment is further performed,
The mixed layer 151 is formed as shown in FIG. By further laminating the cap layer 154 thereon,
It prevents the electrode from deteriorating by reacting with oxygen in the air. As shown in FIG. 24A, when the second element and the third element are ion-implanted at the same time, the third element becomes p as a dopant.
It can be promoted to be introduced into the mold-SiC 140, and the ohmic contact resistance can be further reduced.

(Eleventh Embodiment) FIG. 25 is a sectional view showing an example of an electrode structure according to the eleventh embodiment of the present invention. As shown in FIG. 25, on the p-type SiC substrate 140, a third-element high-concentration layer 162 in which SiC is doped with a high-concentration impurity, a region including the third element, a region including the fourth element, and a fourth element A mixed layer 161 in which a region made of elemental carbide and a region made of a fourth element silicide are mixed is formed in a layered form, and a cap layer 163 is further formed.

The fourth element is an element having a negative value for both the enthalpy of carbide formation and the enthalpy of silicide formation, and specifically, Ta, Nb, Ti, Th, Cr, Mn,
It is selected from Ca and the like. A Group 3 element or a Group 2 element is used as the third element, and specifically, it is the same as the one shown above. Also in this example, by forming the high-concentration layer 162 containing the third element as a dopant, the ohmic contact resistance can be reduced.

FIG. 26 is a process sectional view showing an example of a method of manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 26A, the fourth element and the third element are ion-implanted on the p-type SiC substrate 140, and FIG.
An amorphous region 165 is formed as shown in FIG. Then, as shown in FIG.26 (c), the 3rd element layer 166 and the 4th element layer 167 are formed, and also heat processing is performed and the mixed layer 161 is formed as shown in FIG.26 (d). Further, by laminating the cap layer 163 thereon, it is possible to prevent the electrode from reacting with oxygen in the air to deteriorate.

In the first to eleventh embodiments described above, the heat treatment is carried out in an inert gas atmosphere such as Ar at 500 ° C. to 1000 ° C., preferably 700 ° C. to 90 ° C.
It is preferable to carry out at 0 ° C.

(Twelfth Embodiment) FIG. 27 is a sectional view of a semiconductor device according to the twelfth embodiment of the present invention.

As shown in FIG. 27, an IG using SiC
Al-Si-C wiring material 2 on the electrode 201a of BT201
02 is formed, and this Al-Si-C wiring material 20 is formed.
An Al wire 203 is bonded to 2. A
In the 1-Si-C wiring member 202, Si above the solid solution limit and C above the solid solution limit are solid-dissolved in Al. S in Al
The i concentration is preferably 1.5% and the C concentration is preferably about 0.7%.

When an Al--Si alloy, which is usually used as a wiring material for Si, is used for SiC, there arises a problem that carbon is extracted from SiC. In this example, S
By using Al-Si-C as described above as the wiring material formed on the iC device, the deterioration of the electrodes and the wiring material caused by the precipitation of carbon in Si is prevented, and the resistance of the electrode portion and the wiring portion is reduced. It can be reduced.

(Thirteenth Embodiment) FIG. 28 shows the first embodiment of the present invention.
4 is a cross-sectional view of a semiconductor device according to the third exemplary embodiment.

As shown in FIG. 28, SiC epi layer 212 and Schottky electrode 2 are formed on the main surface of SiC substrate 211.
13 is formed, and an ohmic electrode 214 is formed on the back surface of the SiC substrate 211. As a result, the SiC-SBD is formed.
(Schottky barrier diode) 210 is formed. On the Schottky electrode 213 and the ohmic electrode 214 of the SiC-SBD 210, an Al-Si-C wiring material 215 in which Si and C that are in the solid solution limit or more are dissolved in Al is formed. The effect of the Al-Si-C wiring material 215 is similar to the effect of the previous embodiment. By using Al-Si-C as the wiring material, the electrode and the wiring material caused by the precipitation of carbon in Si. Can be prevented and the resistance of the electrode portion and the wiring portion can be reduced.

(Fourteenth Embodiment) FIG. 29 shows a top view and a sectional view of a semiconductor device according to a fourteenth embodiment of the present invention.

As shown in FIG. 29A, the SiC-IG
The BT 222 and the SiC-SBD 221 are combined and arranged in the same package. As shown in FIG. 29B, the SiC-IGBT 222 and the SiC-SBD 221.
An Al-Si-C wiring material 223 is formed on the main surface electrode of. An electrode 225 (using Cu or the like) is formed on the Al-Si-C wiring material 223 via a metal layer 224 (using Mo or the like). In addition, SiC-IGBT
222 and an electrode 226 on the back surface side of the SiC-SBD 221.
(Using Cu or the like) is formed. Also in this example, the Al-Si-C wiring material 223 can achieve the same effect as described above.

In the above-mentioned Embodiments 12 to 14, Si is used.
Although the C-IGBT and the SiC-SBD have been described as examples, the configuration described above can be applied to other semiconductor devices such as a switching element and a rectifying element using SiC, without being limited thereto. It is possible.

(Fifteenth Embodiment) FIG. 30 is a process sectional view showing a method for manufacturing a semiconductor device according to a fifteenth embodiment of the present invention.

First, as shown in FIG. 30A, SiC
The entire substrate 251 is covered with the SiO ₂ film 252. Then S
The SiO ₂ film 252 is removed only on the back surface side of the iC substrate 251, and further, as shown in FIG.
Deposit. However, when the electrode material 253 is an ohmic electrode, a high temperature heat treatment is required to obtain a low resistance ohmic contact at the SiC / electrode interface. On the other hand, FIG.
Since the electrode 255 formed on the surface of the SiC substrate 251 in the step (d) cannot withstand the high temperature heat treatment, the electrode 255 must be formed after the formation of the electrode material 253 and the high temperature heat treatment are completed. However, the electrode 255
In order to perform the formation of S, in the step of FIG.
The SiO ₂ film 252 remaining on the iC substrate 251 must be removed. An acid such as HF is used to remove the SiO ₂ film 252. At that time, the electrode material 253 may be corroded by the acid. Therefore, the electrode material 254 is formed on the electrode material 253 by using a metal insoluble in acid to prevent the electrode material 253 from being corroded by the acid.

As the acid-resistant electrode material 254, 4A group,
Ti, Zr, Hf, V, N which are 5A group and 6A group elements
At least one metal selected from b, Ta, Cr, Mo and W is used.

(Sixteenth Embodiment) FIG. 31 is a sectional view showing an example of an electrode structure according to the sixteenth embodiment of the present invention. As shown in FIG. 31, Si is formed on the SiC substrate 301.
_{The 1-xy} C _x Ge _y layer 302 and the cap layer 303 are formed in layers. x is 0 ≦ x ≦ 0.5, y is 0 ≦ y ≦
It is 0.3, and the Ge concentration is 10 ²¹ cm ⁻³ or more.

The cap layer 303 is made of metal, intermetallic compound, etc., specifically Ni, Pd, Pt, Cu, Ag, A.
u, Zn, Al, Ga, In, C, Si, Ge, Sn,
Pb, Ti, Zr, Hf, V, Nb, Ta, Cr, M
It is desirable to use one containing one or more elements selected from o and W.

[0093] Si _1-xy C _x Ge _y is narrower band gap compared to SiC, Si _1-xy C _x between the cap layer 303 having a SiC substrate 301 and the metallic conductive
By interposing the Ge _y layer 302, the barrier at the metal / semiconductor interface can be lowered, and the ohmic contact resistance can be reduced. In addition, Si _1-xy C _x G
If the e _y layer 302 is doped to the same conductivity type as the SiC substrate 301, an ohmic electrode having a lower contact resistance can be obtained.

FIG. 32 is a sectional view showing another example of the electrode structure according to this embodiment. The basic structure of the electrode structure is similar to that of the example shown in FIG. The difference from the example of FIG. 31 is that a part of the Si _1-xy C _x Ge _y layer 302 is made of SiC.
The point is that it is buried in the substrate 301. Although the position of the Si _1-xy C _x Ge _y layer 302 may change as in this example depending on the electrode manufacturing method, the same effect as the example of FIG. 31 can be obtained.

FIG. 33 is a sectional view showing another example of the electrode structure according to this embodiment. The basic structure of the electrode structure is similar to that of the example shown in FIG. The difference from the example of FIG. 31 is that the entire Si _1-xy C _x Ge _y layer 302 is buried in the SiC substrate 301. Depending on the manufacturing method of the electrode, the Si _1-xy C _x Ge _y layer 302 as in this example is formed.
Although the position of may change, the same effect as the example of FIG. 31 can be obtained.

(Seventeenth Embodiment) FIG. 34 is a sectional view showing an example of an electrode structure according to the seventeenth embodiment of the present invention. This embodiment differs from the sixteenth embodiment in that S
The Ge layer 304 is formed in layers on the i _1-xy C _x Ge _y layer 302. In this example, the SiC substrate 301
Si _1-xy C _{x, which} has a narrower band gap than SiC
A Ge _y layer 302 is formed, and Si _1-xy is formed on the Ge _y layer 302.
Since the Ge layer 304 having a narrower band gap than C _x Ge _y is formed, the barrier at the metal / semiconductor interface can be further lowered, and the ohmic contact resistance can be further lowered.

(Eighteenth Embodiment) FIG. 35 is a process sectional view showing an example of a method for manufacturing an electrode structure having a structure as shown in the sixteenth embodiment.

As shown in FIG. 35A, the SiC substrate 3
01 after depositing a Si _1-xy C _x Ge _y layer 321 on
By performing the heat treatment, as shown in FIG. 35B, the SiC substrate 301 and the Si _1-xy C _x Ge _y layer 322 are formed.
The interface of is smoothed and the discontinuity is eased. Then, as shown in FIG. 35C, the Si _1-xy C _x Ge _y layer 32 is formed.
2 is deposited with a cap layer 323.

FIG. 36 is a process sectional view showing another example of the method for manufacturing the electrode structure having the structure shown in the sixteenth embodiment.

As shown in FIG. 36A, the SiC substrate 3
01 on top of Si _1-xy C _x Ge _y layer 321 and cap layer 3
After depositing 23 in layers, heat treatment is performed to obtain a structure as shown in FIG.

FIG. 37 is a process sectional view showing another example of the method of manufacturing the electrode structure having the structure shown in the sixteenth embodiment.

As shown in FIG. 37 (a), the SiC substrate 3
Ge at 01 with acceleration voltage of 50 keV and dose of 3 × 10 ¹⁶
Ion implantation is performed at cm ⁻² to form a Ge ion implantation region 331 in an amorphous state. Ion implantation temperature is room temperature to 8
00 ° C is desirable. G in the Ge ion implantation region 331
e is contained at a concentration of 1 × 10 ²¹ cm ⁻³ or more. next,
As shown in FIG. 37 (b), after depositing the cap layer 332, heat treatment is performed. The order of heat treatment and cap layer deposition may be reversed. By performing the heat treatment, FIG.
As shown in (c), the Ge ion implantation layer 331 is made of Si.
It becomes the _1-xy C _x Ge _y layer 333.

It is known that when an ion-implanted layer in an amorphous state is heat-treated and recrystallized, it tends to have a 3C crystal structure. Since the 3C crystal structure has a narrower bandgap than the 4H or 6H crystal structure, the Si _1-xy C _x Ge _y layer has 3 layers.
With the C crystal structure, the ohmic contact resistance can be further reduced. Further, by adjusting the power and the dose amount of Ge ion implantation, it is possible to freely control the Ge concentration, the implantation region, and further the ohmic characteristics.

(19th Embodiment) FIG. 38 is a process sectional view showing an example of a method for manufacturing an electrode structure having a structure as shown in the 17th embodiment.

As shown in FIG. 38A, the SiC substrate 3
Ge at 01 with acceleration voltage of 50 keV and dose of 3 × 10 ¹⁶
Ion implantation is performed at cm ⁻² to form a Ge ion implantation region 331 in an amorphous state. Ion implantation temperature is room temperature to 8
00 ° C is desirable. G in the Ge ion implantation region 331
e is contained at a concentration of 1 × 10 ²¹ cm ⁻³ or more. next,
As shown in FIG. 38B, after the Ge deposition layer 334 and the cap layer 335 are deposited in layers, heat treatment is performed. The order of heat treatment and Ge layer / cap layer deposition may be reversed. By performing the heat treatment, the Ge ion-implanted layer 331 becomes Si _1-xy C _x Ge _{y as shown in FIG.}
This will be the layer 336.

Also in this example, the amorphous ion-implanted layer is heat-treated and re-crystallized to facilitate the formation of the 3C crystal structure and further reduce the ohmic contact resistance.

(Twentieth Embodiment) FIG. 39 is a process sectional view showing an example of a method for manufacturing an electrode structure according to a twentieth embodiment of the present invention.

As shown in FIG. 39A, the SiC substrate 3
By ion-implanting Ge and the dopant element into 01, an ion-implanted region 341 in an amorphous state is formed. Ge and dopant ions may be implanted simultaneously or separately. Ion implantation temperature is room temperature to 8
00 ° C is desirable. Ge is contained in the ion implantation region 341 at a concentration of 1 × 10 ²¹ cm ⁻³ or more. As the dopant element, one whose ion implantation region 341 has the same conductivity type as that of the SiC substrate 301 is used. SiC substrate 301 is n
Type, the dopant is a Group 5 element, specifically N,
P, As, Sb, Bi, V, Nb, and Ta are selected, and if the SiC substrate 301 is p-type, the dopant is a Group 3 or Group 2 element, specifically B, Al, Ga,
In, Tl, Zn, Cd, Hg, Sc, Y, Be, M
It shall be selected from g, Ca, Sr, Ba, and Ra.

The ion implantation region 341 is made amorphous so that the dopant concentration in the region 341 becomes Si.
The concentration is above the solid solution limit in the thermal equilibrium state in C. As a result, Si _1-xy C _x G formed in the next step
The doping concentration in the e _y layer 343 can be dramatically improved, and the ohmic contact resistance can be reduced.

After heat treatment, a cap layer 342 is deposited in layers as shown in FIG. 39 (c). The order of heat treatment and cap layer deposition may be reversed. By performing heat treatment, the ion-implanted layer 341 becomes Si _1-xy C _x Ge.
_{The y} layer 343 is formed. As the cap layer 342, a metal, an intermetallic compound, or the like similar to those described above may be used.

(Twenty-first Embodiment) FIG. 40 is a process sectional view showing an example of a method for manufacturing an electrode structure according to a twenty-first embodiment of the present invention.

As shown in FIG. 40A, the SiC substrate 3
By ion-implanting Ge and the dopant element into 01, an ion-implanted region 341 in an amorphous state is formed. Ion implantation conditions, dopant elements, etc. are the same as those in the case of the twentieth embodiment described above. The ion-implanted region 341 is made amorphous, so that the region 341 is formed.
The dopant concentration therein becomes a concentration above the solid solution limit in the thermal equilibrium state in SiC. As a result, the doping concentration in the Si _1-xy C _x Ge _y layer 346 formed in the next step can be dramatically improved, and the ohmic contact resistance can be reduced.

After heat treatment is performed to form a Si _1-xy C _x Ge _y layer 346 as shown in FIG.
As shown in (c), the Ge layer 344 and the cap layer 345.
Are deposited in layers. The order of heat treatment and deposition of the cap layer and the like may be reversed. Metal as the cap layer 342,
The same compounds as those shown above, such as an intermetallic compound, may be used. Further, it is desirable that the Ge layer 344 be doped to have the same conductivity type as the SiC substrate 301.

(Twenty-second Embodiment) FIGS. 41A to 41C are process sectional views showing an example of a method for manufacturing an electrode structure according to a twenty-second embodiment of the present invention.

As shown in FIG. 41A, the SiC substrate 3
After forming a mixture layer 352 of Ge and a dopant element on 01, Ge and a dopant element are ion-implanted to form an ion-implanted region 351 in an amorphous state, as shown in FIG. Ion implantation conditions, dopant elements, etc. are the same as those in the case of the twentieth embodiment described above. The ion implantation region 351 becomes amorphous, so that the concentration of the dopant in the region 351 becomes equal to or higher than the solid solution limit in the thermal equilibrium state in SiC. As a result, the Si _1-xy C _x Ge _y layer 35 formed in the next step is formed.
The doping concentration in No. 4 can be dramatically improved, and ohmic contact resistance can be reduced.

After heat treatment is performed to form a Si _1-xy C _x Ge _y layer 354 as shown in FIG. _41C , a cap layer 353 is deposited in layers. The order of heat treatment and cap layer deposition may be reversed. As the cap layer 353, a metal, an intermetallic compound, or the like similar to those described above may be used.

(Twenty-third Embodiment) FIG. 42 is a sectional view showing a method for manufacturing an electrode structure according to a twenty-third embodiment of the present invention.

As shown in FIG. 42A, the SiC substrate 3
42 (b) after depositing a poly-Si layer 361 on 01.
As shown in FIG. 6, by implanting Ge ions, an implantation region 362 in an amorphous state is formed. It is desirable that the ion implantation region 362 be doped to have the same conductivity type as the SiC substrate 301. The ion implantation temperature is preferably room temperature to 800 ° C. G is present in the ion implantation region 362.
e is contained at a concentration of 1 × 10 ²¹ cm ⁻³ or more.

As shown in FIG. 42C, heat treatment is performed to form the ion-implanted region 362 in the Si _{1-x- y} C _x Ge _y layer 36.
4, and the electrode 363 is further deposited thereon in layers.
There is no problem even if the order of heat treatment and electrode deposition is reversed. The electrode 363 may be a metal, an intermetallic compound, or the like, specifically, Ni, Pd, Pt, Cu, Ag, Au, Z.
n, Al, Ga, In, C, Si, Ge, Sn, Pb,
It is desirable to contain one or more elements selected from Ti, Zr, Hf, V, Nb, Ta, Cr, Mo and W.

(24th Embodiment) FIG. 43 is a cross-sectional view showing a method for manufacturing an electrode structure according to a 24th embodiment of the present invention.

As shown in FIG. 43 (a), the SiC substrate 3
43 (b) by ion-implanting Ge and the dopant element after depositing the poly-Si layer 371 on 01.
As shown in FIG.
Form 2. The ion implantation temperature is preferably room temperature to 800 ° C. Ge is added to the ion implantation region 371 at 1 × 10 ²¹ c.
It is contained at a concentration of m ^-3 or more. Ion implantation conditions, dopant elements, etc. are the same as those in the case of the twentieth embodiment described above.

As shown in FIG. 43C, heat treatment is performed to form the ion-implanted region 372 in the Si _{1-x- y} C _x Ge _y layer 37.
4, and the electrode 373 is further deposited thereon in layers.
There is no problem even if the order of heat treatment and electrode deposition is reversed. For the electrode 373, the same metal or the like as shown above can be used. Since the Si _1-xy C _x Ge _y layer 374 is heavily doped with impurities, the ohmic contact resistance can be reduced.

(Twenty-fifth Embodiment) FIG. 44 is a sectional view showing a method for manufacturing an electrode structure according to a twenty-fifth embodiment of the present invention.

As shown in FIG. 44A, the SiC substrate 3
01 and a mixture layer 381 of Si and Ge and a cap layer 38.
2 is deposited in layers and then heat-treated to obtain the structure shown in FIG.
As shown in FIG. 4B, the SiC substrate 301 and Si and G
The mixture layer 381 of e reacts to form the Si _1-xy C _x Ge _y layer 383. As the cap layer 382, the same metal or the like as shown above may be used.

(Twenty-sixth Embodiment) FIG. 45 is a sectional view showing a method for manufacturing an electrode structure according to a twenty-sixth embodiment of the present invention.

As shown in FIG. 45A, the SiC substrate 3
After a mixture layer 391 of Si and Ge is layered on 01, a dopant element is ion-implanted. After that, FIG.
After depositing the cap layer 393 as shown in (b), heat treatment is performed. By heat treatment, the SiC substrate 301 and the mixture layer 92 of Si and Ge in which the dopant element is ion-implanted
React to form a Si _1-xy C _x Ge _y layer 394. Since the Si _1-xy C _x Ge _y layer 394 is highly doped with impurities, the ohmic contact resistance can be reduced.

In the sixteenth to twenty-sixth embodiments described above, the heat treatment is performed in an inert gas atmosphere such as Ar at 500 ° C. to 1000 ° C., preferably 700 ° C. to 9 ° C.
It is preferably carried out at 00 ° C.

(Twenty-seventh Embodiment) FIG. 46 is a sectional view showing a structural example of a Schottky diode according to this embodiment. In this embodiment, Si is formed around the Schottky electrode.
When a guard ring of the opposite conductivity type to the C substrate is provided,
The ohmic contact having a sufficiently low resistance can be formed between the guard ring and the electrode.

In FIG. 46, 401 is a SiC substrate, 4
02 is a SiC epitaxial growth layer, 403 is a doping layer to be a guard ring, 404 is a back electrode, and 405 is a surface treatment layer (Si _1-xy C _x doped with impurities).
Ge _y layer), 406 is a surface electrode.

On the n-type SiC substrate 401, a light-doped n-type SiC epitaxial growth layer 402 (having a thickness of 10 μm) is formed.
A substrate on which m) was formed was prepared. SiC is so-called 4H
It has a type structure, and the orientation of the epitaxially grown surface is the so-called Si surface of the (001) surface.

After the substrate is washed,
An oxide film was formed at 1200 ° C. in an oxygen atmosphere. afterwards,
A silicon oxide film was further formed by atmospheric pressure CVD to form an oxide film with a total thickness of 1 μm. Then, this oxide film was patterned to form a pattern without an oxide film at a predetermined position. 1000 ° C with respect to the substrate on which this oxide film is formed
Then, boron ions were implanted at 10 ¹⁹ cm ^-3 . Then, annealing is performed at 1500 ° C. to activate the doped boron, and the p-type doping layer 4 is formed on the portion without the oxide film.
03 was formed. After removing the oxide film on the back surface, Ni was vapor-deposited as the back surface electrode 404 to a thickness of 1 μm and further annealed at 950 ° C. to ensure ohmic contact with the substrate on the back surface.

Next, a p-type doping layer 403 is formed by acid treatment.
After cleaning the surface, ion implantation of Ge is performed, as shown in FIG.
As shown in (enlarged view of FIG. 46A), the surface treatment layer 4
05 (boron-doped Si _1-xy C _x Ge _y
Layers) were formed. Ge is 1 × 1 in the surface treatment layer 405.
It is contained at a concentration of 0 ²¹ cm ^-3 or more. After that, all oxide films are removed, and Ti as the surface electrode 406 is 1 μm.
m was deposited and patterned. Further, annealing was performed at 400 ° C. to form a structure as shown in FIG.

In the sample prepared in this way, SiC
The epitaxial growth layer 402 and the surface electrode 406 were in Schottky contact, and the p-type doping layer serving as a guard ring and the surface electrode 406 were in ohmic contact by the action of the surface treatment layer 405. The contact resistance in the ohmic contact region was 2 × 10 ⁻⁴ Ωcm ² . This is G
The surface becomes amorphous by ion implantation of e,
This is because good ohmic properties were obtained even at low temperature annealing at about 400 ° C.

Before boron ion implantation, the exposed surface of the substrate is again oxidized to form a thin oxide film of about 50 nm, or Ge is deposited on the substrate surface to form a thin layer, and then the same as above. A sample in which Ge ion implantation was performed was also prepared. In this case, the contact resistance is 1 × 10 ^-4 Ωc
m ² , and the ohmic property was further improved.

Moreover, as the SiC substrate 401, p-type Si is used.
A sample using C and an n-type doping layer for the guard ring was also prepared. As the surface treatment layer 405, Ge or Si ion-implanted was used. The resistance in the ohmic portion was in the range of 10 ⁻⁵ Ωcm ² , and ohmic contact could be secured. It is considered that in the case where Si is ion-implanted, silicidation occurs between the electrodes and the ohmic property is easily obtained.

(Twenty-eighth Embodiment) FIG. 47 is a sectional view showing a structural example of a Schottky barrier diode according to a twenty-eighth embodiment of the present invention.

The n-type SiC epitaxial layer 501 is formed on the n-type SiC substrate 500, and the p-type SiC layer 502 is formed in a predetermined region on the SiC epitaxial layer 501, and is sandwiched between the p-type SiC layer 502. A Schottky electrode 503 is formed on the SiC epitaxial layer 501. The surfaces of the p-type SiC layer 502 and the Schottky electrode 503 are covered with polysilicon 504, and the ohmic electrode 505 is formed on the back surface of the n-type SiC substrate 500.

The SiC epitaxial layer 501 contains hydrogen at a predetermined concentration. Since SiC has a deep acceptor level and a donor level, carriers are often trapped in a deep level formed by a non-dopant impurity, which causes a problem that device characteristics deteriorate. By including hydrogen, it is possible to compensate for the deep level created by the non-dopant impurity, and the carrier concentration and carrier mobility are increased,
The electrical characteristics of the Schottky barrier diode can be improved.

If the p-type SiC layer 502 also contains hydrogen, the effect of inactivating the residual donor can be obtained, so that the carrier concentration of the p-type SiC is further increased and the leak current is reduced. You can also

SiC containing hydrogen can be produced by implanting dopant ions and hydrogen ions into the surface simultaneously or separately, or by mixing hydrogen during crystal growth. Hydrogen concentration is 1 × 10 ¹⁸ c
m ^-3 or less is preferable, and 1 × 10 ¹⁴ cm ^-3
The above is preferable.

(Twenty-ninth Embodiment) FIG. 48 is a sectional view showing a structural example of a Schottky barrier diode according to a twenty-ninth embodiment of the present invention.

An n-type SiC epitaxial layer 511 is formed on the n-type SiC substrate 510, and a silicon oxide film 512 is formed in a predetermined region on the SiC epitaxial layer 511. Si with the silicon oxide film 512 formed
The upper part of the C epitaxial layer 511 is the Schottky electrode 5.
An ohmic electrode 514 is formed on the back surface of the n-type SiC substrate 510, which is covered with 13.

The n-type SiC substrate 510 and the SiC epitaxial layer 511 contain a predetermined concentration of oxygen. SiC has many crystal defects caused by vacancies and the like, and the inclusion of oxygen can alleviate the defects.
The carrier concentration and carrier mobility increase, and the electrical characteristics of the Schottky barrier diode can be improved.

The SiC containing oxygen can be produced by implanting dopant ions and oxygen ions into the surface simultaneously or separately, or by mixing oxygen during crystal growth. Oxygen concentration is 1 × 10 ¹⁸ c
m ^-3 or less is preferable, and 1 × 10 ¹⁴ cm ^-3
The above is preferable.

In the 28th and 29th embodiments, the Schottky barrier diode has been described as an example.
Other Si such as rectifying element and switching element using C
It is also applicable to C semiconductor devices.

In addition, the SiC shown in each of the above-mentioned embodiments has S having all crystal structures such as 2H, 4H, 6H, and 3C.
iC is applicable.

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the invention.

[0148]

According to the present invention, in a semiconductor device using SiC, the resistance can be reduced by forming the electrode region into a predetermined structure. Further, by containing oxygen or hydrogen in SiC, it is possible to suppress a decrease in carrier concentration or carrier mobility. Therefore, according to the present invention, a high-performance semiconductor device can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a configuration according to a first embodiment of the present invention.

FIG. 2 is a diagram showing another example of the configuration according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an example of a configuration according to a second exemplary embodiment of the present invention.

FIG. 4 is a diagram showing an example of a configuration according to a third exemplary embodiment of the present invention.

FIG. 5 is a diagram showing an example of a manufacturing process according to the third embodiment of the present invention.

FIG. 6 is a view showing another example of the manufacturing process according to the third embodiment of the present invention.

FIG. 7 is a view showing another example of the manufacturing process according to the third embodiment of the present invention.

FIG. 8 is a diagram showing an example of a manufacturing process according to the fourth embodiment of the present invention.

FIG. 9 is a diagram showing an example of a configuration according to a fifth exemplary embodiment of the present invention.

FIG. 10 is a diagram showing an example of a manufacturing process according to the fifth embodiment of the present invention.

FIG. 11 is a diagram showing an example of a configuration according to a sixth exemplary embodiment of the present invention.

FIG. 12 is a diagram showing an example of a manufacturing process according to the sixth embodiment of the present invention.

FIG. 13 is a diagram showing another example of the configuration according to the sixth exemplary embodiment of the present invention.

FIG. 14 is a diagram showing an example of a configuration according to a seventh embodiment of the present invention.

FIG. 15 is a diagram showing an example of a manufacturing process according to the seventh embodiment of the present invention.

FIG. 16 is a diagram showing an example of a configuration according to an eighth exemplary embodiment of the present invention.

FIG. 17 is a diagram showing an example of a manufacturing process according to the eighth embodiment of the present invention.

FIG. 18 is a diagram showing another example of the configuration according to the eighth embodiment of the present invention.

FIG. 19 is a diagram showing an example of a configuration according to a ninth embodiment of the present invention.

FIG. 20 is a diagram showing an example of a manufacturing process according to the ninth embodiment of the present invention.

FIG. 21 is a diagram showing an example of a configuration according to a tenth exemplary embodiment of the present invention.

FIG. 22 is a view showing an example of a manufacturing process according to the tenth embodiment of the present invention.

FIG. 23 is a diagram showing another example of the configuration according to the tenth embodiment of the present invention.

FIG. 24 is a view showing another example of the manufacturing process according to the tenth embodiment of the present invention.

FIG. 25 is a diagram showing an example of a configuration according to an eleventh exemplary embodiment of the present invention.

FIG. 26 is a view showing an example of a manufacturing process according to the eleventh embodiment of the present invention.

FIG. 27 is a diagram showing an example of a configuration according to a twelfth exemplary embodiment of the present invention.

FIG. 28 is a diagram showing an example of a configuration according to a thirteenth embodiment of the present invention.

FIG. 29 is a diagram showing an example of a configuration according to a fourteenth exemplary embodiment of the present invention.

FIG. 30 is a diagram showing an example of a manufacturing process according to the fifteenth embodiment of the present invention.

FIG. 31 is a diagram showing an example of a configuration according to a sixteenth exemplary embodiment of the present invention.

FIG. 32 is a diagram showing another example of the configuration according to the sixteenth embodiment of the present invention.

FIG. 33 is a diagram showing another example of the configuration according to the sixteenth embodiment of the present invention.

FIG. 34 is a diagram showing an example of a configuration according to a seventeenth exemplary embodiment of the present invention.

FIG. 35 is a view showing an example of manufacturing process according to the eighteenth embodiment of the present invention.

FIG. 36 is a view showing another example of the manufacturing process according to the eighteenth embodiment of the present invention.

FIG. 37 is a view showing another example of the manufacturing process according to the eighteenth embodiment of the present invention.

FIG. 38 is a view showing an example of manufacturing process according to the nineteenth embodiment of the present invention.

FIG. 39 is a view showing an example of manufacturing process according to the twentieth embodiment of the present invention.

FIG. 40 is a view showing an example of manufacturing process according to the twenty-first embodiment of the present invention.

FIG. 41 is a view showing an example of manufacturing process according to the twenty-second embodiment of the present invention.

FIG. 42 is a view showing an example of manufacturing process according to the twenty-third embodiment of the present invention.

FIG. 43 is a view showing an example of a manufacturing process according to the twenty-fourth embodiment of the present invention.

FIG. 44 is a view showing an example of manufacturing process according to the twenty-fifth embodiment of the present invention.

FIG. 45 is a view showing an example of manufacturing process according to the twenty-sixth embodiment of the present invention.

FIG. 46 is a diagram showing an example of a configuration according to the 27th embodiment of the present invention.

FIG. 47 is a diagram showing an example of a configuration according to the twenty-eighth embodiment of the present invention.

FIG. 48 is a diagram showing another example of the configuration according to the twenty-eighth embodiment of the present invention.

[Explanation of symbols]

101, 130, 140 ... SiC substrate 102 ... Si _x C _1-x layers 103, 112 ... Metal layers 104, 121, 131, 141 ... First element layers 105, 122, 132, 142 ... First element carbide layer 106 ... Poly-Si layer 107 ... Doped poly-Si layers 108, 111, 155, 165 ... Amorphous region 109 ... Poly-SiC layer 110 ... Doped poly-Si layer 113 ... Carbide layer 120 ... Poly-SiC layers 123, 143 ... Second element layers 124, 134, 144 ... Second element silicide layer 125 ... First element, second element, first element carbide, second element silicide mixed layer 126, 136 ... First element, second element mixed layer 127, 137, 154, 163 ... Cap layer 133 ... Second element nitride layer 135 ... First element, second element nitride, first element carbide,
Second element silicide mixed layers 145, 152, 162 ... Third element high concentration layers 146, 166 ... Third element layer 151 ... First element, second element, third element, first element carbide, second element Mixed layer 153 of silicide, mixed layer 161 of first element, second element, and third element 161 ... Mixed layer 167 of third element, fourth element, fourth element carbide, and fourth element silicide ... Fourth element layer 201, 222 ... SiC-IGBT 202, 215, 223 ... Wiring material 203 ... Al wire 210 ... SiC-SBD 211, 251 ... SiC substrate 212 ... SiC epitaxial layer 213 ... Schottky electrode 214 ... Ohmic electrode 221 ... SiC-SBD 224 ... metal layer 225, 226 ... electrode 252 ... SiO ₂ film 253 and 254 ... electrode member 255 ... electrode 301 ... SiC substrate 302,322,333,336,343,3 6,3
54, 364, 374, 383, 394 ... Si _1-xy C
_x Ge _y layers 303, 323, 332, 335, 342, 345, 3
53 ... cap layer 304,334,344 ... Ge layer _{321 ... Si 1-xy C x} Ge y deposited layer 331,341,351,362,372,392 ... ion implanted region 352,381,391 ... mixture layer 361, 371 ... Poly-Si deposited layers 363, 373 ... Electrode 382 ... Cap layer, 393 401 ... SiC substrate 402 ... SiC epitaxial growth layer 403 ... Doping layer 404 ... Back surface electrode 405 ... Surface treatment layer (Si _1-xy C _x Ge _y layer) 406 Surface electrode 500, 510 ... n-type SiC substrate 501, 511 ... n-type SiC epitaxial layer 502 ... p-type SiC layer 503, 513 ... Schottky electrode 504 ... polysilicon layer 505, 514 ... ohmic electrode 512 ... silicon oxide film

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seisho Imai 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center, Ltd. (72) Hidetoshi Fujimoto Komukai-Toshiba, Kawasaki-shi, Kanagawa Machi No. 1 within Toshiba Research and Development Center Co., Ltd. (56) Reference JP 62-81764 (JP, A) JP 5-29250 (JP, A) JP 8-64800 (JP, A) JP Flat 8-139051 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/872 H01L 29/28 H01L 29/43

Claims (10)

(57) [Claims] 1. A semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region includes a Si-rich Si _x C _1-x layer. Characteristic semiconductor device. 2. A semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region has a Si-rich Si _x C _1-x layer and a negative enthalpy of carbide formation. A semiconductor device comprising a layer made of a carbide of the first element that the semiconductor device has. 3. A semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region is formed of a silicide of a second element having a negative silicide formation enthalpy. A layer composed of the second element on the layer, a layer composed of the carbide of the first element having a negative carbide formation enthalpy on the layer, and a layer composed of the first element on the layer. A semiconductor device having a structure. 4. A semiconductor device having an n-type SiC region and an electrode region formed on the n-type SiC region, wherein the electrode region is made of a first element having a negative carbide formation enthalpy. A layer made of a carbide, a layer made of a silicide of a second element having a negative silicide formation enthalpy, and a layer made of a nitride of the second element,
Alternatively, a region of the carbide of the first element having a negative value of the enthalpy of carbide formation, a region of the silicide of the second element having a negative value of the enthalpy of formation of the silicide, and a region of the nitride of the second element A semiconductor device comprising a mixed layer. 5. A semiconductor device having a p-type SiC region and an electrode region formed on the p-type SiC region, wherein the electrode region is formed of a first element having a negative carbide formation enthalpy. A layer made of a carbide, a layer made of a silicide of a second element having a negative silicide formation enthalpy, and 2
A SiC layer containing a third element of Group 3 or Group 3 as an impurity , or a region of a carbide of a first element having a negative carbide formation enthalpy and a negative silicide formation enthalpy A layer in which a silicide region of the second element having a value is mixed and a third element of the group 2 or 3 is not included.
A semiconductor device comprising a SiC layer contained as a pure substance . 6. A semiconductor device having a p-type SiC region and an electrode region formed on the p-type SiC region, wherein the electrode region has a negative enthalpy of carbide formation and negative enthalpy of formation of silicide. A layer in which a carbide region of the fourth element and a silicide region of the fourth element are mixed, and a SiC layer containing a third element of the second group or the third group as an impurity. Semiconductor device. 7. A semiconductor device having a SiC region, an electrode portion formed on the SiC region, and a wiring portion formed on the electrode portion, wherein the material used for the wiring portion is a predetermined metal made of silicon. And a semiconductor device containing carbon. 8. The semiconductor device according to claim 7, wherein the predetermined metal contains silicon and carbon at a concentration equal to or higher than a solid solution limit with respect to the metal. 9. A semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region has a Ge concentration of 10 ²¹ cm ⁻³ or more Si _1-xy C _x.
Ge _y layer (however, 0 <x ≦ 0.5, 0 <y ≦ 0.3)
A semiconductor device comprising: 10. A first-conductivity-type SiC region, and an electrode portion that is Schottky-bonded to the first-conductivity-type SiC region,
A semiconductor device having a second conductivity type SiC region sandwiched between the electrode part and the first conductivity type SiC region in a region corresponding to an outer peripheral portion of the electrode part, wherein The Ge concentration is 1 at the boundary between the two conductivity type SiC regions.
Si ²¹ _-xy C _x Ge _y layer of 0 ²¹ cm ^-3 or more (however, 0
<X ≦ 0.5, 0 <y ≦ 0.3) is formed.