JP2000101099A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device using SiC in which resistance is decreased in ohmic electrode region. SOLUTION: The semiconductor device has an SiC region 101 and an electrode region formed thereon wherein the electrode region includes an SixC1-x layer 102 (x>0.5) and a first element carbide layer 105 having negative value of carbide creation enthalpy. The electrode region includes an impurity doped SiC layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device using SiC.

[0002]

2. Description of the Related Art Conventionally, Ni has been widely used as an ohmic electrode of SiC used for a Schottky diode or the like. However, Ni reacts with silicon in SiC to form silicide, and there is a problem that excess carbon segregates on the electrode surface or the interface between SiC and the electrode, causing the ohmic electrode to have high resistance and deteriorate. Further, when carbon is deposited on the surface of the ohmic electrode, when the wiring portion is formed on the surface of the ohmic electrode, the electrode portion and the wiring portion are deteriorated and the resistance is increased.

Further, in a Schottky diode using SiC, a guard ring of a conductivity type opposite to that of the SiC substrate is provided around the Schottky electrode in order to obtain a withstand voltage at a reverse voltage. However, when forming a Schottky electrode for obtaining a Schottky junction and an electrode for a guard ring requiring ohmic contact with the same electrode material, it is not possible to obtain a sufficient ohmic contact even if a Schottky junction is obtained. There's a problem.

[0004] On the other hand, SiC often has a problem that the carrier concentration is lowered due to the trapping of carriers at deep levels created by impurities, and the carrier mobility is lowered due to a large number of crystal defects caused by vacancies and the like. Therefore, there is a problem that the electrical characteristics of the element are deteriorated.

[0005]

As described above, the semiconductor device using SiC has a problem that resistance in an ohmic electrode region or the like is increased due to deposition of carbon or the like. In addition, SiC has a problem that the carrier concentration and the carrier mobility are likely to be reduced due to traps and crystal defects.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. A first object of the present invention is to reduce the resistance in an ohmic electrode region or the like in a semiconductor device using SiC, and to improve the carrier concentration of SiC. Another object is to improve carrier mobility.

[0007]

According to the present invention, there is provided a semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region has x> 0.5.
characterized in that it is configured to include a _x C _1-x layer.

The Si _x C _{1 -x} layer where x> 0.5 is made of Si
The band gap is narrower than that of C (SiC simply described in this specification usually indicates Si _0.5 C _0.5 unless otherwise specified). Therefore, according to the present invention, by providing a Si _x C _1-x layer in which x> 0.5, when a metal layer or the like is formed thereon,
The energy barrier height at the semiconductor interface can be reduced, and the ohmic contact resistance can be reduced.

According to another aspect of the present invention, there is provided a semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region has a Si _x C _{1 -x} layer _satisfying x> 0.5 and a carbide. The enthalpy of formation includes a layer made of a carbide of the first element having a negative value.

In the present invention, since the carbide enthalpy of formation of the first element is a negative value, the carbon in the SiC region is
React with each other to form a carbide of the first element, and to form a Si _x C _1-x layer where x> 0.5.
The Si _x C _1-x layer, as in the previous invention, it is possible to reduce the ohmic contact resistance. Also, by the action of the first element having a negative value of the enthalpy of carbide formation,
Problems such as high resistance and deterioration of the electrode caused by the deposition of carbon can be prevented.

According to another aspect of the present invention, there is provided a semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region has a high impurity concentration.
It is characterized by comprising an iC layer.

According to the present invention, by providing a highly doped SiC layer, when a metal layer or the like is formed thereon, carriers can tunnel the SiC region / metal layer interface, and ohmic contact can be achieved. Resistance can be reduced. Note that the SiC layer here includes Si
Other _0.5 C _0.5 layer, Si _x C _1-x layer is x> 0.5 are also included.

According to another aspect of the present invention, there is provided a semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region comprises a first element carbide having a negative enthalpy of carbide formation. Or a layer composed of a silicide of a second element having a negative value of silicide formation enthalpy, or a carbide of a first element having a negative value of carbide formation enthalpy of negative value. It is characterized by comprising a layer in which a region and a region of silicide of the second element having a negative value of the enthalpy of silicide formation are mixed.

In the present invention, since the silicide formation enthalpy of the second element is a negative value, the silicon in the SiC region and the second
Reacts to form a silicide of the second element, and a good ohmic contact with the SiC region is obtained by the silicide of the second element. In addition, since the carbide enthalpy of formation of the first element is a negative value, the carbon in the SiC region reacts with the first element to easily form a carbide of the first element, and the carbon precipitates due to the formation of silicide. Therefore, it is possible to prevent problems such as high resistance and deterioration of the electrode caused by the above.

The present invention is also a semiconductor device having an n-type SiC region and an electrode region formed on the n-type SiC region, wherein the electrode region has a first enthalpy of carbide formation having a negative value. Or a layer composed of a silicide of the second element having a negative enthalpy of silicide formation and a layer composed of a nitride of the second element having a negative enthalpy of silicide formation. A layer in which a carbide region of the first element having a negative enthalpy of formation, a silicide region of the second element having a negative enthalpy of formation of silicide, and a nitride region of the second element are mixed. Is characterized by including.

In the present invention, as in the previous invention, good ohmic contact can be obtained by the silicide of the second element, and the formation of carbide of the first element can suppress carbon deposition. In addition to the effect, the action of the nitride of the second element prevents nitrogen, which is the n-type dopant of the n-type SiC region, from being extracted from the n-type SiC region, thereby preventing a decrease in doping concentration. The effect that the ohmic contact resistance can be reduced is obtained.

The present invention is also a semiconductor device having a p-type SiC region and an electrode region formed on the p-type SiC region, wherein the electrode region has a first enthalpy of carbide formation having a negative value. A layer composed of a carbide of a second element, a layer composed of a silicide of a second element having a silicide formation enthalpy of a negative value, and a layer containing a third element of Group 2 or Group 3, Alternatively, a layer in which a region of carbide of the first element having a negative value of enthalpy of carbide formation and a region of silicide of the second element having a negative value of enthalpy of silicide formation are mixed, and a group 2 or 3 group It is characterized by including a layer containing a third element.

In the present invention, as in the previous invention, a good ohmic contact can be obtained by the silicide of the second element, and the formation of carbide of the first element can suppress the precipitation of carbon. In addition to the effect, a layer containing a third element (normally, SiC doped with a third element as an impurity (Si _0.5 C _0.5 or Si _{x with} x> 0.5)
C _1-x ) can be tunneled by the carrier, so that the effect of reducing ohmic contact resistance can be obtained.

According to another aspect of the present invention, there is provided a semiconductor device having a p-type SiC region and an electrode region formed on the p-type SiC region, wherein the electrode region has a negative carbide enthalpy and a low silicide enthalpy. Or a layer made of a carbide of a fourth element having a value, a layer made of a silicide of the fourth element, and a layer containing a third element belonging to Group 2 or Group 3, or an enthalpy of forming a carbide. A layer in which a region of carbide of the fourth element and a region of silicide of the fourth element having a negative value of the enthalpy of silicide formation are mixed;
It is characterized by including a layer containing a third element of Group 3 or Group 3.

In the present invention, the carbide enthalpy of formation of the fourth element and the enthalpy of formation of silicide of the fourth element are both negative, and the first element and the second element in the above invention are the same element. Therefore, similarly to the above invention, a good ohmic contact is obtained by the silicide of the fourth element, and the effect of suppressing the precipitation of carbon by forming the carbide of the fourth element is further improved. The effect that the ohmic contact resistance can be reduced by tunneling the carrier to the layer containing the third element is obtained.

Further, the present invention is a semiconductor device having a SiC region, an electrode portion formed on the SiC region, and a wiring portion formed on the electrode portion, wherein a material used for the wiring portion is a predetermined material. It is characterized in that the metal contains silicon and carbon.

Preferably, the predetermined metal contains silicon and carbon at a concentration equal to or higher than the solid solution limit for the metal.

According to the present invention, since the metal of the wiring portion contains carbon in addition to silicon, deterioration and increase in resistance of the electrode portion and the wiring portion caused by the deposition of carbon from the SiC region are prevented. Can be prevented.

The present invention is also a semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region has a Si _1-xy C having a Ge concentration of 10 ²¹ cm ⁻³ or more. It is characterized by comprising an _x Ge _y layer.

The band gap of Si _1-xy C _x Ge _y is narrower than that of SiC. Therefore, according to the present invention, S
By providing the i _1-xy C _x Ge _y layer, when a metal layer or the like is formed thereon, the energy barrier height at the metal / semiconductor interface can be reduced, and the ohmic contact resistance can be reduced. Si _1-xy C _x Ge
_{The y} layer may be doped with an element serving as an impurity. By introducing Ge and impurities in an amorphous state by ion implantation or the like, the doping concentration of the impurities can be drastically improved, and the resistance can be further reduced. Note that the range of x is preferably 0 <x ≦ 0.5, and the range of y is preferably 0 <y ≦ 0.3.

The present invention also provides a first conductivity type SiC region, an electrode portion Schottky-bonded to the first conductivity type SiC region, and an electrode portion in a region corresponding to an outer peripheral portion of the electrode portion. A semiconductor device having a second conductivity type SiC region sandwiched between the first conductivity type SiC region, wherein a Ge concentration is 10 ^{21 at} a boundary portion between the electrode portion and the second conductivity type SiC region. cm ^-3 or more Si _1-xy C _x Ge _y
It is characterized in that a layer is formed.

According to the present invention, a predetermined Ge concentration of S is formed at the boundary between the electrode portion and the second conductivity type SiC region serving as a guard ring.
i _1-xy C _x Ge _y layer (0 <x ≦ 0.5, 0 <y ≦ 0.
3 is preferably formed, so that an ohmic contact with sufficiently low resistance can be obtained between the electrode portion and the guard ring.

Further, the semiconductor device according to the present invention is characterized in that it has an SiC region containing oxygen or hydrogen of 1 × 10 ¹⁸ cm ⁻³ or less. The oxygen concentration is also 1
It is preferably not more than × 10 ¹⁸ cm ⁻³ .

According to the present invention, the inclusion of hydrogen in SiC can compensate for the deep level created by the non-dopant impurity, and the inclusion of oxygen in SiC can reduce crystal defects. Carrier concentration and carrier mobility can be increased.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view showing an example of an electrode structure according to a first embodiment of the present invention.
As shown in FIG. 1, a Si _x C _{1 -x}
The layer 102 and the metal layer 103 are formed in layers.

In the Si _x C _{1 -x} layer, X> 0.5, and the band cap is narrower than that of SiC. Further, the ratio of Si continuously increases from the SiC / Si _x C _{1 -x} interface toward the metal layer, and the band gap decreases continuously toward the metal layer. Therefore, the energy barrier at the semiconductor / metal interface is low,
Ohmic contact resistance can be reduced. Also, the SiC substrate 1
By forming the Si _x C _{1 -x} layer 102 on the upper layer 01, it is also possible to improve the adhesion to the upper layer side.

FIG. 2 is a sectional view showing another example of the electrode structure according to the present embodiment. The basic configuration of the electrode structure is
This is the same as the example shown in FIG. The difference from the example of FIG.
Si _x C _1-x layer 102 is a point that are buried in the SiC substrate 101. By the method of preparing of the electrode, the position of the Si _x C _1-x layer 102 as in this embodiment is changed, but FIG. 1
The same effect as that of the example can be obtained.

(Second Embodiment) FIG. 3 is a sectional view showing an example of an electrode structure according to a second embodiment of the present invention.
As shown in FIG. 3, a poly-SiC layer 120 and a metal layer 103 are formed in layers on a SiC substrate 101.

The poly SiC layer 120 is formed on the SiC substrate 101.
The impurity is doped so as to have the same conductivity type as that of the poly-SiC layer 120, and the doping concentration of the poly-SiC layer 120 is 10 ¹⁸ cm.
^-3 or more. Highly doped poly S
By sandwiching the iC layer 120 between the SiC substrate 101 and the metal layer 103, carriers tunnel the interface between the SiC substrate 101 and the metal layer 103, so that ohmic contact resistance can be reduced. Further, the SiC substrate 10
By forming the poly-SiC layer 120 on the substrate 1, it is possible to improve the adhesion to the upper layer.

(Third Embodiment) FIG. 4 is a sectional view showing an example of an electrode structure according to a third embodiment of the present invention.
As shown in FIG. 4, a Si _x C _1-x
The layer 102, the first element carbide layer 105, and the first element layer (metal layer) 104 are formed in layers.

As the first element, an element having a negative value of enthalpy of carbide formation is used. Specifically, Ta, Zr, N
b, Ti, Th, Be, V, Cr, Al, B, Ce,
It is selected from W, Mn, Ca and the like.

[0038] Similarly to the first embodiment, Si _x C _1-x layer has a X> 0.5, the proportion of Si increases from SiC / Si _x C _1-x interface toward the upper side Therefore, ohmic contact resistance can be reduced. In addition, SiC
It is possible to improve the adhesiveness to form a Si _x C _1-x layer 102 on the substrate 101.

FIG. 5 is a process sectional view showing an example of a manufacturing method for manufacturing an electrode structure having the structure shown in FIG.

As shown in FIG. 5A, the SiC substrate 10
After the first element layer 104 is formed in a layer on the substrate 1, heat treatment is performed to produce a structure as shown in FIG. Since the first element is an element having a negative enthalpy of carbide formation, it reacts with carbon in the SiC substrate 101 to form the first element carbide layer 105. At this time, the SiC substrate 101
Since carbon escapes from the surface, the Si _x C _{1 -x} layer 102 which is a Si-rich region is formed. As described above, in the present example, since the carbon in the SiC substrate 101 reacts with the first element, the problem that carbon is deposited does not occur.

FIG. 6 is a process sectional view showing another example of the manufacturing method for manufacturing the electrode structure having the structure shown in FIG.

As shown in FIG. 6A, the SiC substrate 10
After the poly-Si layer 106 and the first element layer 104 are formed in layers on the substrate 1, heat treatment is performed. Since the first element is an element having a negative carbide formation enthalpy, the SiC substrate 10
The first element carbide layer 105 is formed as shown in FIG. Further, the SiC substrate 10
1 also reacts with the poly-Si layer 106,
Since carbon exit from C substrate 101 surface, Si-rich Si _x C _1-x layer 102 is formed. In addition, poly Si
If the impurity is doped at a high concentration so that the layer 106 has the same conductivity type as the SiC substrate 101, the ohmic contact resistance can be further reduced.

FIG. 7 is a process sectional view showing another example of the manufacturing method for manufacturing the electrode structure having the structure shown in FIG.

As shown in FIG. 7A, the SiC substrate 10
1, a poly-Si layer 106 is formed in a layer shape,
A dopant is ion-implanted on the layer 106. The SiC substrate 101 and the poly-Si layer 106 have the same conductivity type, and the dopant element to be ion-implanted is a Group 5 element if the SiC substrate 101 is n-type, specifically, N, P, As, Sb, B
i or at least one element selected from i.
If 1 is a p-type, a Group 3 element or a Group 2 element, specifically, B, Al, Ga, In, Tl, Zn, Cd, Hg, S
It is one or more elements selected from c, Y, Be, Mg, Ca, Sr, Ba, and Ra. By ion implantation, FIG.
As shown in (b), the poly-Si layer 106 becomes a doped poly-Si layer 107, and the SiC substrate 101 under the doped poly-Si layer 107 is also ion-implanted to become an amorphous region 108.

Next, as shown in FIG. 7C, a first element layer 104 is formed on the doped poly-Si layer 107, and heat treatment is performed. Since the first element is an element having a negative enthalpy of carbide formation, as shown in FIG.
An element carbide layer 105 is formed, and the doped poly Si layer 1
07 also reacts with carbon to form a Si _x C _1-x layer 102. Amorphous region is recrystallized by heat treatment, but since there are characteristics of SiC as prone to 3C-SiC crystal structure when amorphized SiC is recrystallized by heat treatment, the Si _x C _1-x layer 102 crystal The structure has a higher 3C ratio. 3C-SiC is 4H-S
Since the band gap is narrower than iC or 6H—SiC, ohmic contact resistance can be further reduced.

(Fourth Embodiment) An eighth embodiment is a process sectional view showing an example of an electrode structure according to a fourth embodiment of the present invention and a method for manufacturing the same.

As shown in FIG. 8A, the SiC substrate 10
1, a poly SiC layer 109 is formed in a layer shape,
A dopant is ion-implanted on the iC layer 109. SiC
The substrate 101 and the poly SiC layer 109 are of the same conductivity type.
The dopant elements to be ion-implanted are the same as those described in FIG. As shown in FIG.
As shown in (b), the poly SiC layer 109 becomes a doped poly SiC layer 110, and the doped poly SiC layer 110
Is also implanted into the amorphous region 111 by ion implantation.

Next, as shown in FIG. 8C, after a metal layer 112 is laminated on the doped poly-SiC layer 110, a heat treatment is performed. Heat treatment before laminating the metal layer 112,
After that, the metal layer 112 may be stacked. This allows
As shown in FIG. 8D, a carbide layer 113 is formed,
Doped poly SiC layer 110 was recrystallized Si _x C
_{A 1-x} layer 102 is formed. Amorphized SiC
Has a characteristic of SiC that tends to have a 3C—SiC crystal structure when recrystallized by heat treatment.
The crystal structure of _x C _1-x layer 102 becomes large proportion of 3C.
Therefore, the ohmic contact resistance can be reduced for the same reason as described with reference to FIG.

(Fifth Embodiment) FIG. 9 is a sectional view showing an example of an electrode structure according to a fifth embodiment of the present invention.
As shown in FIG. 9, a second element silicide layer 124, a second element layer 123, and a first element carbide layer 12 are formed on a SiC substrate 101.
2 and the first element layer 121 are formed in layers.

The first element is an element having a negative value of the enthalpy of carbide formation, specifically, Ta, Zr, N
b, Ti, Th, Be, V, Cr, Al, B, Ce,
It is selected from W, Mn, Ca and the like. The second element is an element having a negative silicide formation enthalpy, and specifically, Ca, Ti, Ni, Th, Ta, Co, Mo,
It is selected from Cr, Mn, Nb, Fe, Re and the like.

FIG. 10 is a process sectional view showing an example of a method for manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 10A, the second element layer 123 and the first element layer 121 are formed in a layer shape, and heat treatment is performed to thereby form the second element silicide layer 12 as shown in FIG.
4 and the first element carbide layer 122 are formed.

It is conventionally known that an ohmic contact can be obtained by forming a silicide on SiC. However, since the formation of a carbide layer does not cause segregation of excess carbon due to silicide generation, an ohmic contact is obtained. The resistance of the electrode can be further reduced.

(Sixth Embodiment) FIG. 11 shows a sixth embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating an example of an electrode structure according to the embodiment. As shown in FIG. 11, a mixed layer 125 in which a region made of the first element, a region made of the second element, a region made of the first element carbide, and a region made of the second element silicide are formed on the SiC substrate 101 is formed. Have been.

The first element is an element having a negative enthalpy of carbide formation, and the same element as in the fifth embodiment is used. The second element is an element having a negative silicide formation enthalpy, and the same element as in the fifth embodiment is used.

FIG. 12 is a process sectional view showing an example of a method for manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 12A, a mixed layer 126 in which the first element and the second element are mixed is formed on the SiC substrate 101,
By performing the heat treatment, a mixed layer 125 is formed as shown in FIG.

In this embodiment, the silicide in the mixed layer 125 can provide ohmic contact with SiC,
By forming carbides therein, there is no segregation of surplus carbon due to silicide generation, so that it is possible to further reduce the resistance of the ohmic electrode. Further, in the present embodiment, as compared with the fifth embodiment, only one layer is deposited, so that the manufacturing method is simplified.

FIG. 13 is a sectional view showing another example of the electrode structure according to this embodiment. That is, the cap layer 127 is formed on the mixed layer 125. Cap layer 12
It is desirable that the material of No. 7 is selected from metal elements that do not easily react with oxygen, such as Pt, Au, Pd, and Ni. By forming the cap layer 127, it is possible to prevent the electrode from deteriorating by reacting with oxygen in the air.

(Seventh Embodiment) FIG. 14 shows a seventh embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating an example of an electrode structure according to the embodiment. As shown in FIG. 14, on an n-type SiC substrate 130,
A second element silicide layer 134, a second element nitride layer 133, a first element carbide layer 132, and a first element layer 131 are formed.

The first element is an element having a negative value of the enthalpy of carbide formation, and the same element as in the fifth embodiment is used. The second element is an element having a negative silicide formation enthalpy, and the same element as in the fifth embodiment is used.

FIG. 15 is a process sectional view showing an example of a method for manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 15A, the n-type SiC substrate 130
A second element nitride layer 133 and a first element layer 131 are formed in layers on the upper layer, and a heat treatment is performed to form a second element silicide layer 134 and a first element carbide, as shown in FIG. Layer 132 is formed.

Since the silicide is formed on the SiC, ohmic contact is obtained, and the formation of the carbide layer eliminates the segregation of excess carbon due to silicide generation.
The resistance of the ohmic electrode can be further reduced. Since the second element nitride is used, the n-type S
Nitrogen, which is a dopant in iC, is not extracted from SiC, and a high concentration can be maintained, so that the ohmic contact resistance can be further reduced.

(Eighth Embodiment) FIG. 16 shows an eighth embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating an example of an electrode structure according to the embodiment. As shown in FIG. 16, a region composed of the first element, a region composed of the second element nitride, a region composed of the first element carbide, and a region composed of the second element silicide are mixed on the n-type SiC substrate 130. A layer 135 has been formed.

The first element is an element having a negative value of the enthalpy of carbide formation, and the same element as in the fifth embodiment is used. The second element is an element having a negative silicide formation enthalpy, and the same element as in the fifth embodiment is used.

FIG. 17 is a process sectional view showing an example of a method for manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 17A, the n-type SiC substrate 130
Mixed layer 136 in which the first element and the second element nitride are mixed
Is formed and heat treatment is performed to form a mixed layer 135 as shown in FIG.

In this embodiment, the silicide in the mixed layer 135 can provide ohmic contact with SiC,
By forming carbides therein, there is no segregation of surplus carbon due to silicide generation, so that it is possible to further reduce the resistance of the ohmic electrode. Further, the nitrogen as the dopant in the n-type SiC is converted into SiC by the second element nitride.
Without being pulled out from the substrate, the ohmic contact resistance can be further reduced. Further, in the present embodiment, as compared with the seventh embodiment, only one layer is deposited, so that the manufacturing method is simplified.

FIG. 18 is a sectional view showing another example of the electrode structure according to this embodiment. That is, the cap layer 137 is formed on the mixed layer 135 shown in FIG.
The effect of the material of the cap layer 137 and the cap layer is as follows.
This is the same as the example of the cap layer shown in FIG.

(Ninth Embodiment) FIG. 19 shows a ninth embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating an example of an electrode structure according to the embodiment. As shown in FIG. 19, on a p-type SiC substrate 140,
Third element high concentration layer 145, second element silicide layer 144, second element layer 14 in which SiC is heavily doped with impurities
3. A first element carbide layer 142 and a first element layer 141 are formed.

The first element is an element having a negative enthalpy of carbide formation, and the same element as in the fifth embodiment is used. The second element is an element having a negative silicide formation enthalpy, and the same element as in the fifth embodiment is used. As the third element, a Group 3 element or a Group 2 element is used. Specifically, B, Al, Ga, In, T
1, Sc, Y, Be, Mg, Ca, Sr, Ba, Ra,
It is selected from Zn, Cd, Hg and the like.

FIG. 20 is a process sectional view showing an example of a method for manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 20A, the p-type SiC substrate 140
The third element layer 146, the second element layer 143, and the first element layer 141 form a layer thereon, and are subjected to heat treatment, as shown in FIG. A two-element silicide layer 144 and a first-element carbide layer 142 are formed.

In this embodiment, since the high-concentration layer 145 containing the third element as a dopant is formed, and the high-concentration layer 145 is tunneled by carriers, the ohmic contact resistance can be reduced.

(Tenth Embodiment) FIG. 21 is a sectional view showing an example of an electrode structure according to a tenth embodiment of the present invention. As shown in FIG. 21, on a p-type SiC substrate 140, a third element high concentration layer 152 in which SiC is doped with a high concentration of impurities, a region composed of the first element, a region composed of the second element, A mixed layer 151 in which a region made of an element, a region made of one element carbide, and a region made of a second element silicide are formed in a layered manner. As the first, second and third elements, the same elements as in the ninth embodiment are used.

FIG. 22 is a process sectional view showing an example of a method for manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 22A, the p-type SiC substrate 140
By forming a mixed layer 153 in which the first element, the second element, and the third element are mixed, and performing a heat treatment thereon, FIG.
As shown in (b), a third element high concentration layer 152 in which SiC is heavily doped with impurities and a mixed layer 151 are formed.

Also in this example, the ohmic contact resistance can be reduced as in the ninth embodiment by forming the high concentration layer 152 containing the third element as a dopant.

FIG. 23 is a sectional view showing another example of the electrode structure according to the present embodiment. That is, the cap layer 154 is formed on the mixed layer 151 shown in FIG.
The effect of the material of the cap layer 154 and the effect of the cap layer are as follows.
This is the same as the example of the cap layer shown in FIG.

FIG. 24 is a process sectional view showing an example of a method for manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 24A, the second element and the third element are ion-implanted on the p-type SiC substrate 140, and FIG.
An amorphous region 155 is formed as shown in FIG. Subsequently, as shown in FIG. 24C, a mixed layer of the first element, the second element, and the third element is formed, and a heat treatment is further performed.
A mixed layer 151 is formed as shown in FIG. Further, by laminating the cap layer 154 thereon,
The electrode is prevented from reacting with oxygen in the air and being deteriorated. As shown in FIG. 24A, when ion implantation of the second element and the third element is performed simultaneously, the third element becomes p-type as a dopant.
It can be promoted to be introduced into the mold-SiC 140, and the ohmic contact resistance can be further reduced.

(Eleventh Embodiment) FIG. 25 is a sectional view showing an example of an electrode structure according to an eleventh embodiment of the present invention. As shown in FIG. 25, on a p-type SiC substrate 140, a third element high concentration layer 162 in which SiC is doped with a high concentration of impurities, a region made of a third element, a region made of a fourth element, A mixed layer 161 in which a region made of elemental carbide and a region made of the fourth element silicide are mixed is formed in a layer shape, and a cap layer 163 is formed.

The fourth element is an element in which both the enthalpy of forming carbide and the enthalpy of forming silicide have negative values, and specifically, Ta, Nb, Ti, Th, Cr, Mn,
It is selected from Ca and the like. As the third element, a Group 3 element or a Group 2 element is used, which is specifically the same as that described above. Also in this example, the ohmic contact resistance can be reduced by forming the high concentration layer 162 containing the third element as a dopant.

FIG. 26 is a process sectional view showing an example of a method for manufacturing an electrode structure having the structure shown in FIG. As shown in FIG. 26A, the fourth element and the third element are ion-implanted on the p-type SiC substrate 140, and FIG.
An amorphous region 165 is formed as shown in FIG. Subsequently, as shown in FIG. 26C, a third element layer 166 and a fourth element layer 167 are formed, and heat treatment is further performed to form a mixed layer 161 as shown in FIG. Further, by laminating the cap layer 163 thereon, the electrode is prevented from deteriorating by reacting with oxygen in the air.

In the first to eleventh embodiments described above, the heat treatment is performed at 500 ° C. to 1000 ° C., preferably 700 ° C. to 90 ° C. in an inert gas atmosphere such as Ar.
It is preferably performed at 0 ° C.

(Twelfth Embodiment) FIG. 27 is a sectional view of a semiconductor device according to a twelfth embodiment of the present invention.

As shown in FIG. 27, IG using SiC
Al-Si-C wiring material 2 on electrode 201a of BT201
02 is formed, and the Al—Si—C wiring material 20 is formed.
2, an Al wire 203 is bonded. A
In the 1-Si-C wiring member 202, Si having a solid solution limit or more and C having a solid solution limit or more are dissolved in Al. S in Al
It is desirable that the i concentration is about 1.5% and the C concentration is about 0.7%.

When an Al—Si alloy, which is usually used as a wiring material for Si, is used for SiC, there is a problem that carbon is extracted from SiC. In this example, S
By using Al-Si-C as described above as a wiring material formed on an iC device, deterioration of electrodes and wiring materials caused by deposition of carbon in Si is prevented, and resistance of electrode portions and wiring portions is reduced. Can be reduced.

(Thirteenth Embodiment) FIG. 28 shows a thirteenth embodiment of the present invention.
FIG. 13 is a sectional view of a semiconductor device according to a third embodiment.

As shown in FIG. 28, SiC epitaxial layer 212 and Schottky electrode 2
13 is formed, and an ohmic electrode 214 is formed on the back surface of the SiC substrate 211, thereby forming the SiC-SBD.
(Schottky barrier diode) 210 is formed. On the Schottky electrode 213 and the ohmic electrode 214 of the SiC-SBD 210, an Al-Si-C wiring material 215 in which Si and C having a solid solution higher than the solid solution limit are dissolved in Al is formed. The effect of the Al-Si-C wiring material 215 is the same as the effect of the previous embodiment. By using Al-Si-C as the wiring material, the electrode and the wiring material caused by the precipitation of carbon in Si are used. Can be prevented, and the resistance of the electrode portion and the wiring portion can be reduced.

(Fourteenth Embodiment) FIG. 29 is a top view and a sectional view of a semiconductor device according to a fourteenth embodiment of the present invention.

As shown in FIG. 29A, SiC-IG
The BT 222 and the SiC-SBD 221 are combined and arranged in the same package. As shown in FIG. 29B, the SiC-IGBT 222 and the SiC-SBD 221
Al-Si-C wiring member 223 is formed on the main surface electrode. An electrode 225 (using Cu or the like) is formed on the Al-Si-C wiring member 223 via a metal layer 224 (using Mo or the like). In addition, SiC-IGBT
222 and the electrode 226 on the back side of the SiC-SBD 221.
(Using Cu or the like) is formed. Also in this example, the same effect as described above can be obtained by the Al-Si-C wiring member 223.

In the twelfth to fourteenth embodiments, Si
The C-IGBT and SiC-SBD have been described as examples, but the present invention is not limited thereto, and the above-described configuration can be applied to other semiconductor devices such as a switching element and a rectifying element using SiC. It is possible.

(Fifteenth Embodiment) FIG. 30 is a process sectional view showing a method for manufacturing a semiconductor device according to a fifteenth embodiment of the present invention.

First, as shown in FIG.
The entire substrate 251 is covered with a SiO ₂ film 252. Then, S
The SiO ₂ film 252 is removed only on the back surface side of the iC substrate 251, and further, as shown in FIG.
Is deposited. However, when the electrode material 253 is an ohmic electrode, a high-temperature heat treatment is required to obtain a low-resistance ohmic contact at the SiC / electrode interface. On the other hand, FIG.
Since the electrode 255 formed on the surface of the SiC substrate 251 cannot withstand the high-temperature heat treatment in the step (d), the electrode 255 must be formed after the formation of the electrode material 253 and the high-temperature heat treatment are completed. However, the electrode 255
In order to perform the formation of S, in the step of FIG.
The SiO ₂ film 252 remaining on the iC substrate 251 must be removed. To remove the SiO ₂ film 252, an acid such as HF is used. At this time, the electrode material 253 may be eroded by the acid. Therefore, the electrode material 254 is formed on the electrode material 253 by using a metal that is insoluble in acid to prevent the electrode material 253 from being eroded by the acid.

As the acid-resistant electrode material 254, 4A group,
Ti, Zr, Hf, V, N which are 5A group and 6A group elements
At least one metal selected from b, Ta, Cr, Mo, and W is used.

(Sixteenth Embodiment) FIG. 31 is a sectional view showing an example of an electrode structure according to a sixteenth embodiment of the present invention. As shown in FIG. 31, SiC substrate 301
_{A 1-xy} C _x Ge _y layer 302 and a cap layer 303 are formed in layers. x is 0 ≦ x ≦ 0.5, y is 0 ≦ y ≦
0.3, and the Ge concentration is 10 ²¹ cm ⁻³ or more.

The cap layer 303 includes a metal, an intermetallic compound, etc., specifically, Ni, Pd, Pt, Cu, Ag, A
u, Zn, Al, Ga, In, C, Si, Ge, Sn,
Pb, Ti, Zr, Hf, V, Nb, Ta, Cr, M
It is desirable to use one containing one or more elements selected from o and W.

[0093] Si _1-xy C _x Ge _y is narrower band gap compared to SiC, Si _1-xy C _x between the cap layer 303 having a SiC substrate 301 and the metallic conductive
By interposing the Ge _y layer 302, it is possible to reduce the metal / semiconductor interface barrier can reduce the ohmic contact resistance. Also, Si _1-xy C _x G
If the _ey layer 302 is doped with the same conductivity type as the SiC substrate 301, an ohmic electrode with even lower contact resistance can be obtained.

FIG. 32 is a sectional view showing another example of the electrode structure according to the present embodiment. The basic structure of the electrode structure is the same as the example shown in FIG. The difference from the example of FIG. 31 is that a part of the Si _1-xy C _x Ge _y layer 302 is SiC.
This is a point buried in the substrate 301. Although the position of the Si _1-xy C _x Ge _y layer 302 may change depending on the method of manufacturing the electrode as in this example, the same effect as in the example of FIG. 31 can be obtained.

FIG. 33 is a sectional view showing another example of the electrode structure according to the present embodiment. The basic structure of the electrode structure is the same as the example shown in FIG. The difference from the example of FIG. 31 is that the entire Si _{1 -xy} C _x Ge _y layer 302 is buried in the SiC substrate 301. Depending on the manufacturing method of the electrode, the Si _1-xy C _x Ge _y layer 302 as in this example is used.
May be changed, but the same effect as in the example of FIG. 31 can be obtained.

(Seventeenth Embodiment) FIG. 34 is a sectional view showing an example of an electrode structure according to a seventeenth embodiment of the present invention. This embodiment is different from the sixteenth embodiment in that
The point is that the Ge layer 304 is formed in a layer on the i _1-xy C _x Ge _y layer 302. In this example, the SiC substrate 301
Si _1-xy C _x with a narrower band gap than SiC
Ge _y layer 302 is formed, further Si _1-xy thereon
Since the Ge layer 304 having a narrower band gap than C _x Ge _y is formed, the barrier at the metal / semiconductor interface can be further reduced, and the ohmic contact resistance can be further reduced.

(Eighteenth Embodiment) FIG. 35 is a process sectional view showing an example of a method for manufacturing an electrode structure having the structure shown in the sixteenth embodiment.

As shown in FIG. 35A, the SiC substrate 3
After depositing a Si _1-xy C _x Ge _y layer 321 on
By performing the heat treatment, the SiC substrate 301 and the Si _1-xy C _x Ge _y layer 322 are formed as shown in FIG.
To reduce the discontinuity. Thereafter, as shown in FIG. 35 (c), the Si _1-xy C _x Ge _y layer 32
2, a cap layer 323 is deposited.

FIG. 36 is a process sectional view showing another example of a method of manufacturing an electrode structure having the structure as shown in the sixteenth embodiment.

As shown in FIG. 36A, the SiC substrate 3
01 and a cap layer 3 on the Si _1-xy C _x Ge _y layer 321
After the layers 23 are deposited in layers, a heat treatment is performed to obtain a structure as shown in FIG.

FIG. 37 is a process sectional view showing another example of a method for manufacturing an electrode structure having the structure as shown in the sixteenth embodiment.

As shown in FIG. 37A, the SiC substrate 3
Ge is accelerated to 50 at an accelerating voltage of 50 keV and a dose of 3 × 10 ¹⁶
Ions are implanted at cm ⁻² to form an amorphous Ge ion implanted region 331. Ion implantation temperature from room temperature to 8
00 ° C is desirable. In the Ge ion implantation region 331, G
e is contained at a concentration of 1 × 10 ²¹ cm ⁻³ or more. next,
As shown in FIG. 37B, after depositing the cap layer 332, heat treatment is performed. The order of the heat treatment and the cap layer deposition may be reversed. By performing the heat treatment, FIG.
As shown in (c), the Ge ion implanted layer 331 is Si
It becomes the _1-xy C _x Ge _y layer 333.

It is known that, when an amorphous ion-implanted layer is recrystallized by heat treatment, it tends to have a 3C crystal structure. Since the 3C crystal structure has a narrower band gap than the 4H and 6H crystal structures, the Si _1-xy C _x Ge _y layer
With the C crystal structure, the ohmic contact resistance can be further reduced. In addition, by adjusting the power and dose during Ge ion implantation, the Ge concentration, the implantation region, and the ohmic characteristics can be freely controlled.

(Nineteenth Embodiment) FIG. 38 is a process sectional view showing an example of a method for manufacturing an electrode structure having the structure shown in the seventeenth embodiment.

As shown in FIG. 38A, the SiC substrate 3
Ge is accelerated to 50 at an accelerating voltage of 50 keV and a dose of 3 × 10 ¹⁶
Ions are implanted at cm ⁻² to form an amorphous Ge ion implanted region 331. Ion implantation temperature from room temperature to 8
00 ° C is desirable. In the Ge ion implantation region 331, G
e is contained at a concentration of 1 × 10 ²¹ cm ⁻³ or more. next,
As shown in FIG. 38B, a heat treatment is performed after the Ge deposition layer 334 and the cap layer 335 are deposited in layers. The order of the heat treatment and the deposition of the Ge layer and the cap layer may be reversed. By performing the heat treatment, the Ge ion implanted layer 331 becomes Si _1-xy C _x Ge _{y as shown in FIG.}
The layer 336 is formed.

Also in this example, by heat-treating and recrystallizing the ion-implanted layer in the amorphous state, the 3C crystal structure can be easily formed, and the ohmic contact resistance can be further reduced.

(Twentieth Embodiment) FIG. 39 is a process sectional view showing an example of a method for manufacturing an electrode structure according to a twentieth embodiment of the present invention.

As shown in FIG. 39A, the SiC substrate 3
The ion implantation region 341 in an amorphous state is formed by ion-implanting Ge and a dopant element into the element 01. Ge and dopant ions may be implanted simultaneously or separately. Ion implantation temperature from room temperature to 8
00 ° C is desirable. Ge is contained in the ion implantation region 341 at a concentration of 1 × 10 ²¹ cm ⁻³ or more. As the dopant element, one in which the ion implantation region 341 has the same conductivity type as the SiC substrate 301 is used. SiC substrate 301 is n
If it is a type, the dopant is a Group 5 element, specifically N,
The dopant is selected from P, As, Sb, Bi, V, Nb, and Ta. If the SiC substrate 301 is p-type, the dopant is a Group 3 or Group 2 element, specifically, B, Al, Ga,
In, Tl, Zn, Cd, Hg, Sc, Y, Be, M
It shall be selected from g, Ca, Sr, Ba and Ra.

The ion implantation region 341 is made amorphous so that the dopant concentration in the region 341 becomes Si.
The concentration becomes higher than the solid solution limit in the thermal equilibrium state in C. As a result, Si _1-xy C _x G formed in the next step
The doping concentration in the e _y layer 343 can be dramatically improved, it is possible to reduce the ohmic contact resistance.

After the heat treatment, a cap layer 342 is deposited in a layer as shown in FIG. The order of the heat treatment and the cap layer deposition may be reversed. By performing the heat treatment, the ion-implanted layer 341 becomes Si _1-xy C _x Ge.
It becomes the _y layer 343. As the cap layer 342, a metal, an intermetallic compound, or the like that is the same as the one described above may be used.

(Twenty-First Embodiment) FIG. 40 is a process sectional view showing an example of a method for manufacturing an electrode structure according to a twenty-first embodiment of the present invention.

As shown in FIG. 40A, the SiC substrate 3
The ion implantation region 341 in an amorphous state is formed by ion-implanting Ge and a dopant element into the element 01. The ion implantation conditions and the dopant elements are the same as in the case of the twentieth embodiment. The ion implantation region 341 is made amorphous by forming the region 341 into an amorphous state.
The dopant concentration in SiC is higher than the solid solution limit in thermal equilibrium in SiC. As a result, the doping concentration in the Si _1-xy C _x Ge _y layer 346 formed in the next step can be significantly improved, and the ohmic contact resistance can be reduced.

After performing a heat treatment to form a Si _1-xy C _x Ge _y layer 346 as shown in FIG.
As shown in (c), the Ge layer 344 and the cap layer 345
Are deposited in layers. The order of the heat treatment and the deposition of the cap layer and the like may be reversed. Metal as the cap layer 342,
The same materials as those described above, such as an intermetallic compound, may be used. It is desirable that the Ge layer 344 be doped with the same conductivity type as the SiC substrate 301.

(22nd Embodiment) FIG. 41 is a process sectional view showing an example of a method for manufacturing an electrode structure according to a 22nd embodiment of the present invention.

As shown in FIG. 41A, the SiC substrate 3
After forming a mixture layer 352 of Ge and a dopant element on 01, Ge and the dopant element are ion-implanted to form an ion implantation region 351 in an amorphous state, as shown in FIG. The ion implantation conditions and the dopant elements are the same as in the case of the twentieth embodiment. By making the ion-implanted region 351 amorphous, the dopant concentration in the region 351 becomes higher than the solid solution limit in the thermal equilibrium state in SiC. As a result, the Si _1-xy C _x Ge _y layer 35 formed in the next step
4 can be drastically improved, and ohmic contact resistance can be reduced.

After performing a heat treatment to form a Si _1-xy C _x Ge _y layer 354 as shown in FIG. _41C , a cap layer 353 is deposited in a layer. The order of the heat treatment and the deposition of the cap layer may be reversed. As the cap layer 353, the same material as described above such as a metal and an intermetallic compound may be used.

(Twenty-third Embodiment) FIG. 42 is a sectional view showing a method for manufacturing an electrode structure according to a twenty-third embodiment of the present invention.

As shown in FIG. 42A, the SiC substrate 3
After depositing a poly-Si layer 361 on top of FIG.
As shown in FIG. 7, an implantation region 362 in an amorphous state is formed by ion implantation of Ge. It is desirable that the ion implantation region 362 be doped with the same conductivity type as the SiC substrate 301. The ion implantation temperature is preferably from room temperature to 800 ° C. G in the ion implantation region 362
e is contained at a concentration of 1 × 10 ²¹ cm ⁻³ or more.

As shown in FIG. 42 (c), heat treatment is performed to change the ion-implanted region 362 into the Si _{1-x- y} C _x Ge _y layer 36.
4, and an electrode 363 is further deposited thereon in a layered manner.
The order of heat treatment and electrode deposition may be reversed. As the electrode 363, a metal, an intermetallic compound, etc., specifically, Ni, Pd, Pt, Cu, Ag, Au, Z
n, Al, Ga, In, C, Si, Ge, Sn, Pb,
It is desirable that the material contains at least one element selected from Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, and W.

(24th Embodiment) FIG. 43 is a sectional view showing a method for manufacturing an electrode structure according to a 24th embodiment of the present invention.

As shown in FIG. 43A, the SiC substrate 3
After a poly-Si layer 371 is deposited on the substrate 01, Ge and a dopant element are ion-implanted to obtain a structure shown in FIG.
As shown in FIG.
Form 2 The ion implantation temperature is preferably from room temperature to 800 ° C. Ge is 1 × 10 ²¹ c in the ion implantation region 371.
m- ³ or more. The ion implantation conditions and the dopant elements are the same as in the case of the twentieth embodiment described above.

As shown in FIG. 43 (c), heat treatment is performed to change the ion implantation region 372 into the Si _{1-x- y} C _x Ge _y layer 37.
4, and an electrode 373 is further deposited thereon in layers.
The order of heat treatment and electrode deposition may be reversed. For the electrode 373, the same metal or the like as described above can be used. Since the Si _1-xy C _x Ge _y layer 374 is doped with impurities at a high concentration, the ohmic contact resistance can be reduced.

(Twenty-fifth Embodiment) FIG. 44 is a sectional view showing a method for manufacturing an electrode structure according to a twenty-fifth embodiment of the present invention.

As shown in FIG. 44A, the SiC substrate 3
01 and a mixture layer 381 of Si and Ge and a cap layer 38
2 is deposited in a layer and then subjected to a heat treatment to obtain FIG.
4 (b), the SiC substrate 301 and Si and G
The mixture layer 381 of e reacts to form a Si _1-xy C _x Ge _y layer 383. As the cap layer 382, the same metal or the like as described above may be used.

(Twenty-Sixth Embodiment) FIG. 45 is a sectional view showing a method of manufacturing an electrode structure according to a twenty-sixth embodiment of the present invention.

As shown in FIG. 45A, the SiC substrate 3
After depositing a mixture layer 391 of Si and Ge in a layer on 01, a dopant element is ion-implanted. Then, FIG.
After depositing the cap layer 393 as shown in FIG. By the heat treatment, the SiC substrate 301 and the mixture layer 92 of Si and Ge into which the dopant element is ion-implanted.
React to form a Si _1-xy C _x Ge _y layer 394. Since the Si _1-xy C _x Ge _y layer 394 is heavily doped with impurities, ohmic contact resistance can be reduced.

In the sixteenth to twenty-sixth embodiments described above, the heat treatment is performed at 500 ° C. to 1000 ° C., preferably 700 ° C. to 9 ° C. in an atmosphere of an inert gas such as Ar.
It is preferably performed at 00 ° C.

(Twenty-Seventh Embodiment) FIG. 46 is a sectional view showing a configuration example of a Schottky diode according to the present embodiment. In the present embodiment, the Si around the Schottky electrode
When a guard ring of the opposite conductivity type to the C substrate is provided,
A sufficiently low ohmic contact is made between the guard ring and the electrode.

In FIG. 46, reference numeral 401 denotes an SiC substrate,
02 is a SiC epitaxial growth layer, 403 is a doping layer serving as a guard ring, 404 is a back electrode, and 405 is a surface treatment layer (Si _1-xy C _x doped with impurities).
Ge _y layer), 406 is a surface electrode.

A lightly doped n-type SiC epitaxial growth layer 402 (having a thickness of 10 μm) is formed on an n-type SiC substrate 401.
A substrate on which m) was formed was prepared. SiC is what is called 4H
And the orientation of the epitaxially grown surface is the so-called Si surface of the (001) plane.

After performing a cleaning process on the substrate,
An oxide film was formed at 1200 ° C. in an oxygen atmosphere. afterwards,
A silicon oxide film was further formed by normal pressure CVD to obtain an oxide film having a total thickness of 1 μm. Subsequently, the oxide film was patterned to form a pattern without an oxide film at a predetermined position. 1000 ° C. with respect to the substrate on which the oxide film is formed.
Then, boron ions were implanted at 10 ¹⁹ cm ⁻³ . Subsequently, annealing is performed at 1500 ° C. to activate the doped boron, and a p-type doping layer 4 is formed in a portion having no oxide film.
03 was formed. After removing the oxide film on the back surface, Ni was vapor-deposited at 1 μm as the back surface electrode 404 and annealed at 950 ° C. to secure ohmic contact with the substrate on the back surface.

Next, a p-type doping layer 403 is formed by an acid treatment.
After cleaning the surface, Ge was ion-implanted, and FIG.
As shown in (enlarged view of FIG. 46A), the surface treatment layer 4
05 (boron doped Si _1-xy C _x Ge _y
Layer). Ge is 1 × 1 in the surface treatment layer 405.
It is contained at a concentration of 0 ²¹ cm ^-3 or more. Thereafter, all oxide films were removed, and Ti was applied as
m was deposited and patterned. Further, annealing was performed at 400 ° C. to form a structure as shown in FIG.

In the sample prepared in this manner, SiC
The epitaxial growth layer 402 and the surface electrode 406 were in Schottky contact, and the p-type doping layer serving as a guard ring and the surface electrode 406 were in ohmic contact due to the action of the surface treatment layer 405. The contact resistance in the ohmic contact region was 2 × 10 ⁻⁴ Ωcm ² . This is G
The surface becomes amorphous by ion implantation of e,
This is because good ohmic properties were obtained even with low-temperature annealing at about 400 ° C.

Before the ion implantation of boron, the exposed surface of the substrate is oxidized again to form a thin oxide film of about 50 nm, or Ge is deposited on the surface of the substrate to form a thin layer. Then, a sample in which Ge ions were implanted was also prepared. In this case, the contact resistance is 1 × 10 ⁻⁴ Ωc
m ² , and the ohmic properties were further improved.

Further, as the SiC substrate 401, a p-type Si
Using C, a sample using an n-type doping layer for the guard ring was also prepared. As the surface treatment layer 405, a material obtained by ion implantation of Ge or Si was used. The resistance at the ohmic portion was a value on the order of 10 ⁻⁵ Ωcm ² , and an ohmic contact could be secured. It is considered that in the case where Si was ion-implanted, silicidation was caused between the electrode and the electrode, and the ohmic property was easily obtained.

(Twenty-eighth Embodiment) FIG. 47 is a sectional view showing a configuration example of a Schottky barrier diode according to a twenty-eighth embodiment of the present invention.

An n-type SiC epitaxial layer 501 is formed on an n-type SiC substrate 500, and a p-type SiC layer 502 is formed in a predetermined region on the SiC epitaxial layer 501, and is sandwiched between the p-type SiC layers 502. A Schottky electrode 503 is formed on the SiC epitaxial layer 501. The surfaces of p-type SiC layer 502 and Schottky electrode 503 are covered with polysilicon 504, and ohmic electrode 505 is formed on the back surface of n-type SiC substrate 500.

The SiC epitaxial layer 501 contains a predetermined concentration of hydrogen. SiC has a problem that the acceptor level and the donor level are deep, and carriers are often trapped in a deep level formed by a non-dopant impurity, resulting in deterioration of device characteristics. By including hydrogen, it is possible to compensate for the deep level created by the non-dopant impurity, and the carrier concentration and the carrier mobility are increased,
The electrical characteristics of the Schottky barrier diode can be improved.

Further, if hydrogen is also contained in the p-type SiC layer 502, an effect of inactivating the residual donor can be obtained, so that the carrier concentration of the p-type SiC is further increased to reduce the leak current. Can also.

SiC containing hydrogen can be produced by simultaneously or separately ion-implanting dopant ions and hydrogen ions into the surface, or by mixing hydrogen during crystal growth. Hydrogen concentration is 1 × 10 ¹⁸ c
m ⁻³ or less, and 1 × 10 ¹⁴ cm ⁻³
It is preferable that it is above.

(Twenty-ninth Embodiment) FIG. 48 is a sectional view showing a configuration example of a Schottky barrier diode according to a twenty-ninth embodiment of the present invention.

An n-type SiC epitaxial layer 511 is formed on n-type SiC substrate 510, and a silicon oxide film 512 is formed in a predetermined region on SiC epitaxial layer 511. Si on which a silicon oxide film 512 is formed
The upper part of the C epitaxial layer 511 is the Schottky electrode 5
13 and an ohmic electrode 514 is formed on the back surface of the n-type SiC substrate 510.

A predetermined concentration of oxygen is contained in the n-type SiC substrate 510 and the SiC epitaxial layer 511. SiC has many crystal defects caused by vacancies and the like, and the defect can be relaxed by containing oxygen.
The carrier concentration and the carrier mobility increase, and the electrical characteristics of the Schottky barrier diode can be improved.

The SiC containing oxygen can be produced by simultaneously or separately implanting dopant ions and oxygen ions on the surface, or by mixing oxygen during crystal growth. Oxygen concentration is 1 × 10 ¹⁸ c
m ⁻³ or less, and 1 × 10 ¹⁴ cm ⁻³
It is preferable that it is above.

In the twenty-eighth and twenty-ninth embodiments, the Schottky barrier diode has been described as an example.
Other Si such as rectifiers and switching elements using C
It is also applicable to C semiconductor devices.

The SiC shown in each of the above embodiments has an SC having all crystal structures such as 2H, 4H, 6H, and 3C.
iC applies.

The embodiments of the present invention have been described above. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention.

[0148]

According to the present invention, in a semiconductor device using SiC, the resistance can be reduced by forming the electrode region into a predetermined structure. Further, by including oxygen or hydrogen in SiC, it is possible to suppress a decrease in carrier concentration or carrier mobility. Therefore, according to the present invention, a high-performance semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a configuration according to a first embodiment of the present invention.

FIG. 2 is a diagram showing another example of the configuration according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an example of a configuration according to a second embodiment of the present invention.

FIG. 4 is a diagram showing an example of a configuration according to a third embodiment of the present invention.

FIG. 5 is a view showing an example of a manufacturing process according to a third embodiment of the present invention.

FIG. 6 is a view showing another example of the manufacturing process according to the third embodiment of the present invention.

FIG. 7 is a view showing another example of the manufacturing process according to the third embodiment of the present invention.

FIG. 8 is a view showing an example of a manufacturing process according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing an example of a configuration according to a fifth embodiment of the present invention.

FIG. 10 is a view showing an example of a manufacturing process according to a fifth embodiment of the present invention.

FIG. 11 is a diagram showing an example of a configuration according to a sixth embodiment of the present invention.

FIG. 12 is a view showing an example of a manufacturing process according to a sixth embodiment of the present invention.

FIG. 13 is a diagram showing another example of the configuration according to the sixth embodiment of the present invention.

FIG. 14 is a diagram showing an example of a configuration according to a seventh embodiment of the present invention.

FIG. 15 is a view showing an example of a manufacturing process according to a seventh embodiment of the present invention.

FIG. 16 is a diagram showing an example of a configuration according to an eighth embodiment of the present invention.

FIG. 17 is a view showing an example of the manufacturing process according to the eighth embodiment of the present invention.

FIG. 18 is a diagram showing another example of the configuration according to the eighth embodiment of the present invention.

FIG. 19 is a diagram showing an example of a configuration according to a ninth embodiment of the present invention.

FIG. 20 is a view showing an example of a manufacturing process according to a ninth embodiment of the present invention.

FIG. 21 is a diagram showing an example of a configuration according to a tenth embodiment of the present invention.

FIG. 22 is a view showing an example of the manufacturing process according to the tenth embodiment of the present invention.

FIG. 23 is a view showing another example of the configuration according to the tenth embodiment of the present invention.

FIG. 24 is a view showing another example of the manufacturing process according to the tenth embodiment of the present invention.

FIG. 25 is a diagram showing an example of a configuration according to an eleventh embodiment of the present invention.

FIG. 26 is a view showing an example of the manufacturing process according to the eleventh embodiment of the present invention.

FIG. 27 is a diagram showing an example of a configuration according to a twelfth embodiment of the present invention.

FIG. 28 is a diagram showing an example of a configuration according to a thirteenth embodiment of the present invention.

FIG. 29 is a diagram showing an example of a configuration according to a fourteenth embodiment of the present invention.

FIG. 30 is a view showing an example of the manufacturing process according to the fifteenth embodiment of the present invention.

FIG. 31 is a view showing an example of a configuration according to a sixteenth embodiment of the present invention.

FIG. 32 is a view showing another example of the configuration according to the sixteenth embodiment of the present invention.

FIG. 33 is a view showing another example of the configuration according to the sixteenth embodiment of the present invention.

FIG. 34 is a view showing an example of a configuration according to a seventeenth embodiment of the present invention.

FIG. 35 is a view showing an example of the manufacturing process according to the eighteenth embodiment of the present invention.

FIG. 36 is a view showing another example of the manufacturing process according to the eighteenth embodiment of the present invention.

FIG. 37 is a view showing another example of the manufacturing process according to the eighteenth embodiment of the present invention;

FIG. 38 is a view showing an example of the manufacturing process according to the nineteenth embodiment of the present invention.

FIG. 39 is a view showing an example of the manufacturing process according to the twentieth embodiment of the present invention.

FIG. 40 is a view showing an example of the manufacturing process according to the twenty-first embodiment of the present invention.

FIG. 41 is a view showing an example of the manufacturing process according to the twenty-second embodiment of the present invention.

FIG. 42 is a view showing an example of the manufacturing process according to the twenty-third embodiment of the present invention.

FIG. 43 is a view showing an example of the manufacturing process according to the twenty-fourth embodiment of the present invention.

FIG. 44 is a view showing an example of the manufacturing process according to the twenty-fifth embodiment of the present invention.

FIG. 45 is a view showing an example of the manufacturing process according to the twenty-sixth embodiment of the present invention.

FIG. 46 is a view showing an example of a configuration according to a twenty-seventh embodiment of the present invention.

FIG. 47 is a view showing an example of a configuration according to a twenty-eighth embodiment of the present invention.

FIG. 48 is a view showing another example of the configuration according to the twenty-eighth embodiment of the present invention.

[Explanation of symbols]

101,130,140 ... SiC substrate 102 ... Si _x C _1-x layer 103, 112 ... metal layer 104,121,131,141 ... first element layer 105,122,132,142 ... first element carbide layer 106 ... Poly Si layer 107: doped poly Si layer 108, 111, 155, 165: amorphous region 109: poly SiC layer 110: doped poly Si layer 113: carbide layer 120: poly SiC layer 123, 143: second element layer 124, 134, 144 ... second element silicide layer 125 ... mixed layer of first element, second element, first element carbide, and second element silicide 126, 136 ... mixed layer of first element and second element 127, 137, 154, 163: cap layer 133: second element nitride layer 135: first element, second element nitride, first element carbide,
Mixed layer of second element silicide 145, 152, 162 Third element high concentration layer 146, 166 Third element layer 151 First element, second element, third element, first element carbide, second element Mixed layer of silicide 153 ... Mixed layer of first element, second element, third element 161 ... Mixed layer of third element, fourth element, fourth element carbide, fourth element silicide 167 ... Fourth element layer 201, 222: SiC-IGBT 202, 215, 223: Wiring material 203: Al wire 210: SiC-SBD 211, 251: SiC substrate 212: SiC epitaxial layer 213: Schottky electrode 214: Ohmic electrode 221: SiC-SBD 224 ... metal layer 225, 226 ... electrode 252 ... SiO ₂ film 253 and 254 ... electrode member 255 ... electrode 301 ... SiC substrate 302,322,333,336 343,346,3
54, 364, 374, 383, 394 ... Si _1-xy C
_x Ge _y layer 303,323,332,335,342,345,3
53 ... cap layer 304,334,344 ... Ge layer _{321 ... Si 1-xy C x} Ge y deposited layer 331,341,351,362,372,392 ... ion implanted region 352,381,391 ... mixture layer 361, 371 ... poly-Si deposition layer 363,373 ... electrodes 382 ... cap layer, 393 401 ... SiC substrate 402 ... SiC epitaxial growth layer 403 ... doping layer 404 ... rear electrode 405 surface treatment layer _{(Si 1-xy C x Ge} y layer) 406 ... Surface electrodes 500, 510 ... n-type SiC substrate 501, 511 ... n-type SiC epitaxial layer 502 ... p-type SiC layer 503, 513 ... Schottky electrode 504 ... polysilicon layer 505, 514 ... ohmic electrode 512 ... silicon oxide film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Osamu Takikawa, Inventor: Okamu Toshiba-cho, Kochi-ku, Kawasaki-shi, Kanagawa Prefecture 1 Toshiba R & D Center Co., Ltd. (72) Inventor: Seiji Imai Komukai, Sachi-ku, Kawasaki-shi, Kanagawa No. 1 Toshiba-cho, Toshiba R & D Center (72) Inventor Hidetoshi Fujimoto No. 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term (reference) 4M104 AA03 AA07 BB01 BB02 BB04 BB05 BB06 BB07 BB09 BB14 BB16 BB17 BB18 BB20 BB21 BB24 BB25 BB26 BB27 BB34 BB37 BB38 BB40 CC01 DD35 DD78 DD91 GG03 HH15 HH20

Claims (12)

[Claims] 1. A semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region includes a Si _x C _1-x layer where x> 0.5. A semiconductor device characterized in that: 2. A semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region has a Si _x C _{1 -x} layer with x> 0.5 and a carbide enthalpy of formation. A semiconductor device including a layer made of a carbide of a first element having a negative value. 3. A semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region includes a SiC layer doped with an impurity. Semiconductor device. 4. A semiconductor device having a SiC region and an electrode region formed on the SiC region, wherein the electrode region is a layer made of a first element carbide having a negative enthalpy of carbide formation. And a layer of silicide of a second element having a negative value of enthalpy of silicide formation, or a region of carbide of a first element having a negative value of enthalpy of carbide formation and silicidation. A semiconductor device comprising a layer in which a region of silicide of a second element having a negative enthalpy of formation is mixed. 5. A semiconductor device having an n-type SiC region and an electrode region formed on the n-type SiC region, wherein the electrode region is formed of a first element having a negative enthalpy of carbide formation. A layer composed of a carbide, a layer composed of a silicide of the second element having a silicide formation enthalpy of a negative value, and a layer composed of a nitride of the second element.
Alternatively, the region of the carbide of the first element having a negative value of the enthalpy of carbide formation, the region of the silicide of the second element having the negative value of enthalpy of silicide formation, and the region of the nitride of the second element have a negative value. A semiconductor device comprising a mixture of layers. 6. A semiconductor device having a p-type SiC region and an electrode region formed on the p-type SiC region, wherein the electrode region is formed of a first element having a negative enthalpy of carbide formation. A layer made of carbide, a layer made of silicide of the second element having a negative enthalpy of silicide formation, and 2
Or a layer of a first element having a negative value of the enthalpy of carbide formation and a enthalpy of formation of the silicide having a negative value, A semiconductor device including a layer in which a region of a silicide of a second element is mixed and a layer containing a third element belonging to Group 2 or Group 3. 7. A semiconductor device having a p-type SiC region and an electrode region formed on the p-type SiC region, wherein the electrode region has a negative value for enthalpy for generating carbide and a value for enthalpy for generating silicide. A layer composed of a carbide of the fourth element, a layer composed of a silicide of the fourth element, and a layer containing a third element of Group 2 or 3; or a carbide-forming enthalpy and silicide It includes a layer in which a region of a carbide of the fourth element and a region of a silicide of the fourth element having a negative value of the formation enthalpy are mixed, and a layer containing a third element of Group 2 or Group 3. A semiconductor device. 8. A semiconductor device having an SiC region, an electrode portion formed on the SiC region, and a wiring portion formed on the electrode portion, wherein a material used for the wiring portion is a predetermined metal such as silicon. And a semiconductor device containing carbon. 9. The semiconductor device according to claim 8, wherein said predetermined metal contains silicon and carbon at a concentration higher than a solid solution limit for said metal. 10. A semiconductor device having a SiC region and the electrode region formed on the SiC region, the electrode region is Ge concentration 10 ²¹ cm ^-3 or more Si _1-xy C
wherein a that is configured to include a _x Ge _y layer. 11. A first conductivity type SiC region, an electrode portion Schottky-bonded to the first conductivity type SiC region,
A semiconductor device having a second conductivity type SiC region sandwiched between the electrode portion and the first conductivity type SiC region in a region corresponding to an outer peripheral portion of the electrode portion; The Ge concentration is 1 at the boundary between the two conductivity type SiC regions.
A semiconductor device, wherein a Si _1-xy C _x Ge _y layer of 0 ²¹ cm ⁻³ or more is formed. 12. A semiconductor device having an SiC region containing oxygen or hydrogen of 1 × 10 ¹⁸ cm ⁻³ or less.