JP3356149B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit,
In particular, the present invention relates to a PLL circuit with an improved pull-in time.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a conventional PLL circuit. A phase comparator (PD) 1, a frequency comparator (FD) 2, charge pump (CP) circuits 3, 4 are shown.
, A loop filter 5, and a VCO (voltage controlled oscillator) 6
It is a configuration consisting of As shown in FIG. 5, the phase comparator 1 receives the input reference signal Din and the comparison signal Vout (VCO6).
And the inverted signal VoutB of the comparison signal (the inverted output of the VCO 6 and CLK-B
), And UP according to the flow of FIG.
(Up) and DOWN (down) signals.

That is, when the input reference signal Din changes from 0 to 1
, Or when it changes from 1 to 0, the UP signal is set to 1. When the comparison signal Vout (CLK) changes from 0 to 1, the UP signal is set to 0 and the DOWN signal is set to 1. Further, the inverted signal VoutB (CLK-B) of the comparison signal changes from 0 to 1
When it changes to 0, 0 is output to DOWN.

The charge pump circuit 3 has a phase comparator U
With the P and DOWN signals as inputs, a constant current is output while the UP signal is 1 and a constant current is output while the DOWN signal is 1. The frequency comparator 2 receives the input reference signal Din, the comparison signal Vout (CLK), and the 90-degree shift signal VoutQ of the comparison signal as inputs, and sets 1 as UP when the frequency of the comparison signal is slower than the frequency of the input reference signal. When the frequency of the comparison signal is faster than the frequency of the input reference signal, 1 is output as DOWN.

More specifically, the comparison signal and the comparison signal 9
0 degrees out more determined each state in the signal are defined as follows (see Figure 7). That is, A when the comparison signal is 1 and the 90-degree shift signal of the comparison signal is 0, B when the comparison signal is 1 and the 90-degree shift signal of the comparison signal is 1, and B when the comparison signal is 0 and the comparison signal is 90 degrees. C when the shift signal is 1 and 0 when the comparison signal is
D when the 90 ° shift signal of the comparison signal is 0.

[0006] Falling (rising) of the input reference signal
The state at the time is obtained, and the state transition is A → B, B → C, C →
When a transition is made from D to D to A, 1 is output to DOWN because the frequency of the comparison signal is faster than the frequency of the input reference signal. The state transitions are A → D, D → C, C → B, B →
In the case of transition to A, 1 is output to UP because the frequency of the comparison signal is slower than the frequency of the input reference signal.

The charge pump circuit 4 receives the UP signal and the DOWN signal output from the frequency comparator as inputs and outputs a constant current while the UP signal is 1 and outputs a constant current while the DOWN signal is 1. The loop filter 5 receives the outputs of the two charge pump circuits 3 and 4 as inputs, integrates the signals, and outputs the integrated control voltage. VCO
6 receives the output of the loop filter 5 as an input and outputs a signal Vout having a frequency corresponding to the input voltage, a 90-degree phase shift signal VoutQ, and an inverted signal VoutB. The loop filter 5 can be composed of a resistor and a capacitor, and is well known. Therefore, the description thereof is omitted, but various modified examples can be used.

[0008]

SUMMARY OF THE INVENTION A PL having the above-described configuration
In the L circuit, the frequency of the input reference signal and the frequency of the comparison signal match, but when the phase is out of phase, the phase comparator pulls in the phase. However, this method has a problem in that when the phase is shifted by nearly 90 degrees or when the phase is shifted by almost 180 degrees, it takes a long time to pull in.

Therefore, an object of the present invention is to solve the above-mentioned drawbacks of the prior art, and it is an object of the present invention to reduce the phase difference between the input reference signal and the comparison signal by 90%.
An object of the present invention is to provide a PLL circuit capable of shortening the pull-in time when the shift is close to 180 degrees or when the shift is close to 180 degrees.

[0010]

According to the present invention, there is provided a phase error detecting means for detecting a phase error between an input reference signal and a comparison signal and outputting a phase error signal; Frequency error detection means for detecting a frequency difference between the input reference signal and the comparison signal and outputting a ± 90 degree deviation signal between the input reference signal and the comparison signal. A control voltage generating means for generating a control voltage in accordance with each output of the phase error detecting means, the frequency error detecting means, and the 90 ° shift detecting means; and outputting the comparison signal having a frequency corresponding to the control voltage. PLL including voltage-controlled oscillation means
A circuit is obtained.

At the time of falling (rising) of the input reference signal, the comparison signal is 1 and 90
The case where the degree shift signal is 0 is A, the case where the comparison signal is 1 and the 90 degree shift signal of the comparison signal is 1 is B, and the comparison signal is 0 and the 90 degree shift signal of the comparison signal is 1 When the case is defined as C and the case where the comparison signal is 0 and the 90-degree shift signal of the comparison signal is 0 is defined as D, the 90-degree shift detection means determines whether the input reference signal falls (rises). Of the comparison signal and 90 of the comparison signal
The relation with the deviation signal is examined. If the transition is made from D to D, a +90 degree deviation is detected and the above-mentioned +90 degree deviation signal is output. It is characterized by detecting and outputting the -90 degree shift signal.

The control voltage generating means includes a charge pump circuit to which each output of the phase error detecting means, the frequency error detecting means, and the 90 ° shift detecting means is input,
An integration circuit for integrating each output of the charge pump circuit. Further, the charge pump circuit outputs a current in a positive direction and a current in a negative direction in accordance with the ± 90 ° shift signal.

Further, the 90-degree shift detecting means is configured to detect a 180-degree shift between the input reference signal and the comparison signal and output a 180-degree shift signal. In addition, the relationship between the comparison signal at the time of falling (rising) of the input reference signal and the 90-degree shift signal of the comparison signal is examined, and when a transition is made from D to A or A to D, a 180-degree shift is detected. And outputting the 180 ° shift signal. Further, a switching means for switching the phase of the comparison signal to ± 90 or 180 degrees in accordance with the ± 90 ° shift signal or the 180 ° shift signal is provided.

The operation of the present invention will be described. By detecting a deviation of ± 90 degrees and charging a positive or negative current to the loop filter at the time of the detection, the pull-in time is shortened. That is, the relationship between the comparison signal and the 90-degree shift signal of the comparison signal is defined as follows by the phase shift detector of 90 degrees or more.

When the input reference signal falls (rises),
A when the comparison signal is 1 and the 90-degree displacement signal of the comparison signal is 0, B when the comparison signal is 1 and the 90-degree displacement signal of the comparison signal is 1, and B when the comparison signal is 0 and the 90-degree displacement signal of the comparison signal. Is 1
Is C, the case where the comparison signal is 0 and the 90-degree shift signal of the comparison signal is 0 is D.

The input reference signal falls (rises)
At this time, the relationship between the comparison signal and the 90-degree shift signal of the comparison signal is examined.
Outputs the WN signal. Also, when the transition is made from A to A,-
A 90-degree shift is detected and an UP signal is output. The charge pump circuit receives the UP signal and the DOWN signal indicating that the phase is shifted by 90 degrees or more, and outputs a positive or negative current to the Lupus filter. Thereby, the retraction time can be reduced.

Further, the shift time is shortened by detecting the shift of ± 90 degrees and 180 degrees of the comparison signal and digitally switching the phase of the output signal of the VCO by 90 degrees, -90 degrees and 180 degrees. That is, when the relationship between the comparison signal and the 90-degree shift signal of the comparison signal is defined as above,
At the time of falling (rising) of the input reference signal, the relationship between the comparison signal and the 90-degree shift signal of the comparison signal is examined, and when a transition is made from D to D, a 90-degree shift is detected, and 1 (D) is output to the output terminal (D). When 0) changes from output D, A to A, a -90 degree shift is detected and 1 (0) is output to the output terminal (A). Further, when a transition is made from D to A or A to D, a 180-degree shift is detected, and 1 is output to the output terminal (DA).

In the phase switch for switching the phase of the comparison signal, the output Vout of the VCO, the output VoutQ + of a + 90 ° shifted waveform of Vout, the output VoutB of a + 180 ° shifted waveform of Vout, and the output VoutQ− of a −90 ° shifted waveform of Vout. Of 4
The waveforms and the outputs A, D, and D of the phase difference detection means of 90 degrees or more
A is input. When the output D is 1, this phase switch outputs VoutQ + as Vout, VoutB as VoutQ, and VoutQ- as VoutB. When output A is 1,
VoutQ- is Vout, Vout is VoutQ, VoutQ + is VoutB
And output each. When output DA is 1, Vou
tB is output as Vout, Vout is output as VoutQ, and VoutQ + is output as VoutB. When the outputs D, A, and DA are all 0, Vout is Vout, VoutQ + is VoutQ, and VoutB is Vou.
Each is output as tB. The outputs A, D, and DA do not become 1 at the same time.

By this processing, the 90-degree shift signal and -9
From the 0-degree shift signal and the 180-degree shift signal, it is possible to change the phase of the comparison signal by 90 degrees, -90 degrees, or 180 degrees and to output the comparison signal, thereby shortening the pull-in time.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention, and the same parts as those in FIG. 4 are denoted by the same reference numerals. As shown in FIG. 1, the PL of the first embodiment
The L circuit includes a phase comparator 1, a frequency comparator 2, charge pump circuits 3, 4, 8, a loop filter 5, and a VC.
O6 and a detector 7 having a phase of 90 degrees or more.

The PLL circuit having this configuration will be described below. The phase comparator 1 is the phase comparator 1 shown in FIG.
And, as shown in FIG. 5, the input reference signal Din
, The comparison signal CLK, and the inverted signal CLK-B of the comparison signal
And outputs UP and DOWN signals according to the flow of FIG. That is, the input reference signal Din is changed from 0 to 1
, Or when it changes from 1 to 0, the UP signal is set to 1. When the comparison signal CLK changes from 0 to 1, U
0 is output to P and 1 is output to DOWN. When the inverted signal CLK-B of the comparison signal changes from 0 to 1, DOWN
Is output as 0.

The charge pump circuit 3 is equivalent to the charge pump circuit 3 of FIG.
With the WN signal as an input, a constant current is output while the UP signal is 1 and a constant current is output while the DOWN signal is 1.

The frequency comparator 2 receives an input reference signal, a comparison signal, and a 90-degree shift signal of the comparison signal as inputs, and if the frequency of the comparison signal is lower than the frequency of the input reference signal,
Is output to DOWN, and in the opposite case, 1 is output to DOWN. That is,
The state based on the comparison signal and the 90-degree shift signal of the comparison signal is defined as shown in FIG.
reference).

A is when the comparison signal is 1 and the 90-degree shift signal of the comparison signal is 0, B is when the comparison signal is 1 and the 90-degree shift signal of the comparison signal is 1, and 0 when the comparison signal is 0 and the comparison signal is 90. The case where the degree shift signal is 1 is C, the comparison signal is 0 and the comparison signal is 9
The case where the 0-degree shift signal is 0 is D.

The input reference signal falls (rises)
The state at the time is obtained, and the state transition is A → B, B → C, C →
When a transition is made from D to D to A, 1 is output to DOWN because the frequency of the comparison signal is faster than the frequency of the input reference signal. The state transitions are A → D, D → C, C → B, B →
In the case of transition to A, 1 is output to UP because the frequency of the comparison signal is slower than the frequency of the input reference signal.

The charge pump circuit 4 receives a UP signal and a DOWN signal as outputs of the frequency comparator and outputs a constant current while the UP signal is 1 and outputs a constant current while the DOWN signal is 1.

When the phase difference of 90 degrees or more is input by the input reference signal, the comparison signal, and the 90 degree shift signal of the comparison signal, and the comparison signal is shifted by 90 degrees or more from the input reference signal, the DOWN signal is output. Is output. If the comparison signal is shifted by more than -90 degrees from the input reference signal, U
Outputs the P signal.

That is, each state is defined in the same manner as described above by the comparison signal and the 90-degree shift signal of the comparison signal. When the state of the comparison signal and the 90-degree shift signal of the comparison signal at the time of falling (rising) of the input reference signal transitions from D to D, a 90-degree shift is detected and a DOWN signal is output. In addition, when a transition is made from A to A, a shift of -90 degrees is detected and UP is detected.
Output a signal. Further, when the state of the comparison signal and the 90-degree shift signal of the comparison signal at the time of falling (rising) of the input reference signal transitions from A to D and D to A, a 180-degree shift is detected and the UP or DOWN signal is detected. Output.

The charge pump circuit 8 inputs an UP signal and a DOWN signal indicating that a phase shift of 90 ° or more has been detected at the output of the phase shift detector 90 ° or more, and outputs a positive or negative current to the loop filter 5. I do. The loop filter 5 receives the outputs of the three charge pump circuits as inputs, integrates the signals, and outputs an integrated control voltage.
The VCO 6 receives the output of the loop filter 5 as an input, and outputs a signal Vout having a frequency corresponding to the input voltage, a 90-degree phase shift signal VoutQ thereof, and an inverted signal VoutB.

As described above, the pull-in time can be shortened by detecting a deviation of ± 90 degrees and charging a positive or negative current to the loop filter at the time of detection. That is, the phase detector 90 shifts the phase by 90 degrees or more.
The relationship between the comparison signal and the 90 ° shift signal of the comparison signal is defined as shown in FIG. 7, and the relationship between the comparison signal and the 90 ° shift signal of the comparison signal when the input reference signal falls (rises) is examined. When a transition is made from D to D, a 90-degree shift is detected and a DOWN signal is output. Also, the comparison signal when the input reference signal falls (rises) and the comparison signal 90
Investigate the relationship between the deviation signals, and if the transition from A to A is-
A 90-degree shift is detected and an UP signal is output.

The charge pump circuit 4 receives an UP signal and a DOWN signal indicating that a phase shift of 90 degrees or more has been detected and inputs a positive or negative current to the loop filter 5.
Output to Thereby, the retraction time can be reduced.
This means that, although the frequency is almost the same, if a phase shift of 90 degrees or more (−90 degrees or more, 90 degrees or more) is found, the gain of the phase comparator is set higher (lower) than usual. This is the same (the characteristic shown in FIG. 2), and the time for phase pull-in can be shortened.

Similarly, when a shift of about 180 degrees is detected, it is the same as increasing (lowering) the gain of the phase comparator (the characteristic shown in FIG. 2), and the time for phase pull-in can be shortened. .

FIG. 3 is a view showing a second embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. The PLL circuit of this example includes a phase comparator 1, a frequency comparator 2, charge pump circuits 3 and 4, a loop filter 5, and a VC.
O 6, a phase shifter 9 or more, and a phase shifter 9.

As shown in FIG. 3, the phase comparator receives the input reference signal Din, the comparison signal CLK, and the inversion signal CLK-B of the comparison signal as inputs and follows the flow of FIG.
Outputs a DOWN signal. That is, the input reference signal Din
Is changed from 0 to 1 or from 1 to 0, the UP signal is set to 1. Further, when the comparison signal CLK changes from 0 to 1, it outputs 0 to UP and 1 to DOWN. When the inverted signal CLK-B of the comparison signal changes from 0 to 1, D
0 is output to OWN.

The charge pump circuit 3 receives the UP and DOWN signals of the phase comparator 1 as inputs and outputs a constant current while the UP signal is 1, and outputs a constant current while the DOWN signal is 1. The frequency comparator 2 receives the input reference signal, the comparison signal, and the 90-degree shift signal of the comparison signal as inputs and increases the comparison signal when the frequency of the comparison signal is lower than the frequency of the input reference signal.
Is output to DOWN, and conversely, 1 is output to DOWN when it is early. That is, the state is defined as follows based on the comparison signal and the 90 ° shift signal of the comparison signal (see FIG. 7).

A indicates that the comparison signal is 1 and the 90-degree shift signal of the comparison signal is 0, B indicates that the comparison signal is 1 and the 90-degree shift signal of the comparison signal is 1, and B indicates that the comparison signal is 0 and the comparison signal is 90. The case where the degree shift signal is 1 is C, the comparison signal is 0 and the comparison signal is 9
The case where the 0-degree shift signal is 0 is D.

The falling (rising) of the input reference signal
The state at the time is obtained, and the state transition is A → B, B → C, C →
When a transition is made from D to D to A, 1 is output to DOWN because the frequency of the comparison signal is faster than the frequency of the input reference signal. The state transitions are A → D, D → C, C → B, B →
In the case of transition to A, 1 is output to UP because the frequency of the comparison signal is slower than the frequency of the input reference signal.

The charge pump circuit 4 receives the output of the frequency comparator, the UP signal and the DOWN signal,
And outputs a certain current while the DOWN signal is one. The phase difference detector of 90 degrees or more is
The DOWN signal is output when the input reference signal, the comparison signal, and the 90-degree shift signal of the comparison signal are input and the comparison signal is shifted by 90 degrees or more from the input reference signal. If the comparison signal deviates by more than -90 degrees from the input reference signal, an UP signal is output. That is, if the state is defined in the same manner as described above from the comparison signal and the 90-degree shift signal of the comparison signal, when the state transitions from D to D, a 90-degree shift is detected and 1 (0) is output to the output terminal D. . Further, when the state of the comparison signal and the 90-degree shift signal of the comparison signal at the time of the fall (rising) of the input reference signal transitions from A to A, a −90-degree shift is detected and 1 (0) is output to the output terminal A. ) Is output.

When the state of the comparison signal at the time of falling (rising) of the input reference signal and the state of the signal shifted by 90 degrees from the comparison signal change from D to A or A to D, a 180 degree shift is detected and the output terminal is detected. Output 1 to DA.

The phase switch 9 outputs the output Vou of the VCO 6
t, Vout of +90 degree waveform output VoutQ +, Vout
Are output as VoutB and VoutQ-, which are output waveforms shifted by +180 degrees and -90 degrees of Vout, and outputs A, D, and DA of the phase difference detector of 90 degrees or more.

When D is 1, the phase switch 9 sets Vou
t is VoutQ- , VoutQ + is Vout, VoutB is VoutQ + ,
VoutQ- is output as VoutB. When A is 1, VoutQ- is Vout, Vout is VoutQ + , VoutQ +
As VoutB and VoutB as VoutQ− , respectively.

When DA is 1, VoutB is changed to Vout, Vout
As VoutB , VoutQ + as VoutQ−, and VoutQ− as VoutQ + , respectively. When D, A, and DA are all 0, Vout is Vout, VoutQ + is VoutQ + , and VoutB is Vout.
outB and VoutQ- are output as VoutQ- , respectively.
Note that the terminals A, D, and DA do not become 1 at the same time.

The loop filter 5 receives the outputs of the two charge pump circuits 3 and 4 as inputs, integrates the signals, and outputs an integrated control voltage. VCO 6 is a loop filter 5
Of the frequency corresponding to the input voltage with the output of
out, its 90-degree phase shift signal VoutQ, and the inverted signal VoutQ.
outB is output.

As described above, in the second embodiment, 90-degree shift, -90-degree shift, and 180-degree shift of the comparison signal are detected.
The output signal of the VCO is digitally converted to 90 degrees, -90 degrees, 1
By switching by 80 degrees, the pull-in time can be reduced. That is, the relationship between the comparison signal and the 90-degree shift signal of the comparison signal is defined as described above, and the relationship between the comparison signal at the time of falling (rising) of the input reference signal and the 90-degree shift signal of the comparison signal is determined. When the transition is made from D to D, a 90-degree shift is detected, and 1 (0) is output to the output terminal D.

Further, the relationship between the comparison signal at the time of falling (rising) of the input reference signal and the 90-degree shift signal of the comparison signal is checked. Output 1 (0) to A.

Further, the relationship between the comparison signal and the 90-degree shift signal of the comparison signal at the time of falling (rising) of the input reference signal is examined.
An 80 degree shift is detected and 1 is output to the output terminal DA.

In the phase switch 9, the output Vou of the VCO
t, output VoutQ + of a + 90-degree shifted waveform of Vout, output VoutB of a + 180-degree shifted waveform of Vout, output VoutQ- of a -90-degree shifted waveform of Vout, and outputs A, D and DA are input. When D is 1, this phase switch 9 changes Vout to VoutQ-
, VoutQ + are output as Vout, VoutB is output as VoutQ + , and VoutQ− is output as VoutB.

When A is 1, VoutQ- is set to Vout, Vout
As VoutQ + , VoutQ + as VoutB , and VoutB as VoutQ- . When DA is 1, VoutB is set to Vou
t, Vout is VoutB , VoutQ + is VoutQ-, VoutQ- is
Each is output as VoutQ + . When D, A, and DA are all 0, Vout is Vout, VoutQ + is VoutQ + , VoutQ +
outB is output as VoutB and VoutQ- is output as VoutQ- . Note that the terminals A, D, and DA do not become 1 at the same time.

As a result of this processing, the 90-degree shift signal and -9
From the 0-degree shift signal and the 180-degree shift signal, it is possible to change the phase of the comparison signal by 90 degrees, -90 degrees, or 180 degrees and to output the comparison signal, thereby shortening the pull-in time.

[0050]

As described above, according to the present invention, when the phase of the comparison signal deviates from the input reference signal by ± 90 degrees or more, the gain of the phase comparator is equivalently increased (lower).
Since the control is performed, there is an effect that the phase pull-in is speeded up. Further, when the phase of the comparison signal is shifted by ± 90 degrees or more or 180 degrees with respect to the input reference signal, the phase of the output signal (comparison signal) of the VCO is switched and controlled accordingly. This has the effect of speeding up the phase pull-in.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a change in gain of the phase comparator according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a block diagram of a phase comparator and an operation waveform diagram thereof .

FIG. 6 is an operation flow of the phase comparator.

FIG. 7 is a diagram illustrating an operation example of the frequency comparator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Phase comparator 2 Frequency comparator 3,4,8 Charge pump circuit 5 Loop filter 6 VCO 7 Detector with phase difference of 90 degrees or more 9 Phase switch

Claims (7)

(57) [Claims] 1. A phase error detecting means for detecting a phase error between an input reference signal and a comparison signal and outputting a phase error signal;
Frequency error detecting means for detecting a frequency difference between the input reference signal and the comparison signal and outputting a frequency error signal, and detecting ± 90 degrees deviation between the input reference signal and the comparison signal to ± 90 degrees A 90-degree shift detecting means for outputting a signal; a control voltage generating means for generating a control voltage in accordance with each output of the phase error detecting means, the frequency error detecting means, and the 90-degree shift detecting means; And a voltage-controlled oscillating means for outputting the comparison signal having a predetermined frequency. 2. When the input reference signal falls (rises), the comparison signal is 1 and the case where the 90 ° shift signal of the comparison signal is 0 is A. The comparison signal is 1 and the comparison signal is 90%. The case where the degree shift signal is 1 is B, the case where the comparison signal is 0 and the 90 degree shift signal of the comparison signal is 1 is C, and the comparison signal is 0 and the 90 degree shift signal of the comparison signal is 0. When the case is defined as D, the 90-degree shift detecting means checks the relationship between the comparison signal at the time of falling (rising) of the input reference signal and the 90-degree shift signal of the comparison signal, and D → D When the transition is made, a + 90-degree shift is detected and the above-mentioned + 90-degree shift signal is output. When the transition is made from A to A, a -90-degree shift is detected and the above-mentioned -90-degree shift signal is output. 2. The method according to claim 1, wherein PLL circuit. 3. The charge pump circuit having the outputs of the phase error detecting means, the frequency error detecting means, and the 90 ° shift detecting means as inputs, and integrating the respective outputs of the charge pump circuit. 3. The PLL circuit according to claim 2, further comprising an integrating circuit. 4. The charge pump circuit according to claim 1, wherein
4. The PLL circuit according to claim 3, wherein positive and negative currents are respectively output in accordance with the degree shift signal. 5. The 90-degree shift detecting means detects a 180-degree shift between the input reference signal and the comparison signal, and detects
3. The PLL circuit according to claim 2, wherein the PLL circuit is configured to output a zero-degree shift signal. 6. A relationship between the comparison signal at the time of falling (rising) of the input reference signal and a 90-degree shift signal of the comparison signal is examined, and when a transition is made from D to A or A to D, 180 degrees is obtained. 6. The P according to claim 5, wherein the shift is detected and the 180-degree shift signal is output.
LL circuit. 7. The phase of the comparison signal is shifted by ± 90 degrees or 18 degrees according to the ± 90 degrees shift signal or the 180 degrees shift signal.
7. The PLL circuit according to claim 6, further comprising switching means for switching to 0 degrees.