JP3355855B2 - Communication data check circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a real-time check of communication data to be received or relayed in a communication system requiring a high-reliable high-speed response such as a loop-type LAN for a distributed real-time control system for general industry. The present invention relates to a communication data check circuit installed in a computer.

[0002]

2. Description of the Related Art Conventionally, in a loop-type transmission line, a part of communication data arriving at a relay station may be rewritten in order to manage the transmission line. In this case, the transmitting station sequentially adds the bit values of each word of the communication data to be transmitted, and adds the obtained value as a check code to the end of the data, so if the relay station partially rewrites the communication data, Also, it is necessary to rewrite the check code in real time. However, since the relay station has a limited response time, it may be difficult to recalculate and rewrite the check code. Therefore, in general, a method that eliminates the need for rewriting the check code at the relay station by excluding words including bits of the data portion that are rewritten at the time of relay from the target of addition of the check code from the beginning is used. Had been.

[0003]

Therefore, the head word of the communication data contains a bit that can be rewritten at the time of relaying despite the fact that the destination station and transmission station information important for transmission control exist. The section word is excluded from the check code addition target. As a result, even if the destination station and transmitting station information may be corrupted due to noise or the like during transmission, the data corruption is not detected, and the reliability of the communication system is reduced accordingly. There was a problem of doing. The present invention has been made to solve the above problems, and an object of the present invention is to provide a communication data check circuit capable of improving reliability by increasing a check range in communication data. It is in.

[0004]

In order to achieve the above-mentioned object, according to the present invention, check data based on a value obtained by vertically adding bit values of all data except for a portion to be rewritten at the time of relaying is added to the end. Mask bit pattern output means for outputting a bit pattern for masking a rewrite bit portion for each word at a timing at which each word of the communication data is input at a relay station to which the communication data is input; A mask circuit for masking each word of the data using the mask bit pattern output from the mask bit pattern output means, a word value masked by the mask circuit and a word value output from the data latch circuit; And a word value output from the adder, and temporarily holds the word value output from the adder. A data latch circuit that sends the held word value to the adder at the timing when the masked word is input from the circuit, and adds at the timing when the added value for the check data at the end of the communication data is output from the adder. A determination circuit for determining whether or not all bits of the value are settled to 0 or 1, and outputting an error signal when not settled;

When a half adder having the same number of bits as a word is used in combination as an adder, a vertical parity check value is used as check data. When a full adder having the same number of bits as the number of bits forming a word is used as an adder, a sum check value is used as check data.

[0006]

According to the present invention, when the communication data to which the check data based on the value obtained by vertically adding the bit values of all the data except the portion to be rewritten at the time of relaying is inputted to the relay station is input to the relay station, Is output from the mask bit pattern output means at a timing at which each word constituting the word is input. Next, each word of the input communication data is masked by the mask circuit using the mask bit pattern output from the mask bit pattern output means.

Next, the adder adds the value of the word masked in the mask circuit and the value of the word output from the data latch circuit bit by bit.
Further, the data latch circuit temporarily holds the word value output from the adder. Further, at the timing when the masked word is input from the mask circuit to the adder, the word value held by the data latch circuit is sent to the adder. At the timing when the value obtained by adding the check data at the end of the communication data is output from the adder, the determination circuit determines whether or not all the bits of the added value have been set to 0 or 1, and the set value has not been set. In this case, an error signal is output. The occurrence of this error signal indicates that an abnormal value has occurred in the communication data.

When a half adder of the same number as the number of bits constituting a word is used in combination as an adder, a vertical parity check value is used as check data. When a full adder having the same number of digits as the number of bits constituting a word is used, a sum check value is used as check data.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the configuration of a relay station when the present invention is applied to a unidirectional loop transmission circuit. In the figure, reference numeral 1 denotes a station, and reference numerals 2 and 3 denote other stations with respect to the station 1. These stations 1 to 3 are connected in a loop by a transmission line 4 composed of an optical cable or the like. The communication data is transmitted through the transmission line 4 in the clockwise direction. The figure shows that the communication data transmitted by the other station 2 is received by the station 1 and the communication data transmitted by the station 1 is received by the other station 3. The station 1 includes an input buffer circuit 5, a FIFO memory 6, a bus 7, an output buffer circuit 8, a communication data check circuit 9, and a processor 10.

FIG. 3 is a diagram showing a format of communication data transmitted and received between the stations in FIG. Communication data 21
Is composed of a plurality of consecutive words 22 and word 2
2 is composed of n + 1 bits. Also, the hatched portions 22A, 22B, 2
2C indicates the position of a bit whose data content is rewritten when the communication data 21 is relayed, and the bit pattern in the hatched portion is a mask bit pattern used for mask processing described later. Further, check data is written in the last word 23. The content of the check data is a sum check value or a vertical parity check value obtained by adding the values of the bits of each word 22 excluding the hatched portions in the vertical direction.

FIG. 1 shows a communication data check circuit 9 shown in FIG.
FIG. 3 is a diagram showing an internal configuration of the device. As illustrated, the communication data check circuit 9 includes a transmission control unit 11 and a D-FF 1
2, decoder 13, AND gate 14, adder 15, data latch 16, comparator 17, AND gate 18
It is composed of The transmission control unit 11 transmits the communication data 2 to the AND gate 14 via the data buses Di0 to Din.
When 1 is input, in order from the first word 22,
The signal a indicating the type of the word is sent to the D-FF 12, and the latch clock c is set to D-FF at the word reception timing.
The data is sent to the FF 12 and the data latch 16. Further, the transmission control unit 11 sends the check enable signal b to the AND gate 18 at a predetermined timing after the last word 23 of the communication data 21 is input.

The D-FF 12 sends a type signal d to the decoder 13 based on the latch clock c. The type signal d is delayed by one word from the type signal a.
The decoder 13 converts the type signal d into a mask bit pattern and sends it to the AND gate 14 via the mask bit lines M0 to Mn. Here, the mask bit pattern is a bit array in which a bit at a position where data on a word is rewritten is set to one. The AND gate 14, which is a mask circuit, includes a data bus Di0-Din and a mask bit line M
For each value input from 0 to Mn, a logical product for each bit is obtained and output to the adder 15. In the AND gate 14, by masking the values of the data buses Di0 to Din, only the value of the bit at the position that is not rewritten is extracted.

Next, an adder 15 adds the value of the (n + 1) -bit input from the AND gate 14 and the value of the (n + 1) -bit similarly input from the data latch 16, and sends the result to the data latch 16 and the comparator 17. send. The data latch 16 outputs the data of the adder 1 based on the latch clock c.
After holding the added value from 5, it is sent to the adder 15 again at the timing of the next clock. In addition, the comparator 17
Checks the added value from adder 15 and checks each word 2
2 are sequentially added, and at the timing when the addition value for the last word 23 is finally output, it is checked whether or not all the bits of the addition value are settled to 0 or 1; If it has not been set to 1, an unsettling detection signal e is sent to the AND gate 18.

The AND gate 18 outputs an error signal f when both the check enable signal b and the irregularity detection signal e are input. This error signal f is sent to the processor 10 of FIG. 2, and error processing on the communication data 21 is started. Note that, as the adder 15, n +
When one half adder is used in combination, a vertical parity check value is used as check data of the last word 23. When an adder 15 of n + 1 digits is used as the adder 15, a sum check value is used as the check data of the last word 23.

In this embodiment, when the communication data 21 is input, each bit value is sequentially added while masking the bits of the changed data portion of each word 22, and the last word 23 is added. Immediately after that, the quality of the received communication data 21 is determined. That is, the communication data 21 is determined after the arrival of the last word 23 by the adder 15.
After the elapse of the circuit delay time. Therefore, when the processor 10 performs an error process before the next communication data arrives, the processing time has a margin because the pass / fail judgment is early.

Moreover, in this embodiment, since the check target is all data except for the part changed at the time of relaying, the reliability of the check result is improved accordingly. In particular,
Even if the word at the beginning of the communication data contains data to be rewritten at the time of relaying along with destination station and transmission station information important for transmission control, all data other than the rewritten data are to be checked. Even if information on the destination station and the transmitting station is damaged due to noise or the like, it can be reliably detected. The present invention can be similarly applied to communication systems other than the above-described unidirectional loop transmission line embodiment.

[0017]

As described above, according to the present invention, a mask bit pattern for excluding a portion rewritten at the time of relaying communication data in units of bits is prepared for each word, and a mask bit pattern is prepared for each word input. The final addition value is checked by sequentially adding the values of the words excluding the bit portion to be rewritten by the mask processing, so that the check range in the communication data is increased, and the check reliability is improved accordingly.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an internal configuration of a communication data check circuit according to an embodiment.

FIG. 2 is a block diagram illustrating a configuration of a unidirectional loop transmission circuit to which the embodiment is applied.

FIG. 3 is a diagram showing a format of communication data in the embodiment.

[Explanation of symbols]

 1 to 3 stations 4 Transmission path 5 Input buffer circuit 6 FIFO memory 7 Bus 8 Output buffer circuit 9 Communication data check circuit 10 Processor 11 Transmission control unit 12 D-FF 13 Decoder 14 AND gate 15 Adder 16 Data latch 17 Comparator 18 AND Gate 21 Communication data 22 Words 22A, 22B, 22C Rewriting part 23 Words Di0-Din Data bus M0-Mn Mask bit line

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/437 H04L 1/00

Claims (3)

(57) [Claims] 1. A relay station to which communication data to which a check data based on a value obtained by vertically adding a bit value of all data except for a part to be rewritten at the time of relay is added is inputted. Mask bit pattern output means for outputting a bit pattern for masking a rewrite bit portion for each word at a time when a word is input; and a mask output from the mask bit pattern output means for each word of the input communication data. A mask circuit that performs mask processing using a bit pattern, an adder that adds, for each bit, a word value masked by the mask circuit and a word value output from the data latch circuit, and an adder that is output from the adder. When the word value is temporarily held and the masked word is input from the mask circuit to the adder And a data latch circuit for sending the word value held by the summing to the adder, and at the timing when the added value for the check data at the end of the communication data is output from the adder, all bits of the added value are settled to 0 or 1. A communication data check circuit, comprising: a determination circuit that determines whether or not the data has been set, and outputs an error signal when the data is not settled. 2. The communication data check circuit according to claim 1, wherein an adder combining a half number of adders of the same number as the number of bits forming the word is used, and the vertical parity check value is used as the check data. circuit. 3. The communication data check circuit according to claim 1, wherein a full adder having the same number of bits as the number of bits forming the word is used as the adder, and the communication data check circuit uses a sum check value as the check data. circuit.