JP3347217B2 - Thin film transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a liquid crystal display device and a thin film transistor used for switching of an LSI such as an image sensor, a thermal head, and a memory, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG.
FIG. 10B is a plan view of a conventional thin film transistor used in the liquid crystal display device disclosed in Japanese Patent Application Publication No.
(A) shows an AA cross-sectional view. In the figure, 1 is a substrate made of glass, 2 is a gate electrode, 3 is a gate insulating layer, and 4 is an active layer region. Reference numeral 5 denotes a channel protective layer region which protects the active layer region 4 when the electrodes 7 and 8 described later are etched. Reference numeral 6 denotes an ohmic layer region. 7 is a source electrode and 8 is a drain electrode.

In a conventional method of manufacturing a thin film transistor, a 0.3 μm thick Cr film is formed on a substrate 1 by a sputtering method, and then patterned using a photoresist mask to form a gate electrode 2 and a gate wiring. Next, SiN is formed by CVD.
A gate insulating layer 3 is formed by forming a film having a thickness of 0.2 μm. Next, the i-type amorphous silicon layer is
An active layer is formed by forming a film having a thickness of μm. A channel protection layer region 5 made of a SiN film is formed thereon by a CVD method to a thickness of 0.2 μm and then patterned to form the channel protection layer region 5.

Then, an n-type amorphous silicon layer is formed to a thickness of 0.05 μm by a CVD method to form an ohmic layer 6. This is patterned to form an ohmic layer region 6 and an active layer region 4.

Next, a metal layer such as Cr is formed to a thickness of 0.1 mm by a sputtering method.
A 1 μm-thick film is formed and patterned to form a source electrode 7 and a drain electrode 8. Next, a portion between the source electrode 7 and the drain electrode 8 in the ohmic layer region 6 is removed by etching using the source electrode 7 and the drain electrode 8 as a mask.

Next, the operation will be described. FIG. 10 (a)
10B, the current injected from the source electrode 7 through the ohmic layer region 6 into the active layer region 4 is such that when a voltage higher than the threshold voltage is applied to the gate electrode 2, the current is Crosses the active layer region 4 again and reaches the drain electrode 8 via the ohmic layer region 6 through a channel 12 (FIG. 14 described later) formed on the gate electrode 2 side of the active layer region 4. When the voltage of the gate electrode 2 is lower than the threshold, the resistance of the active layer region 4 is high, and almost no current flows.

FIG. 11 is an equivalent circuit of a thin film transistor substrate of a liquid crystal display device. In the figure, 9 is a thin film transistor, 10 is a liquid crystal display element, 7 is a source electrode, 2 is a gate electrode, 8 is a drain electrode, and 11 is a common electrode.

FIG. 12 is a voltage waveform diagram showing the operation of a thin film transistor used in a liquid crystal display device. FIG.
11A shows the gate voltage V _G applied to the gate electrode 2 in FIG. 11, FIG. 12B shows the source voltage V _S applied to the source electrode 7 in FIG. 11, and FIG. 12C shows the drain voltage in FIG. the drain voltage _{V D} at the electrode 8. FIG. 12D shows a common electrode voltage V applied to the common electrode 11 of FIG.
_COM .

The operation of the liquid crystal display will now be described. The liquid crystal display device 10 is displayed by the liquid crystal molecules are deflected the transmittance varies due to the potential difference of the common electrode voltage V _COM voltage of the device across, i.e. the drain voltage V _D. Typically the drain voltage V _D varies in response to the signal, the common electrode voltage V _COM D _C voltage fixed is applied.

[0010] The image signal voltage is provided by a source electrode 7. When the gate voltage V _G is applied the source voltage V _S is the first field is an image display period is V _G ON, the signal voltage is displayed is applied to the liquid crystal element as the drain voltage V _D with respect to the common electrode voltage V _COM. The liquid crystal display element 10 is equivalently a liquid crystal capacitance Clc.
During the field, the signal voltage is held in this capacitance. In this manner, when the elements on the entire screen are charged with the signal voltages, display as an image becomes possible.

In the second field, the source electrode 7
Are applied to each other, and the gate voltage V _{G of} each pixel is applied.
There charge from the liquid crystal capacitance Clc is drawn to the source electrode 7 display is ended when the V _G ON.

FIG. 13 shows an equivalent circuit of a thin film transistor.
FIG. 14 is a diagram for explaining the effect of the structure of the conventional thin film transistor shown in FIG. 10 on the operation of the liquid crystal display device. In FIG. 13, Cgd is the capacitance due to the overlapping portion between the gate electrode 2 and the drain electrode 8, and is the capacitance due to the cross hatched portion 8a and 2b in FIG. 14B. Cd
s is a portion 7 where the drain electrode 8 and the source electrode 7 are opposed
a, 8a. Cgs is an overlapping portion of the gate electrode 2 and the source electrode 7, and is denoted by 7a and 2a in FIG.
Shows the capacity between a.

Clc is a liquid crystal capacitance of the liquid crystal display element, and 11 is a common electrode. Rsc extends from the source electrode 7 through the ohmic layer region 6 and across the active layer region 4 to the channel 12.
, And similarly, R _DC is a resistance value between the drain electrode 8 and the channel 12. Here the channel is shown at 12 in FIG. 14 (b), the gate voltage _{V G V} G O
When N, the current path is formed in the active layer region 4.

[0014] If there is capacity Cgd overlap between the gate electrode 2 and the drain electrode 8, the gate voltage _{V G} is the drain voltage V
Bonded through _D and Cgd, change in the gate voltage △ _{V G} acts to vary the drain voltage _{V D} △ Vgd only. Here is always negative in _{△ V G = V G OFF-} V G ON. ΔVgd is given by (Equation 1).

[0015]

(Equation 1)

The source voltage is a signal voltage V _S is the drain voltage V is used inverted so the polarity usually every field whether positive or negative signal voltage as shown in FIG. 16 (c)
_D is reduced by ΔVgd shown in the above (Equation 1), and the drain voltage V _D applied to the liquid crystal display element is reduced.
Low only △ Vgd by the source voltage _{V S} is. That is, it acts as if the center voltage of the AC signal voltage was shifted downward by ΔVgd.

ΔVgd depends on the capacitance Cgd which overlaps between the gate electrode 2 and the drain electrode 8 as shown in (Equation 1). Since Cgd has voltage dependency, the drain voltage rises and falls for each signal.

As shown in FIGS. 13 and 14,
If there is a resistance value R _SC between the source electrode 7 and the channel 12 and a resistance value R _DC between the drain electrode 8 and the channel 12,
Applied source voltage V _S results in a voltage drop before reaching the drain electrode 8. Thus Figure 12 since the gate voltage _{V G} as shown in FIG. 12 (a) becomes _V G ON
The rising waveform G (1) of the drain voltage shown in FIG. Therefore, a display of a sufficient density cannot be obtained at the time of rising.

[0019]

Since the conventional thin film transistor is constructed as described above, the drain voltage shifts downward by the voltage .DELTA.Vgd depending on the signal voltage due to the overlap capacitance Cgd between the gate and drain electrodes. Is done.

The rise of the drain voltage is delayed by the resistances R _SC and R _DC between the gate electrode or the source electrode and the channel 12 in the i-type amorphous silicon layer which is the active layer region, and it takes time to reach a predetermined voltage. However, there is a problem that the screen flickers and the image becomes dark and light.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a thin film transistor which can reduce the fluctuation of the drain voltage due to the combination of the gate voltage and the drain voltage and improve the rising characteristics of the drain voltage. It is an object to provide a structure and a manufacturing method thereof.

[0022]

Means for Solving the Problems The thin film transistor according to the first invention, a gate electrode formed on the base plate, a gate insulating layer formed on the gate provided on the gate insulating layer An active layer region formed of a silicon layer having the same width as the electrode width; first and second ohmic layer regions provided to be connected to both outer side walls of the active layer region;
And a source and drain electrode portion made of a refractory metal silicide layer provided to be connected to both outer walls of the second ohmic layer region, respectively, wherein the first ohmic layer region, the second ohmic layer region, Are set to have the same length as the gate electrode width.

A thin film transistor according to a second aspect of the present invention is a thin film transistor, comprising: a gate electrode formed on a substrate; a gate insulating layer formed thereon; an active layer region formed thereon; On both outer sides of the electrode width, first and second ohmic layer regions which are the same length as the gate electrode width and are formed apart from each other are formed.

A source electrode wiring and a drain electrode connecting portion formed on the gate insulating layer apart from the gate electrode; a source electrode extending from the first ohmic layer region to the source electrode wiring; And a drain electrode extending from the second ohmic layer region to the drain electrode connection portion.

In the manufacturing method according to the third invention, an opaque gate electrode is formed on a transparent substrate, and a gate insulating layer is formed thereon. Next, an active layer and an ohmic layer made of a silicon layer are successively formed on the gate insulating layer and then patterned to form an active layer region and an ohmic layer region.

Further, on the gate insulating layer, a source electrode wiring and a drain electrode connecting portion are formed by an opaque metal layer on both sides apart from the gate electrode. Next, a transparent conductive layer is formed on the entire surface, a negative resist layer is formed thereon, and light is irradiated from the back surface of the transparent substrate to form a negative resist using the gate electrode, the source electrode wiring, and the drain electrode connection portion as a mask. The layer is developed to form a negative resist pattern. Using the negative resist pattern as a mask, the transparent conductive layer is etched to form a source electrode and a drain electrode.

A thin film transistor according to a fourth aspect of the present invention provides a gate electrode formed on a substrate, a gate insulating layer formed thereon, an active layer region formed thereon, and a gate electrode formed on the active layer region. A channel protection layer region having the same width as the gate electrode width is formed.

A first and a second ohmic layer regions formed on both sides of the active layer region so as to cover an end of the channel protection region, and formed on the gate insulating layer at a distance from the gate electrode. Source and drain electrode connections, a source electrode extending from the first ohmic layer region to the source electrode wiring, and a drain extending from the second ohmic layer region to the drain electrode connection And an electrode.

[0029]

SUMMARY OF] According to the thus constructed thin-film transistor as in the first invention, the source connected to the thickness portion of the active layer area,
Since the drain electrode portion is provided, R _SC , R _DC
Can be reduced. Further, since the first and second ohmic layers are provided between the active layer region and the source and drain electrode portions made of the refractory metal silicide layer,
It works in the direction of lowering the resistance at the connection with the active layer region.

In the thin film transistor according to the second aspect of the present invention, the source and drain electrodes made of the transparent conductive layer are formed on the gate electrode outside the gate electrode width, so that the gate electrode overlaps the source and drain electrodes. And Cgd can be reduced.

According to the manufacturing method of the third invention, the transparent conductive film formed on the ohmic layer is formed by using the opaque gate electrode, source electrode wiring, and drain electrode connection portions formed on the transparent substrate as a mask. The source and drain electrodes are formed outside the width of the gate electrode by patterning by exposing the negative resist to the back surface, so that the gate electrode and the source and drain electrodes are prevented from overlapping.

According to the structure of the thin film transistor according to the fourth aspect of the present invention, the source and drain electrodes made of the transparent conductive layer are formed on the gate electrode outside the gate electrode width, so that the gate electrode and the source and drain electrodes are formed. Cgd can be reduced by eliminating the overlap between them.

[0033]

[Embodiment 1] FIG. 1 shows an embodiment of the structure of the thin film transistor of the first invention. FIG. 1A is a plan view thereof, and FIG.
It is an AA sectional view of (a). In the figure, 1, 2, 3,
7 and 8 are the same as those of the conventional apparatus, and thus the description thereof is omitted. Here, the substrate 1 includes a transparent substrate such as a glass substrate and an opaque substrate such as silicon. An active layer region 13 is formed on the gate insulating layer 3 and on the gate electrode 2 with the same width as the gate electrode 2. The active layer region is a silicon layer of amorphous silicon, polysilicon, crystalline silicon, or the like.

Numeral 14 denotes a channel protective layer region which is formed inside the gate electrode width on the active layer region 13 and has the same width as the gate electrode 2. Reference numerals 15 and 16 denote source and drain electrode portions, which are connected to both outer walls of the film thickness portion of the active layer region 13. The source and drain electrode portions are, for example, Cr,
It is formed of a metal silicide such as a high melting point metal such as W, Ti, and Ta. This further includes, for example, Al, Al alloys, Al
It is connected to both electrodes 7 and 8 of low resistance such as Si-doped polysilicon and becomes source and drain electrodes 7 and 8.

Next, the operation of the thin film transistor will be described. When the gate voltage V _G a voltage is applied between the source electrode 7 and the drain electrode 8 becomes V _G ON, a channel is formed on the gate electrode 2 side of the active layer region 13 this transistor becomes conductive.

By employing the structure of the present invention, the distance between the source electrode portion 15 and the drain electrode portion 16 is made equal to the width of the gate electrode 2, and the source and drain electrode portions 15, 1
6 is formed on the gate electrode 2 just outside the gate electrode width, so that the gate electrode 2 and the source electrode 1
5, there is no overlap with the drain electrode portion 16, and thus Cgd is reduced.

Further, since the source electrode portion 15 and the drain electrode portion 16 are formed so as to be connected to the side walls in the thickness direction of the active layer region 13, the distance between the source and drain electrode portions and the channel 12 becomes the shortest, and R _SC , R _DC are reduced.

FIG. 2 shows the effect of the present invention. FIG.
12 shows one frame of the drain voltage waveform of the liquid crystal display device shown in FIG. As described above, the overlap between the gate electrode 2 and the drain electrode portion 16 is eliminated and C
Since gd is reduced, the shift ΔVgd of the drain voltage of the conventional device shown in FIG.
Bruno △ Vgd (2), and the most shift without a stable drain voltage _{V D} is obtained. Further, by adopting this structure, the source electrode portion 15 and the drain electrode portion 16 are formed.
FIG. 1 shows that the resistances R _SC and R _DC between the channels have been reduced.
2 rising characteristics of slow drain voltage V _D shown in (c) G (1) fast rise characteristics are as G (2) of FIG. 2 is obtained.

Embodiment 2 FIG. Next, one embodiment of a method of manufacturing a thin film transistor according to the second invention, which is performed to obtain the structure of the first invention, will be described with reference to FIGS. In FIG. 3, a 0.3 μm-thick Cr film is formed on a transparent substrate 1 such as a glass substrate by a sputtering method, and then patterned using a photoresist mask to form a gate electrode 2 and a gate wiring.

Next, in FIG. 3B, a gate insulating layer 3 is formed by depositing a 0.2 μm SiN film or a Si ₃ N ₄ film by the CVD method. Subsequently, as shown in FIG.
An active layer 17 made of an i-type amorphous silicon layer is formed to a thickness of 0.1 μm by the VD method. Further, as shown in FIG. 2D, a channel protection layer 18 made of a SiN film is formed to a thickness of 0.2 μm by the CVD method.

Next, as shown in FIG. 3E, a positive resist layer 19 is applied to the entire surface, and 5 to 10 mj / cm ² light is irradiated from the back surface of the glass substrate 1 using the gate electrode 2 as a mask. The layer 19 is developed to form a positive resist pattern 20.

Next, as shown in FIG. 4A, using the resist pattern 20 as a mask, the SiN film serving as the channel protective layer 18 is etched by SF ₆ or CF ₄ plasma, and as shown in FIG. The channel protection layer region 14 is formed.

Next, as shown in FIG. 4C, the entire surface of the substrate was formed by sputtering at a substrate temperature of 200.degree.
And a high melting point metal layer 21 made of a high melting point metal silicide layer.
5 and 16 are formed. Next, the unreacted portions of the refractory metal layer 21 at portions where silicide is not formed, such as on the channel protective layer region 14, are removed by etching. A source electrode portion 15 and a drain electrode portion 16 made of the refractory metal silicide layer on both sides of the active layer region 13 thus formed are formed. Thereafter, source and drain electrodes 7 and 8 are formed (FIG. 4E), and a thin film transistor is obtained.

In this embodiment, an insulating layer such as SiN is used as the channel protective layer region 14. However, a transparent conductive layer such as ITO (indium tin oxide) which does not form a silicide may be used.

According to the method of manufacturing a thin film transistor according to the present invention, since the channel protection layer region 14 is formed by back exposure using the gate electrode 2 on the transparent substrate 1 as a mask, the channel protection layer region has the same width as the gate electrode width. 14 can be formed.

Using the channel protective layer region 14 as a mask, a source electrode portion 15 and a drain electrode portion 1 made of a refractory metal silicide layer are formed on the silicon layer as the active layer 17.
6, the source electrode portion 15 and the drain electrode portion 16 made of the refractory metal silicide layer can be formed outside the gate electrode width of the active layer region 13.

As a result, on the gate electrode 21, the distance between the source electrode portion 15 and the drain electrode portion 16 is formed to have the same length as the gate electrode width, and the source and drain electrode portions 15, 16 are formed on both sides of the gate electrode width. Is formed, so that the gate electrode 2
Cgd can be reduced, and there is an effect of reducing ΔVgd (2) shown in FIG. 2B.

Embodiment 3 FIG. FIG. 5 is a sectional view showing the structure of an embodiment of the thin film transistor according to the third invention. This plan view is the same as FIG. A gate electrode 2 formed on a substrate 1, a gate insulating layer 3 formed on the gate electrode 2, an active layer region 13 having the same width as the gate electrode formed thereon; First and second ohmic layers 22a, 22b formed respectively on both outer side walls of the source electrode portion 15 and drain electrode portion connected to the first and second ohmic layers 22a, 22b, respectively. 1
6 is provided. This structure is the same as the device of the first invention except that first and second ohmic layers 22a and 22b are added. The first and second ohmic layers 22a and 22b are formed by implanting phosphorus or boron into an i-type amorphous silicon layer of the same material as the active layer region 13, and have a width of about 0.1 to several μm. is there.

By adopting the structure of the present invention, basically, as in the first invention, Cgd is reduced, and R _SC and R _DC are reduced.
Can be reduced, and the effect shown in FIG. Further, by providing the first and second ohmic layers 22a and 22b between the active layer region 13 and the source electrode portion 15 and between the active layer region 13 and the drain electrode portion 16, respectively, the resistance between the source and the drain is further increased. Can be lowered.

Embodiment 4 FIG. FIG. 6 shows the structure of one embodiment of the thin film transistor according to the fourth invention. A gate electrode 2 formed on a substrate 1;
The gate insulating layer 3 formed thereon, the active layer region 4 formed thereon, and the outside of the gate electrode width on the active layer region 4 are separated from each other by the same length as the gate electrode width. The formed first and second ohmic layer regions 60a,
60b are formed.

Further, the source electrode wiring 70 and the drain electrode connecting portion 36 formed on the gate insulating layer 3 so as to be separated from the gate electrode 2, and extend from the first ohmic layer region 60 a to the source electrode wiring 70. And a drain electrode 38 extending from the second ohmic layer region 60b to the drain electrode connection portion 36.
And a configuration including

The feature of this structure is that the first and second ohmic layer regions 60a, 60b are separated from each other by the same width as the gate electrode width on the active layer region 4 just above the electrode width of the gate electrode 2.
Is formed, and the first ohmic layer region 60a is formed.
, The drain electrode 38 extending from the source electrode 37 and the second ohmic layer region 60b to the drain electrode connecting portion 36.

According to the structure of the present invention, the gate electrode 2 and the source / drain electrodes 37 and 38 do not overlap and Cdg
Can be reduced.

Embodiment 5 FIG. FIGS. 7 and 8 show a sixth embodiment for obtaining the structure of the fifth invention.
An embodiment of a method for manufacturing a thin film transistor according to the present invention will be described. As shown in FIG. 7A, a metal layer such as Cr is formed on a glass substrate 1 by sputtering and patterned to form a gate electrode 2. Next, S
An iN film is formed, and a gate insulating film 3 is formed. Then CV
The active layer 17 made of an i-type amorphous silicon layer is formed by the method D, and then the ohmic layer 34 made of an n-type amorphous silicon layer is formed.

Next, as shown in FIG. 7B, the active layer 17 and the ohmic layer 34 made of the i-type amorphous silicon layer are patterned to form the ohmic layer region 6 and the active layer region 4. Next, as shown in FIG. 7C, a high melting point metal film 21 made of, for example, Cr is formed on the entire surface by sputtering, and is patterned and separated from the gate electrode 2 as shown in FIG. Source wiring 7
0 and the drain electrode connecting portion 36 are formed.

Next, as shown in FIG. 8A, a transparent conductive layer 41 of ITO (indium tin oxide) is formed thereon. Further, as shown in FIG. 8B, a negative resist layer 42 is applied thereon. Next, back exposure is performed from below, and the negative resist layer 42 is developed using the opaque gate electrode 2, the source electrode wiring 70 and the drain electrode connecting part 36 as a mask, and the negative resist patterns 43 and 44 as shown in FIG. To form Next, as shown in FIG. 8D, the transparent conductive layer 41 is etched using the negative resist patterns 43 and 44 as a mask, and the source electrode 3 is etched.
7 and a drain electrode 38 are formed. Although not shown in FIG. 8D, the ohmic layer region 6 between the source and drain electrodes is removed by etching using the source and drain electrodes as a mask to form the first and second ohmic layer regions 60.
a, 60b are formed, and the thin film transistor is completed.

According to the manufacturing method of the present invention, the transparent electrode formed on the ohmic layer region is formed by using the opaque gate electrode 2, the source electrode wiring 70, and the drain electrode connecting portion 36 formed on the transparent substrate 1 as a mask. Since the negative resist layer applied to the surface of the conductive film 41 was back-exposed and patterned to form source and drain electrodes, the source and drain electrodes were formed outside the gate electrode width, and the gate electrode 2 and A structure in which the source 37 and the drain electrode 38 do not overlap can be obtained.

Embodiment 6 FIG. FIG. 9 shows the structure of an embodiment of the thin film transistor according to the sixth invention. FIG. 9A is a plan view, and FIG.
It is an AA sectional view of (a). In the figure, reference numeral 5 denotes a channel protective layer region. The rest of the configuration is exactly the same as the structure shown in FIG.

The structure of the thin film transistor is such that a gate electrode 2 formed on a transparent substrate 1, a gate insulating layer 3 formed thereon, and an active layer region 4 formed thereon.
And a channel protection layer region 5 having the same width as the gate electrode formed on the active layer region inside the gate electrode width.

Further, the first and second portions formed on both sides of the active layer region 4 so as to cover the ends of the channel protection region.
Ohmic layer regions 60a and 60b and gate insulating layer 3
An opaque source electrode wiring 70 and a drain electrode connecting portion 36 formed above and separated from the gate electrode 2; a source electrode 37 extending from the first ohmic layer region 60a to the source electrode wiring 70; Ohmic layer area 6
0b to the drain electrode connecting portion 36.

According to the structure of the present invention, since the source and drain electrodes 37 and 38 are formed in the outer portion of the gate electrode vertically above the gate electrode 2, there is no overlap between the gate electrode and the source and drain electrodes. Cgd can be reduced, and the fluctuation of the gate voltage can be prevented from affecting the drain voltage.

[0062]

The present invention has the following effects because it is configured as described above. The effect according to the first invention is that C gd can be reduced, and R _SC and R _DC can be reduced. Further, since the first and second ohmic layers 22a and 22b are provided between the active layer region 13 and the source and drain electrode portions 15 and 16, respectively, the connection resistance between the source and drain electrode portions 15 and 16 and the channel is reduced, and A transistor having a high speed can be formed.

The effect of the second invention is that the first and second ohmic layer regions 60a, 60 are separated from the active layer region 4 just above the electrode width of the gate electrode 2 by the same length as the gate electrode width.
b is formed, and the first ohmic layer region 60
Since the source electrode 37 and the drain electrode 38 are formed from the a and the second ohmic layer region 60b, respectively, the gate electrode 2 does not overlap the source and drain electrodes 37 and 38, and Cdg can be reduced.

The effect according to the third invention is that the opaque gate electrode 2 and the source electrode wiring 7 formed on the transparent substrate 1
0, using the drain electrode connection portion 36 as a mask, the negative resist layer applied to the surface of the transparent conductive layer 41 formed on the ohmic layer region was back-exposed and patterned to form the source and drain electrodes 37 and 38. Source and drain electrodes 37 and 38 which do not overlap with the gate electrode 2
Can be formed.

The effect according to the fourth invention is that the source and drain electrodes 37 and 38 are formed in the outer portion of the gate electrode vertically above the gate electrode 2, so that the gate electrode 2
Thus, Cgd can be reduced without overlapping between the source and drain electrodes 37 and 38, and fluctuation of the gate voltage does not affect the drain voltage.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a thin film transistor according to an embodiment of the first invention of the present application.

FIG. 2 is a diagram illustrating an effect of the first invention of the present application.

FIG. 3 is a diagram showing a manufacturing process of a thin film transistor according to an embodiment of the second invention of the present application. (Part 1)

FIG. 4 is a diagram showing a manufacturing process of a thin film transistor according to an embodiment of the second invention of the present application. (Part 2)

FIG. 5 is a diagram showing a structure of a thin film transistor according to an embodiment of the third invention of the present application.

FIG. 6 is a diagram showing a structure of a thin film transistor according to an embodiment of the fourth invention of the present application.

FIG. 7 is a diagram showing a manufacturing process of a thin film transistor according to an embodiment of the fifth invention of the present application. (Part 1)

FIG. 8 is a diagram showing a manufacturing process of a thin film transistor according to an embodiment of the fifth invention of the present application. (Part 2)

FIG. 9 is a view showing a structure of a thin film transistor according to an embodiment of the sixth invention of the present application.

FIG. 10 is a diagram showing a structure of a conventional thin film transistor.

FIG. 11 is a diagram illustrating a circuit configuration of a liquid crystal display device using a thin film transistor.

FIG. 12 is a diagram showing operation waveforms of a thin film transistor used in a liquid crystal display device.

FIG. 13 is a diagram illustrating an equivalent circuit of a thin film transistor.

FIG. 14 is a diagram for explaining a problem of a conventional thin film transistor.

[Explanation of symbols]

Reference Signs List 1 substrate, 2 gate electrode, 3 gate insulating layer, 4 active layer region, 5 channel protective layer region, 6 ohmic layer region, 7 source electrode, 13 active layer region, 14 channel protective layer region, 15 source electrode section, 16 drain Electrode part, 17 active layer (silicon layer), 18 channel protective layer, 19 positive resist layer, 20 positive resist pattern, 21 high melting point metal layer, 22a first ohmic layer, 22b second ohmic layer, 36 drain electrode connection Part, 37 source electrode, 38 drain electrode, 4
1 transparent conductive layer, 42 negative resist layer, 43, 44
Negative resist pattern, 60a first ohmic layer,
60b Second ohmic layer, 70 Source electrode wiring.

Continued on the front page (72) Inventor, Naoki Nakagawa 997, Miyoshi, Nishigoshi-cho, Kikuchi-gun, Kumamoto Prefecture, Japan Inside Advanced Display Co., Ltd. ) Inventor Tatsuya Nakayama 997 Miyoshi, Nishi-Koshi-cho, Kikuchi-gun, Kumamoto Prefecture, Japan Advanced Display Co., Ltd. 4-94133 (JP, A) JP-A-5-211166 (JP, A) JP-A-61-278163 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 G02F 1/1368

Claims (4)

(57) [Claims] 1. A substrate, a gate electrode formed on the substrate, a gate insulating layer formed on the gate electrode, and a silicon layer provided on the gate insulating layer and having the same width as the gate electrode. an active layer region comprising at a first and second ohmic layer region arranged in connection with both outer walls of the active layer region, respectively to the first and second outer sides walls of the ohmic layer region A source electrode portion and a drain electrode portion formed of a refractory metal silicide layer provided in a connected manner, wherein the first ohmic layer region and the second
A thin film transistor, wherein the distance from the ohmic layer region is equal to the width of the gate electrode. 2. A substrate, a gate electrode formed on the substrate, a gate insulating layer formed on the gate electrode, an active layer region formed on the gate insulating layer, and the active layer region First and second ohmic layer regions formed on both outer sides of the upper gate electrode width at the same length as the gate electrode width and separated from each other; and formed on the gate insulating layer at a distance from the gate electrode. A source electrode wiring and a drain electrode connection, a source electrode extending from the first ohmic layer region to the source electrode wiring, and a drain electrode extending from the second ohmic layer region to the drain electrode connection. And a thin film transistor. 3. A first step of forming an opaque gate electrode on a transparent substrate, a second step of forming a gate insulating layer on the gate electrode, and a silicon layer on the gate insulating layer. A third step of forming an active layer region and an ohmic layer region by successively forming and patterning an active layer and an ohmic layer, and forming an opaque metal layer on the gate insulating layer away from the gate electrode and outside the gate electrode A fourth step of forming a source electrode wiring and a drain electrode connection part according to the above, a fifth step of forming a transparent conductive layer on the entire surface, and a sixth step of forming a negative resist layer on the transparent conductive layer,
A seventh step of irradiating light from the back surface of the transparent substrate to develop the negative resist layer using the gate electrode and the source electrode wiring and the drain electrode connection as a mask to form a negative resist pattern; Forming a source electrode and a drain electrode by etching the transparent conductive layer using the pattern as a mask to form a source electrode and a drain electrode. 4. A substrate, a gate electrode formed on the substrate, a gate insulating layer formed on the gate electrode, an active layer region formed on the gate insulating layer, and the active layer region A channel protection layer region having the same width as the gate electrode formed thereon, and first and second ohmic layers formed on both sides of the active layer region so as to cover the ends of the channel protection region. A region, a source electrode wiring and a drain electrode connecting portion formed apart from the gate electrode on the gate insulating layer, a source electrode extending from the first ohmic layer region to the source electrode wiring, A drain electrode extending from the second ohmic layer region to the drain electrode connection.