JPH0945930A - Thin film transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure sufficient on-current of a thin film transistor while suppressing the off-current. SOLUTION: A thin film transistor is provided with a laminated structure formed by laminating a semiconductor thin film 1, a gate electrode 2 provided with a prescribed pattern and a gate insulating film 3 between the film 1 and the electrode 2. The semiconductor thin film 1 is provided with a channel area 4, a high concentration impurity area 5 and a low concentration impurity area 6. The semiconductor thin film 1 is provided with an internal part IN included in the pattern of the gate electrode 2 and an external part OUT positioned outside the pattern. The channel area 4 is formed on the internal part IN, and the high concentration impurity area 5 is formed on the external part OUT. The low concentration impurity area 6 is positioned between the channel area 4 and the high concentration impurity area 5, and at least a part of the area 6 is included in the internal part IN. The on current is prevented from reducing by modulating the low concentration impurity area 6 by gate potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor integrated in a thin film semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a structure and a manufacturing method for suppressing an off current of a thin film transistor and ensuring a sufficient on current.

[0002]

2. Description of the Related Art In recent years, large-area integrated circuits have been actively researched for downsizing and thinning of electronic devices. For example, elements such as an active matrix liquid crystal television, a contact type line sensor, and a thermal printer head have been developed. A thin film transistor using a semiconductor thin film such as polycrystalline silicon as an active layer is considered to be optimal for the development of these devices. Various improvements have been attempted in order to fabricate a device in a polycrystalline silicon thin film. In general, a polycrystalline film, which is considered to be an aggregate of small-grain silicon, has a large number of dangling bonds, which makes electrical characteristics inferior to those of single-crystal silicon transistors. There is. It has been pointed out that when a polycrystalline silicon thin film is used for the active layer of a MOS transistor, the breakdown voltage of the drain junction is low and the junction leakage current (off current) is large. In the drain junction, the leak current at the Si / SiO ₂ interface in the weak electric field is dominated by the tunnel current in the strong electric field exceeding 2 × 10 ⁵ V / cm.

[0003]

An offset gate structure has been proposed in order to increase the breakdown voltage of a thin film transistor and reduce the leakage current. The thin film transistor has a laminated structure in which a semiconductor thin film made of polycrystalline silicon, a gate electrode having a predetermined pattern, and a gate insulating film interposed between the two are stacked. In the offset gate structure, a channel region, a high concentration impurity region and a low concentration impurity region are formed in the semiconductor thin film. The high-concentration impurity regions are located on both sides of the channel region and function as a source region and a drain region. The low-concentration impurity region is interposed between the channel region and the drain region and / or between the channel region and the source region, and is a so-called LDD region (Lightly Doped D).
It is called a rain). However, this LDD
Although the leakage current can be remarkably suppressed by providing the region, the drive current (ON current) is decreased on the contrary. Conventional LD
Since the D region is outside the gate electrode and is not subject to modulation by the gate potential, the ON current is reduced accordingly. In particular, when the LDD region is provided on the source region side, the on-current is significantly reduced. Problems to be solved by such conventional techniques include, for example, the Institute of Electronics, Information and Communication Engineers, C-II Vol.
73-C-II No. 4 pp. 277-283 199
Apr. 0, "Design of drain junction in polycrystalline silicon MOSFET".

[0004]

The following means have been taken in order to solve the above-mentioned problems of the prior art. That is, the thin film transistor according to the present invention basically has a semiconductor thin film, a gate electrode having a predetermined pattern, and a gate insulating film interposed therebetween. A channel region in the semiconductor thin film;
A high concentration impurity region and a low concentration impurity region are provided. This semiconductor thin film is divided into an inner part included in the pattern of the gate electrode and an outer part located outside the pattern. The channel portion is formed in the inner portion, and the high concentration impurity region is formed in the outer portion. Characteristically, the low-concentration impurity region is located between the channel region and the high-concentration impurity region, and at least a part thereof is included in the inner portion. Preferably, the low-concentration impurity region has an impurity concentration of 10 ¹⁶ to 10 ¹⁸ / cm ³ . or,
The low-concentration impurity region may have a gradient in impurity concentration along the horizontal direction from the channel region to the high-concentration impurity region. Alternatively, the low-concentration impurity region may have an impurity concentration having a gradient along the depth direction of the semiconductor thin film. Preferably, the high concentration impurity regions are located on both sides of the channel region, and the low concentration impurity regions are provided between at least one of the high concentration impurity regions and the channel region.

In another aspect of the present invention, a thin film transistor is manufactured by the following steps. First, a first step of forming a gate electrode having a predetermined pattern on an insulating substrate is performed. Then, a second step of forming a gate insulating film on the gate electrode is performed. Then, a third step of forming a semiconductor thin film on the gate insulating film is performed. Further, a first impurity blocking film is formed on the semiconductor thin film with a pattern that is inside the pattern of the gate electrode. Thereafter, a fifth step of doping the semiconductor thin film with impurities at a low concentration is performed using the first impurity blocking film as a mask. Further, a sixth step of forming the second impurity blocking film with a pattern including the pattern of the first impurity blocking film and having a larger area than that is performed. Finally, a seventh step of doping the semiconductor thin film with a high concentration of impurities is performed using the second impurity blocking film as a mask. Preferably, the fourth step includes a backside exposure process of performing overexposure from the backside of the transparent insulating substrate using the gate electrode as a mask and setting the pattern of the first impurity blocking film on the surface of the insulating substrate. Further preferably, the sixth step includes a back surface exposure process of exposing the back surface of the transparent insulating film using the gate electrode as a mask and setting a pattern of the second impurity blocking film on the surface of the insulating substrate. In the fifth step, the impurity ions are accelerated in the electric field to dope the semiconductor thin film. Similarly, in the seventh step, impurity ions are subjected to electric field acceleration to dope the semiconductor thin film. Alternatively, in the seventh step, doped silicon containing a high concentration of impurities may be superposed on the semiconductor thin film to be irradiated with laser light to dope the impurities. More preferably, the fourth
In the process, a first impurity blocking film is formed using a thermally deformable photoresist, and in the sixth process, the photoresist is reflow-heated to expand the pattern of the first impurity blocking film and convert it into a second impurity blocking film. It may be a method of doing.

The present invention includes a display thin film semiconductor device. In this display thin film semiconductor device, a pixel electrode, a thin film transistor for switching and driving the pixel electrode, and a thin film transistor included in a drive circuit for driving the thin film transistor are integrally formed on the same substrate. At least the thin film transistor included in the driving circuit has a stacked structure in which a semiconductor thin film, a gate electrode having a predetermined pattern, and a gate insulating film interposed therebetween are stacked, and the semiconductor thin film has a channel region and a high concentration impurity. A region and a low concentration impurity region are provided. The semiconductor thin film is divided into an inner part included in the pattern of the gate electrode and an outer part located outside the pattern. The channel portion is formed in the inner portion,
The high-concentration impurity region is formed on the outer portion. Characteristically, the low-concentration impurity region is located between the channel region and the high-concentration impurity region, and at least a part of the low-concentration impurity region is included in the inner portion.

In a thin film transistor using a semiconductor thin film such as polycrystalline silicon as an active layer, it is important to suppress off current (leakage current), and an LDD structure is adopted. However, when the LDD structure in which the low-concentration impurity region (LDD region) is interposed between the channel region and the high-concentration impurity region, the on-current (driving current) is reduced. In view of this point, the present invention realizes a novel LDD structure that suppresses off current without lowering on current. In the conventional LDD structure, the LDD region is on the outer side of the gate pattern and is not subject to modulation by the gate potential, so the drive current is reduced accordingly. In particular, if this LDD region is present on the source region side, it will greatly decrease. Therefore, in the present invention, this LDD region is arranged inside the gate pattern so that it is modulated by the gate potential so as not to reduce the ON current.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION The best mode for carrying out the invention will be described below with reference to FIG. (A) shows a basic cross-sectional structure of a thin film transistor according to the present invention, which is a bottom gate type. As shown in the figure, the thin film transistor has a laminated structure in which a semiconductor thin film 1 made of polycrystalline silicon or the like, a gate electrode 2 having a predetermined pattern, and a gate insulating film 3 interposed therebetween are stacked. In this example, the gate electrode 2 is arranged below the semiconductor thin film 1 to form a bottom gate type. The semiconductor thin film 1 has a channel region (i
An (intrinsic) region 4, a high-concentration impurity region (N ++ region) 5, and a low-concentration impurity region (N region) 6 are provided. The high-concentration impurity regions 5 are located on both sides of the channel region 4 and function as the source region S and the drain region D, respectively. On the other hand, the low concentration impurity region 6 is LDD
It becomes a region and is interposed between at least one of the high-concentration impurity regions 5 and the channel region 4. In this example, the LDD region 6 is provided between the channel region 4 and the drain region D and between the channel region 4 and the source region S.

The semiconductor thin film 1 is patterned in an island shape, and is divided into an inner portion IN included in the pattern of the gate electrode 2 and an outer portion OUT located outside the pattern. While the channel region 4 is formed in the inner part IN,
The high concentration impurity region 5 is formed in the outer portion OUT.
Characteristically, the low-concentration impurity region 6 is the channel region 4
And the high-concentration impurity region 5 and at least a part thereof is included in the inner portion IN. In the illustrated example, the low-concentration impurity regions 6 are all included in the inner portion IN.
Preferably, the low concentration impurity region 6 has an impurity concentration of 1
It is set to 0 ¹⁶ to 10 ¹⁸ pieces / cm ³ . Further, the low-concentration impurity region 6 may have an impurity concentration having a gradient along the horizontal direction from the channel region 4 to the high-concentration impurity region 5. By providing the LDD region with a concentration distribution in the drain direction or the source direction, the width of the LDD region can be effectively narrowed and more ON current can be secured.
Alternatively, the same effect can be obtained even if the impurity concentration of the LDD region has a gradient along the depth direction of the semiconductor thin film 1. The thin film transistor having the above-described structure is formed on the insulating substrate 7 and covered with the passivation film 8. Contact holes communicating with the source region S and the drain region D are opened in the passivation film 8. A wiring 9 is patterned on the passivation film 8 and is electrically connected to the source region S and the drain region D via contact holes.

When measuring the drain breakdown voltage,
The source region S and the gate electrode 2 are held in a state close to the ground potential, and a positive potential (in the case of an N-channel transistor) is applied to the drain region D. At this time, a strong accumulation layer (accumulation layer) is formed at the junction between the channel region 4 and the drain region D. Therefore, a strong lateral electric field is generated at the junction, which causes breakdown.
The LDD region 6 is interposed to weaken the lateral electric field. Conventionally, it has been considered that even if the LDD region 6 is provided in the inner portion IN of the pattern of the gate electrode 2, it is meaningless because it is modulated by the gate potential. However,
A detailed calculation revealed that when the impurity concentration of the LDD region 6 is set in an appropriate range, it has an LDD function even if it is modulated by the gate potential. By positively utilizing this phenomenon, the on-current is not lowered by modulating the gate potential, and the off-current is suppressed.

(B) represents a top gate type thin film transistor, and the present invention can be applied to both the bottom gate type and the top gate type. Note that the portions corresponding to the bottom-gate thin film transistor shown in (A) are given corresponding reference numerals to facilitate understanding. As shown in the figure, in the top gate type, a gate electrode 2 is patterned on a semiconductor thin film 1 via a gate insulating film 3. The channel region 4 is formed in the inner portion IN of the pattern of the gate electrode 2, and the high concentration impurity region 5 is formed in the outer portion OU.
It is formed in T. The low-concentration impurity region 6 is at least partially included in the inner portion IN of the pattern of the gate electrode 2.

FIG. 2 is a graph showing the relationship between the on-current and off-current of the thin film transistor and the impurity concentration in the LDD region. The vertical axis represents the on-current and the off-current, and the horizontal axis represents the impurity concentration. The curve AON represents the on-current of the thin film transistor shown in FIG.
The curve ZON represents the ON current of the conventional thin film transistor. Further, the curve AOFF represents the off current of the thin film transistor according to the present invention, and the curve ZOFF represents the off current of the conventional thin film transistor. As is clear from the graph, by setting the impurity concentration of the LDD region (N region) between 10 ¹⁶ / cm ^{3 and} 10 ¹⁸ / cm ³ , the thin film transistor according to the present invention has almost no change in on-current. The off current is reduced. On the other hand, in the conventional thin film transistor, the provision of the LDD region reduces the on-current. High-concentration impurity region (N ++ region)
The impurity concentration of is controlled to about 10 ²⁰ to 10 ²¹ / cm ³ .

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the method of manufacturing a thin film transistor according to the present invention will be described in detail with reference to FIG. First, in step (A), a gate electrode 52 having a predetermined pattern is formed on an insulating substrate 51 made of glass or the like. For example, after forming a metal film made of Ta / Mo or the like by sputtering, the metal film is patterned by photolithography and etching to form the gate electrode 52. At this stage, the first photomask is used.

In step (B), a gate insulating film 53 is formed on the gate electrode 52. For example, S by CVD
The gate insulating film 53 is formed by forming iO ₂ . Alternatively,
P-SiN may be used instead of SiO ₂ . Furthermore, a laminated film of P-SiN and SiO ₂ may be used as the gate insulating film. Then, a semiconductor thin film 54 made of amorphous silicon is formed by the CVD method. The semiconductor thin film 54 is irradiated with laser light to be once melted, and then amorphous silicon is converted into polycrystalline silicon in a cooling process. Further, the semiconductor thin film 54 is patterned into an island shape by photolithography and etching to form an element region (active layer) of the thin film transistor. At this stage, the second photomask is used.

Proceeding to step (C), SiO ₂ is deposited by CVD to a thickness of 50 nm to form a protective film 55. Then, the first impurity blocking film 56 is formed on the semiconductor thin film 54 with a pattern that is inside the pattern of the gate electrode 52.
Formed through. Specifically, over-exposure is performed from the back surface of the transparent insulating substrate 51 using the gate electrode 52 as a mask, and the pattern of the first impurity blocking film 56 is set on the surface of the insulating substrate 51. More specifically, the photoresist is processed into the first impurity blocking film 56 by self-alignment by performing overexposure from the back surface after applying the photoresist. As a result, not only can the first impurity blocking film 56 be patterned very accurately,
Since the self-alignment method uses the gate electrode 52 as a mask, no photomask is required. Gate electrode 5
The alignment accuracy of the first impurity blocking film 56 with respect to 2 is extremely high. Subsequently, using the first impurity blocking film 56 as a mask, the semiconductor thin film 54 is doped with impurities at a low concentration to form an N region. For example, ions of impurities such as phosphorus are accelerated in the electric field to dope the semiconductor thin film 54. After that, the used first impurity blocking film 56 is peeled off.

Proceeding to step (D), the first impurity blocking film 56.
Second pattern with a larger area than that of
The impurity blocking film 57 is formed. Specifically, exposure is performed from the back surface of the transparent insulating substrate 51 using the gate electrode 52 as a mask, and the second impurity blocking film 57 is formed on the front surface of the insulating substrate 51.
Then, the back side exposure process is performed to set the pattern. More specifically, a photoresist is applied to the surface of the protective film 55 and then backside exposure is performed to process the photoresist into the second impurity blocking film 57 by self-alignment. At this time, the second impurity blocking film 57 having a larger area than the first impurity blocking film 56 can be formed by adjusting the exposure amount. For example,
Just exposure may be performed instead of overexposure. Further, the semiconductor thin film 54 is doped with impurities at a high concentration by using the second impurity blocking film 57 as a mask to provide an N ++ region. Specifically, ions of an impurity such as phosphorus are accelerated in the electric field to dope the semiconductor thin film 54 through the protective film 55. Thereafter, the unnecessary second impurity blocking film 57 is removed. As described above, the source region S and the drain region D (N ++ region) and the LDD region (N region) of the bottom gate type thin film transistor are formed. As is clear from the figure, LDD
The region is provided between the channel region and the source region S and between the channel region and the drain region D, and is included inside the pattern of the gate electrode 52.

In step (E), the bottom gate type thin film transistor is covered with the interlayer insulating film 58. For example, S
The interlayer insulating film 58 is formed by depositing iO ₂ by CVD.
Then, a P-SiN film is formed by CVD to form a cap film 59.
And In this state, annealing is performed at, for example, about 350 ° C. to diffuse the hydrogen contained in the interlayer insulating film 58 into the semiconductor thin film 54. The characteristics of the thin film transistor can be improved by this hydrogenation treatment. The cap film 59 has a dense composition and suppresses outward diffusion of hydrogen. After that, a contact hole communicating with the source region S and the drain region D is opened by photolithography and etching. At this stage, the third photomask is used.

Thereafter, an electrode forming step and the like are performed to complete the thin film semiconductor device. The completed state is shown in FIG. After opening the contact holes in the previous step, a metal film is formed by sputtering. In this example, aluminum and molybdenum are stacked to form two layers. This metal film is patterned by photolithography and etching to form the wiring electrode 60. At this stage, the fourth photomask is used. Subsequently, a photosensitive acrylic resin or the like is applied to provide a flattening film 61, and the unevenness of the thin film transistor or the wiring electrode 60 is filled. Further, the flattening film 61 is selectively etched by photolithography to open a contact hole. At this stage, the fifth photomask is used. Finally, a transparent conductive film such as ITO is formed on the flattening film 61 by sputtering, and patterned into a predetermined shape by photolithography and etching to process the pixel electrode 62. At this stage, the sixth photomask is used. As described above, the pixel electrode 62 and the thin film transistor for driving the pixel electrode 62 are integrally formed in the display thin film semiconductor device. Further, although not shown, thin film transistors forming peripheral drive circuits are also integrally formed on the same insulating substrate 51. As described above, according to the manufacturing method of the present invention, the thin film display semiconductor device for display can be manufactured using only six photomasks. If the flattening film 61 is omitted, only five photomasks may be used.

FIG. 3 shows the relationship between the exposure amount and the offset width in the back surface exposure process shown in steps (C) and (D) of FIG. This offset width represents the width of the impurity blocking films 56 and 57 that enter the inside of the pattern of the gate electrode 52. This graph shows the case where the exposure energy was set to 15 mW / cm ² and the positive photoresist OFPR-800 was used as the material of the impurity blocking film. Glass (Corning 7059) is used as the insulating substrate. Further, the gate insulating film uses a laminated structure of SiN _x (50 nm) and SiO ₂ (200 nm), and the semiconductor thin film uses 30 nm polycrystalline silicon. As is clear from the graph, when the exposure time is set to 20s, the exposure amount is 3
The value is 00 mJ / cm ² , the just exposure condition is obtained, and the offset width is zero. On the other hand, for example, the exposure time is 5
When it is set to about 0 s, the exposure amount is about 800 mJ / cm ² , and the overexposure condition is obtained, and the offset width is about 1 μm. In this way, the offset width can be set accurately by controlling the exposure time, and the LDD region width with less variation can be realized. Note that the photoresist can be processed into the impurity blocking film by exposure from the front surface side using a photomask, without adopting backside exposure by self-alignment using the gate electrode as a mask. However, in this case, an alignment error always occurs, so that the widths of the LDD regions differ between the source region side and the drain region side. Alternatively, the width of the LDD region varies among individual thin film transistors.

FIG. 6 is a schematic perspective view showing an example of an active matrix type display panel using the display thin film semiconductor device shown in FIG. 5 as a drive substrate. As shown in the figure, the present display panel has a flat structure including a driving substrate 101, a counter substrate 102, and a liquid crystal 103 held between them. A screen portion 104 and a peripheral portion are integrally formed on the drive substrate 101. Peripheral part is vertical drive circuit 105
And a horizontal drive circuit 106. These driving circuits are composed of thin film transistors having an LDD structure according to the present invention. A terminal portion 107 for external connection is formed on the upper end of the peripheral portion of the drive substrate 101. The terminal portion 107 is connected to a vertical drive circuit 105 and a horizontal drive circuit 106 via a wiring 108. The screen portion 104 includes gate wirings 109 and signal wirings 110 that intersect in a matrix. A pixel electrode 111 and a thin film transistor 112 for switching and driving the pixel electrode 111 are formed at each intersection. The gate wiring 109 is connected to the vertical driving circuit 105, and the signal wiring 110 is connected to the horizontal driving circuit 106. The drain region of the thin film transistor 112 is connected to the corresponding pixel electrode 111, the source region is connected to the corresponding signal line 110, and the gate electrode is connected to the corresponding gate line 1.
It continues to 09. In such a configuration, at least the thin film transistor included in the driving circuits 105 and 106 has the LDD region included inside the gate electrode pattern. In general, a switching thin film transistor for driving a pixel electrode holds signal charges written in the pixel electrode for one field period, so it is important to severely suppress off current (leakage current). In contrast,
It is important that the thin film transistor forming the drive circuit suppresses the off-current and secures a large on-current to improve the driving ability. In particular, in a high-speed drive circuit, it is essential not only to increase the absolute value of the on-current but also to control the variation of the on-current between individual thin film transistors to within ± 20%. In this respect, according to the present invention, the LDD region is included inside the gate electrode pattern to secure a sufficient on-current. Further, the LDD region width of each thin film transistor is accurately controlled by performing the above-described over-exposure process from the back surface, so that there is little variation in the on-current.

FIG. 7 is a schematic sectional view showing another embodiment of the method for forming the first impurity blocking film and the second impurity blocking film. The parts corresponding to those in FIG. 4 are designated by the corresponding reference numerals to facilitate understanding. The step (A) is the same as the step (C) in FIG. 4, and the first impurity blocking film 56 is formed by overexposure from the back surface using the gate electrode 52 as a mask. However, the difference is that a thermally deformable photoresist is used as the material of the impurity blocking film 56. After that, in step (B), the thermally deformable photoresist is reflow-heated to expand the pattern of the first impurity blocking film 56 and convert it into the second impurity blocking film 57. The reflow heating is performed at a temperature of 140 ° C. to 180 ° C., for example. As described above, in this embodiment, the first impurity blocking film 56 is converted into the second impurity blocking film 57 by reflow heating instead of forming the second impurity blocking film by the exposure process from the back surface, and the manufacturing process is simplified. Can be converted. Further, in this reflow heating, the expansion width can be precisely controlled by controlling the heating temperature and the heating time, and therefore the LDD region width can be formed without variation.

FIG. 8 is a schematic sectional view showing another example of the method of forming the source region S and the drain region D. In this example, instead of the ion doping shown in the step (D) of FIG. 4, impurities are introduced into the semiconductor thin film at a high concentration by a thermal diffusion method. The parts corresponding to those in the step (D) of FIG. 4 are designated by the corresponding reference numerals to facilitate understanding. In this example, doped silicon 70 containing a high concentration of impurities is overlaid on the semiconductor thin film 54, and is irradiated with laser light to dope the impurities. In this regard, the second impurity blocking film 57 uses heat resistant SiO ₂ instead of the photoresist. The second impurity blocking film 57 is
It also functions as an etching stopper when the doped silicon 70 is etched into a wiring electrode. In this example, laser doping is used to diffuse impurities into the semiconductor thin film 54 and simultaneously activate them.

[0023]

As described above, according to the present invention, the LDD region of the thin film transistor is at least partially included in the inner portion of the gate electrode pattern, so that the off current can be suppressed and a sufficient on current can be secured. It is possible. or,
Since the width of the LDD region is precisely controlled by adopting the backside exposure technique by self-alignment using the gate electrode as a mask, the variation in the on-current can be significantly suppressed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a best mode for carrying out a thin film transistor according to the present invention.

FIG. 2 is a graph showing a relationship between an impurity concentration in an LDD region of a thin film transistor and an on-current and an off-current.

FIG. 3 is a graph showing a relationship between an exposure amount and an offset width in backside exposure using a gate electrode as a mask.

FIG. 4 is a process drawing showing an example of a method of manufacturing a thin film transistor according to the present invention.

5 is a cross-sectional view showing a completed state of a display thin film semiconductor device manufactured according to the process shown in FIG.

6 is a perspective view showing an example of an active matrix type display panel in which the display thin film semiconductor device shown in FIG. 5 is assembled as a drive substrate.

FIG. 7 is a process drawing showing another embodiment of the method of manufacturing a thin film transistor according to the present invention.

FIG. 8 is a cross-sectional view showing another embodiment of the method of manufacturing a thin film transistor according to the present invention.

[Explanation of symbols]

 1 semiconductor thin film 2 gate electrode 3 gate insulating film 4 channel region 5 high concentration impurity region 6 low concentration impurity region 7 insulating substrate

Claims (13)

[Claims] 1. A laminated structure having a semiconductor thin film, a gate electrode having a predetermined pattern, and a gate insulating film interposed therebetween is stacked, and the semiconductor thin film has a channel region, a high-concentration impurity region, and a low concentration impurity region. A thin film transistor having a concentration impurity region, wherein the semiconductor thin film has an inner part included in a pattern of the gate electrode and an outer part located outside the pattern, and the channel region is formed in the inner part. The high-concentration impurity region is formed in the outer portion, the low-concentration impurity region is located between the channel region and the high-concentration impurity region, and at least a part is included in the inner portion. Thin film transistor. 2. The low-concentration impurity region has an impurity concentration of 10 ¹⁶ to 10 ¹⁸ pieces / cm ^3.
The thin film transistor as described in the above. 3. The thin film transistor according to claim 1, wherein the low-concentration impurity region has a gradient in impurity concentration along a horizontal direction from the channel region to the high-concentration impurity region. 4. The thin film transistor according to claim 1, wherein the low-concentration impurity region has an impurity concentration having a gradient along a depth direction of the semiconductor thin film. 5. The high concentration impurity region is located on both sides of a channel region, and the low concentration impurity region is provided between at least one high concentration impurity region and the channel region. Thin film transistor. 6. A first step of forming a gate electrode having a predetermined pattern on an insulating substrate, a second step of forming a gate insulating film on the gate electrode, and a semiconductor thin film on the gate insulating film. A third step of forming, a fourth step of forming a first impurity blocking film on the semiconductor thin film with a pattern that is inside the pattern of the gate electrode, and a low impurity concentration using the first impurity blocking film as a mask. And a sixth step of forming a second impurity blocking film with a pattern including the pattern of the first impurity blocking film and having a larger area than that of the first impurity blocking film, and the second impurity blocking 7. A method for manufacturing a thin film transistor, which comprises performing a seventh step of doping the semiconductor thin film with a high concentration of impurities using the film as a mask. 7. In the fourth step, overexposure is performed from the back surface of a transparent insulating substrate using the gate electrode as a mask,
7. The method of manufacturing a thin film transistor according to claim 6, further comprising a backside exposure process of setting a pattern of the first impurity blocking film on the surface of the insulating substrate. 8. The sixth step includes a back surface exposure process of performing exposure from the back surface of a transparent insulating substrate using the gate electrode as a mask and setting a pattern of a second impurity blocking film on the surface of the insulating substrate. Item 7. A method of manufacturing a thin film transistor according to Item 7. 9. The method of manufacturing a thin film transistor according to claim 6, wherein in the fifth step, impurity ions are subjected to electric field acceleration to dope the semiconductor thin film. 10. The method of manufacturing a thin film transistor according to claim 6, wherein in the seventh step, impurity ions are subjected to electric field acceleration to dope the semiconductor thin film. 11. The thin film transistor according to claim 6, wherein in the seventh step, doped silicon containing impurities at a high concentration is formed on the semiconductor thin film and irradiated with laser light to dope the impurity. Production method. 12. In the fourth step, a first impurity blocking film is formed using a thermally deformable photoresist, and the sixth impurity blocking film is formed.
7. The method of manufacturing a thin film transistor according to claim 6, wherein in the step, the pattern of the first impurity blocking film is enlarged by converting the photoresist into a second impurity blocking film by reflow heating the photoresist. 13. A display thin film semiconductor device in which a pixel electrode, a thin film transistor for switching and driving the pixel electrode, and a thin film transistor included in a driving circuit for driving the thin film transistor are integrated and formed on the same substrate, and at least the driving circuit. The thin film transistor included has a laminated structure in which a semiconductor thin film, a gate electrode having a predetermined pattern, and a gate insulating film interposed therebetween are stacked, and the semiconductor thin film has a channel region, a high-concentration impurity region, and a low concentration impurity region. A concentration impurity region is provided, the semiconductor thin film has an inner part included in the pattern of the gate electrode and an outer part located outside the pattern, the channel region is formed in the inner part, and A high concentration impurity region is formed on the outer side, and the low concentration impurity region is located between the channel region and the high concentration impurity region. One at least a portion indicating thin film semiconductor device, characterized in that encompassed inner side.