JP3328207B2 - Preamplifier and gain control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a preamplifier and a gain control method, and more particularly, to a transimpedance preamplifier for amplifying while converting an input current into a voltage, and a gain control method used therein.

[0002]

2. Description of the Related Art In general, as a preamplifier for converting a received optical signal into an electric signal and amplifying it, a transimpedance amplifier for amplifying and converting a weak current into a voltage is used.

[0003] Such an amplifier is described, for example, in Japanese Patent Application Laid-Open No. 9-8563. That is,
A conventional optical receiving preamplifier is an optical receiving preamplifier that amplifies a current signal from a light receiving element, a feedback amplifier circuit that varies a gain phase characteristic by a first control signal in accordance with the magnitude of the current signal, A large input control circuit for comparing an output of the feedback amplifier circuit with a reference voltage and outputting a first control signal to the feedback amplifier circuit. The feedback amplification circuit includes an amplifier for amplifying the current signal, a buffer circuit for buffering the output of the amplifier, a first resistor and a second resistor for switching the gain of the amplifier, and a phase for performing phase compensation of the amplifier. It is composed of a compensation capacitor, and a first switch element and a second switch element that perform a switching operation of gain and phase compensation. The large input control circuit compares the reference voltage with the output of the feedback amplifier circuit and outputs a second control signal, and outputs a first control signal that is set and reset by the second control signal and the reset signal. And a flip-flop. The control circuit includes: a reference voltage generating circuit that outputs a second reference voltage having a voltage value lower than the reference voltage; an output of the feedback amplifier circuit;
, A first comparator and a second comparator respectively comparing the reference voltage with the reference voltage, a flip-flop that is set and reset by a comparison output signal and a reset signal that are outputs of the second comparator, and an output of the flip-flop. , An inverter for inverting the output of the second comparator, an exclusive-OR circuit for performing an exclusive-OR operation on the output signal of the flip-flop and the output signal of the D flip-flop, And a logical product circuit for calculating the logical product of the output signal of the logical logic circuit and the comparison output signal output from the first comparator. The control circuit includes a peak hold circuit that holds the peak voltage of the output of the feedback amplifier circuit, a reference voltage generation circuit, a first comparator that compares the output of the peak hold circuit with the reference voltage, and an output of the feedback amplifier circuit. A second comparator for comparing the output of the second comparator with a second reference voltage, a flip-flop that is set and reset by a comparison output signal and a reset signal output from the second comparator, and a second flip-flop that holds the output of the flip-flop. 1 D flip-flop, an inverter for inverting the output of the second comparator, and a second input for receiving an output signal of the first D flip-flop and a comparison output signal which is an output of the first comparator. And a D flip-flop. Further, the control circuit includes a reference voltage generating circuit, a first comparator and a second comparator for comparing an output of the feedback amplifier circuit with the reference voltage and the second reference voltage, respectively, and an output of the second comparator. A flip-flop that is set and reset by the comparison output signal and the reset signal, a delay circuit that delays the output signal of the flip-flop, and an exclusive-OR that performs an exclusive OR operation on the output of the delay circuit and the output signal of the flip-flop. The circuit comprises an OR circuit and an AND circuit for performing an AND operation on the output signal of the exclusive logic circuit and the comparison output signal output from the first comparator. In such a conventional technology, since a control circuit for switching a feedback resistance between an amplifier and a buffer circuit with an FET switch and for switching a phase compensation capacitor is provided, it is possible to minimize a change in the offset of the amplifier when a large signal is input. It describes that stable operation can be expected without fluctuation of transimpedance gain, and the difference in data amplitude can be suppressed when burst-like data is input.

FIG. 6 is a circuit diagram for explaining a conventional transimpedance type preamplifier. FIG.
In the transimpedance type preamplifier shown in (1), when a reset signal is input, the MOS transistor is controlled by a peak hold circuit (PD), a threshold generation circuit, and a large input protection circuit, and the gain of the current-voltage conversion amplifier (PRE) is maximized The specified feedback resistor 2 or 3 is selected so that

[0005]

However, in the prior art, a large signal input and a reset signal which saturate the output of the transimpedance type preamplifier are simultaneously inputted at the time of system startup or the like. Since the transimpedance type preamplifier is fixed at the maximum gain, the output is saturated, the linearity cannot be maintained, and the signal cannot be received, or the dynamic range becomes narrow and the maximum input level becomes 15 dBm. There was a problem that it was limited to the extent.

[0006] The present invention has been made in view of such a problem, and an object thereof is to provide a preamplifier with:
By adding a comparator that operates only when a reset signal is input to return the feedback resistor to the initial state, even if the reset signal and the input signal overlap, the output does not saturate and the linearity can be maintained, and the dynamic range can be maintained. It is to provide a preamplifier and a gain control method that can be expanded.

[0007]

Means for Solving the Problems The gist of the invention described in claim 1 of the present invention, the current-voltage conversion connected to the input terminal
Amplifying circuit, MOS transistor, peak hold circuit,
A threshold generation circuit, a large input protection circuit, and a control circuit,
The control circuit consists of a reference voltage generation circuit that creates the reference voltage,
, First flip-flop circuit, NOT logic operation circuit
Path, OR circuit, second flip-flop circuit, exclusive
An OR circuit, and an input / output of the current / voltage conversion amplifier
A specified feedback resistor is connected between the
Before operating as a switch between the input and output of the
The MOS transistor is connected to the gain limiting feedback resistor.
And the threshold generation circuit performs the peak hold operation.
Using the output of the road as the reference voltage, create a judgment threshold for large signal input,
The large input protection circuit is an output of the current-voltage conversion amplifier circuit.
Force and the output of the threshold generation circuit are input,
When it is detected, the fact is output to the OR circuit,
The comparator outputs the output of the reference voltage generation circuit and the voltage.
Compare the output of the current-voltage conversion amplifier circuit and the result of the comparison.
To the clock terminal of the first flip-flop circuit.
And the first flip-flop circuit has a data terminal
Is pulled up to the power supply potential, and the clock terminal is
The output of the comparator is connected and the reset terminal
The counter of the externally supplied reset signal which is the output of the constant logic operation circuit
Output signal is connected to the input terminal of the OR circuit.
And the OR circuit is connected to one of the
Output of input protection circuit and first flip-flop circuit
And outputs the signal of the result of the comparison to the second
Output to the clock terminal of the flip-flop circuit,
In the second flip-flop circuit, the data terminal is connected to the front.
It is pulled up to the power supply potential and the clock terminal
The output of the OR circuit is connected, and the reset terminal
The output of the exclusive OR circuit is connected and the output from the output terminal is
Force is connected to the gate terminal of the MOS transistor
And the exclusive OR circuit is configured to reset the externally supplied signal.
From the signal and the output terminal of the first flip-flop circuit
Performs an exclusive OR operation with the output of
The reset terminal of the second flip-flop circuit
When the external supply reset signal is output.
The peak hold circuit is a voltage follower circuit.
To become the second flip-flop circuit is the logical value "
0 "as an output signal of the output terminal,
The reset terminal of the flip-flop circuit is connected to the external
A signal obtained by inverting the supply reset signal by the NOT logic operation circuit.
Signal is input, and the second flip-flop circuit
Between the output of the comparator and the externally supplied reset signal.
Normal operation state when exclusive OR operation result is logical value H
When the logical value is L, the logical value “0” is output from the output terminal.
Output as a force signal . The gist of the invention described in claim 2 of the present invention resides in that a current-voltage conversion amplifier circuit connected to an input terminal,
S transistor, peak hold circuit, threshold generation circuit,
It has a large input protection circuit and a control circuit.
A reference voltage generation circuit to generate a reference voltage, a comparator
Data, a first flip-flop circuit, a NOT logic operation circuit,
OR circuit, second flip-flop circuit, exclusive logic
A sum circuit between the input and output of the current-voltage conversion amplifier circuit
Is connected to a specified feedback resistor,
Between the input and output of the width circuit, the M
The OS transistor and the gain limiting feedback resistor are connected,
In the first flip-flop circuit, a data terminal
Is pulled up to the power supply potential, and
The output of the comparator is connected to the reset terminal.
The externally supplied reset signal, which is the output of the NOT logic operation circuit,
The inverted signal is connected, and the output terminal is the input of the OR circuit.
The second flip-flop connected to one of the terminals.
In a flip-flop circuit, the data terminal is connected to the power supply potential.
Pulled up, the clock terminal is connected to the OR circuit.
An output is connected and the exclusive OR is connected to the reset terminal.
The output of the circuit is connected, and the output from the output terminal is
Preamplifier connected to the gate terminal of the S transistor
The output of the peak hold circuit
Pressure and a large signal input determination threshold using the threshold generation circuit
Generating an output, and an output of the current-voltage conversion amplifier circuit.
The large input protection to which the output of the threshold generation circuit is input
When the circuit detects an excessive input, the fact
Outputting to the OR circuit using a protection circuit;
Using a comparator, the output of the reference voltage generation circuit and
Compare the output of the current-voltage conversion amplifier circuit,
To the clock terminal of the first flip-flop circuit.
And outputting to the child, using the OR circuit, the large
Output of input protection circuit and first flip-flop circuit
And outputs the signal of the result of the comparison to the second
Output to the clock terminal of the flip-flop circuit
And the externally supplied resource using the exclusive OR circuit.
Set signal and output terminal of the first flip-flop circuit
Performs an exclusive OR operation with the output from the child and performs the operation.
Of the reset of the second flip-flop circuit
And outputting the externally supplied reset signal to the
When output, the peak hold circuit
Operate as a follower circuit, and
The logical value “0” is output from the output terminal of the
And outputs the externally supplied reset signal to the NOT logic.
The signal inverted by using the arithmetic circuit is converted to the first flip-flop.
Inputting to the reset terminal of the flop circuit;
Between the output of the comparator and the externally supplied reset signal.
When the exclusive OR operation result is a logical value H, the second
The flip-flop circuit is brought into a normal operation state, and the second
Using a flip-flop circuit, when the logic value is L,
A value "0" is output from the output terminal of the second flip-flop circuit.
And a step of outputting as an output signal .

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. The description will proceed with the transimpedance preamplifier 100 as an example of the preamplifier 100.

(First Embodiment) FIG. 1 is a circuit diagram for explaining a first embodiment of a transimpedance preamplifier 100 according to the present invention. The transimpedance preamplifier 100 according to the first embodiment includes an input terminal I
N is connected to the current-voltage conversion amplifier circuit 1 (PRE in the figure).
), A MOS transistor 4, a peak hold circuit 5 (denoted by PD in the figure), a threshold generation circuit 6, a large input protection circuit 7, and a control circuit 50.

The control circuit 50 includes a reference voltage generating circuit (referred to as REF voltage in the figure) 8 for generating a reference voltage, a comparator (referred to as COMP in the figure) 9, and a flip-flop circuit (referred to as F / F in the figure). ) 10, NOT logical operation circuit 11,
It has an OR circuit (denoted by OR in the drawing) 12, a flip-flop circuit (denoted by F / F in the drawing) 13, and an exclusive OR circuit (denoted by EXOR in the drawing).

Next, the control circuit 50 will be described with reference to FIG.

A specified feedback resistor 2 is connected between the input and output of the current-voltage conversion amplifier circuit 1. A MOS transistor 4 operating as a switch and a gain limiting feedback resistor 3 are connected between the input and output of the current-voltage conversion amplifier circuit 1.

The threshold generation circuit 6 includes a peak hold circuit 5
(Referred to as B in the figure) is used as a reference voltage to create a large signal input determination threshold.

The large input protection circuit 7 receives the output of the current / voltage conversion amplifier circuit 1 (denoted by A in the drawing) and the output of the threshold generation circuit 6 (denoted by C in the drawing), and detects an excessive input. When this is done, the fact (denoted by D in the figure) is output to the OR circuit 12.

The comparator 9 compares the output of the reference voltage generation circuit 8 (denoted by E in the figure) with the output of the current-voltage conversion amplifier circuit 1, and compares the comparison result (denoted by F in the figure) with a flip-flop. Output to the clock terminal C of the circuit 10.

In the flip-flop circuit 10, the data terminal D is pulled up to the power supply potential VDD, the output of the comparator 9 is connected to the clock terminal C (denoted by F in the figure),
The output of the NOT logic operation circuit 11 (that is, an inverted signal of the externally supplied reset signal) is connected to the reset terminal R, and the output terminal Q is connected to one of the input terminals of the OR circuit 12.

The OR circuit 12 compares the output of the large input protection circuit 7 (denoted by D in the figure) with the output of the flip-flop circuit 10 and outputs the comparison result signal (denoted by H in the figure) to the flip-flop. Output to the clock terminal C of the loop circuit 13.

In the flip-flop circuit 13, the data terminal D is pulled up to the power supply potential VDD, the output of the OR circuit 12 (denoted as H in the drawing) is connected to the clock terminal C,
The output of the exclusive OR circuit 14 (denoted by I in the drawing) is connected to the reset terminal R, and the output from the output terminal Q (denoted by J in the drawing) is connected to the gate terminal of the MOS transistor 4. .

The exclusive-OR circuit 14 performs an exclusive-OR operation on the externally supplied reset signal and the output from the output terminal Q of the flip-flop circuit 10 (denoted by G in the figure), and executes the operation result ( (Denoted by I in the figure) is output to the reset terminal R of the flip-flop circuit 13.

When the externally supplied reset signal is output, the peak hold circuit 5 becomes a voltage follower circuit,
The flip-flop circuit 13 outputs the logical value “0” to the output terminal Q.
(Indicated by J in the figure). A signal obtained by inverting the externally supplied reset signal by the NOT logic operation circuit 11 is input to the reset terminal R of the flip-flop circuit 10.

The flip-flop circuit 13 is exclusive of the output of the comparator 9 (denoted by F in the drawing) (that is, the output of the terminal Q of the flip-flop circuit 10 (denoted by G in the drawing)) and the externally supplied reset signal. When the result of the logical sum operation is a logical value H, the normal operation state is set.

Next, an embodiment of the gain control method of the present invention executed by the transimpedance type preamplifier 100 of the first embodiment will be described.

The gain control method according to the present embodiment is a step executed by the control circuit 50, which controls an amplification factor when amplifying while converting an input signal input to the input terminal IN in the form of current into a voltage. A gain control method, comprising a prescribed feedback resistor 2 and a gain limiting feedback resistor 3 for feeding an output signal back to an input terminal IN by a predetermined feedback amount, and converting the input signal into a voltage via the feedback resistors 2 and 3. When an input signal whose input level is equal to or lower than an output amplitude level at which the current-voltage conversion amplifier circuit 1 is saturated is input to the current-voltage conversion amplifier circuit 1 that amplifies while converting, or an externally supplied reset signal is input. Sometimes select the specified feedback resistor 2,
When an input signal whose input level is larger than the output amplitude level at which the current-voltage conversion amplifier circuit 1 is saturated is input, the specified feedback resistor 2 and the gain limiting feedback resistor 3 are selected, and the specified feedback resistor 2 is used for gain limiting. There is a control step of reducing the gain of the current-voltage conversion amplifier circuit 1 by connecting the feedback resistors 3 in parallel.

This control step is performed when an input signal whose input level is higher than the output amplitude level at which the current-voltage conversion amplifier circuit 1 is saturated is input, and when the externally supplied reset signal is input, the specified feedback resistance 2 and a step of selecting the gain limiting feedback resistor 3 and connecting the gain limiting feedback resistor 3 in parallel with the specified feedback resistor 2 to reduce the gain of the current-voltage conversion amplifier circuit 1.

The control step includes a feedback resistor 3 for gain limitation.
Switch means connected between the input and output of the current-to-voltage conversion amplification circuit 1 in series with a threshold value generation circuit 6 for determining whether the input level is greater than the gain switching level of the current-to-voltage conversion amplification circuit 1 and a large input protection When the input signal whose input level is equal to or lower than the output amplitude level at which the current-voltage conversion amplifier circuit 1 is saturated is input to the transimpedance preamplifier 100 having the circuit 7 or the externally supplied reset signal is input. When the switch means is turned off, the gain limiting feedback resistor 3 is removed from the feedback loop and the specified feedback resistor 2 is selected, and the input level is changed from the output amplitude level at which the current-voltage conversion amplifier circuit 1 is saturated. When a large input signal is input, or when the input level is larger than the output amplitude level at which the current-voltage conversion amplifier circuit 1 is saturated. Even when the signal is inputted externally supplied reset signal defining feedback resistor gain limiting feedback resistor 3 is made conductive the switch means when the inputted 2
To reduce the gain of the current-voltage conversion amplifier circuit 1 in parallel.

The control step is a step executed by the comparator 9 to determine whether or not an input signal having an output amplitude such that the current-voltage conversion amplifier circuit 1 is saturated is input independently of the externally supplied reset signal. A comparison step.

The control step is a flip-flop circuit 1
0 is a step to be executed, when an input signal whose input level is larger than the output amplitude level at which the current-voltage conversion amplifier circuit 1 is saturated is input, and the input level is the gain switching of the current-voltage conversion amplifier circuit 1. A step of detecting that an input signal higher than the level or an externally supplied reset signal is input.

The control step is a step executed by the exclusive OR circuit 14, and is performed when an input signal whose input level is larger than the output amplitude level at which the current-voltage conversion amplifier circuit 1 is saturated is input. Exclusive OR process for detecting that an externally supplied reset signal has been input.

The control step is a flip-flop circuit 1
3 is a step to be executed, wherein an input signal whose input level is higher than the output amplitude level at which the current-voltage conversion amplifier circuit 1 is saturated and whose input level is higher than the gain switching level of the current-voltage conversion amplifier circuit 1 is input. In some cases, the method includes a step of detecting that an externally supplied reset signal has been input.

Next, the basic operation of the transimpedance preamplifier 100 according to the first embodiment will be described with reference to the drawings. In the circuit diagram of FIG. 1, it is now assumed that the resistance value of the prescribed feedback resistor 2 is 40 KΩ and the resistance value of the gain limiting feedback resistor 3 is 3 KΩ. The output C voltage of the threshold generation circuit 6 is 500 mV, the output E voltage of the reference voltage generation circuit 8 is 400 mV, and the transimpedance preamplifier 1
It is assumed that the DC voltage of the output of 00 when there is no signal is a general 1V.

Here, the reason why the voltage of the output E of the reference voltage generation circuit 8 in the control circuit 50 is set lower than the voltage of the output C of the threshold value generation circuit 6 will be described. The gain switching of the transimpedance preamplifier 100 is performed by the large input protection circuit 7, and the comparator 9 of the control circuit 50 detects the saturation of the transimpedance preamplifier 100. In this embodiment, since only the saturation of the transimpedance preamplifier 100 needs to be detected, the accuracy of the output E of the reference voltage generation circuit 8 of the control circuit 50 may be low. However, since it must not operate at an input level at which the large input protection circuit 7 does not operate, the production conditions and environmental conditions of the DC voltage of the transimpedance preamplifier 100 when there is no signal are taken into consideration, Control circuit 50
Must be set so that the output E of the reference voltage generation circuit 8 does not exceed the voltage of the output C of the threshold generation circuit 6.

The static operation of the transimpedance preamplifier 100 according to the first embodiment will be described. FIG. 2 is a diagram illustrating DC characteristics (DC characteristics) of the transimpedance preamplifier 100 according to the first embodiment.
The horizontal axis is the input level (unit: [mAp-p]) of the transimpedance preamplifier 100, and the vertical axis is the output amplitude voltage (shown as preamplifier exit amplitude (node A) in the figure).
(The unit is [mVp-p]). When the input level is about 12.5 μAp-p or less, which is the gain switching level of the transimpedance preamplifier 100, only the specified feedback resistor 2 is selected by the control circuit 50. on the other hand,
When the input level becomes larger than about 12.5 μAp-p, the gain limiting feedback resistor 3 is selected by the control circuit 50 and connected in parallel with the specified feedback resistor 2 to reduce the gain. The saturation of the preamplifier 100 can be prevented.

Next, the transient operation of the transimpedance type preamplifier 100 of the first embodiment will be described. FIG. 3 is a waveform operation diagram of the transimpedance preamplifier 100 of the first embodiment when a reset signal and an input signal are not input simultaneously. The input level here is determined by the transimpedance preamplifier 10
This is a level of about 12.5 μAp-p or more at which the gain of 0 is switched by the control circuit 50 (see FIG. 2).

When the input signal is input from the input terminal IN after the input of the reset signal, the input signal is approximately 1
When the output signal amplitude exceeds 2.5 μAp-p, the output signal amplitude of the transimpedance preamplifier 100 becomes 500 mVp-p.
As described above (see FIG. 2), the control circuit 50 operates to perform gain switching.

More specifically, first, when the logical value "1" is once input to the reset signal and the logical value becomes "0", first, the peak hold circuit 5 of the control circuit 50 causes the current-voltage converting / amplifying circuit 1 Of the output ("0" level) (denoted as B in the figure). Subsequently, the threshold generation circuit 6 of the control circuit 50 which receives the output of the peak hold circuit 5 as an input
Is reduced by 500 mVp-p to the gain switching threshold of the transimpedance preamplifier 100 (C in the figure).
Notation). Thereafter, a signal is input, and the output signal of the transimpedance preamplifier 100 is set to a threshold (C in the figure) in the large input protection circuit 7 of the control circuit 50.
), A logical value “1” is output as a gain switching signal (denoted as D in the figure).

At this time, since the output of the flip-flop circuit 10 of the control circuit 50 (represented by G in the figure) has been reset, its output becomes "0" (= output at the time of reset). Then, the OR circuit 12 of the control circuit 50 outputs a logical value “1” (denoted as H in the figure).

Flip-flop circuit 13 of control circuit 50
Since the reset output (denoted by I in the figure) has a logical value "0", the normal operation state is maintained.

When the output of the OR circuit 12 of the control circuit 50 (denoted by H in the drawing) changes to a logical value "1", the output of the flip-flop circuit 13 of the control circuit 50 (denoted by J in the drawing) is changed. The logical value changes from “0” to “1”. As a result, the MOS transistor 4 is turned on (ON state = activated state), and the resistance value of the feedback resistor is changed to the control circuit 5.
As a result of switching from 40 KΩ to 3 KΩ by 0, the output of the transimpedance type preamplifier 100 is not saturated and the linearity is maintained.

Next, the operation of the transimpedance type preamplifier 100 of the first embodiment when the reset signal and the input signal overlap will be described. FIG. 4 is an operation waveform diagram of the transimpedance preamplifier 100 of the first embodiment when a reset signal and an input signal are input simultaneously. In the state where the reset signal is input, the peak hold circuit 5 of the control circuit 50 is a voltage follower circuit, so that the output of the peak hold circuit (denoted by B in the figure) is the output of the transimpedance type preamplifier 100. Follows the output signal. Since the gain switching threshold value (denoted by C in the drawing) is based on the peak hold circuit output (B), the control circuit 5
The 0 large input protection circuit 7 does not exceed the threshold value despite the large signal input. Therefore, the output of the large input protection circuit 7 (denoted by D in the figure) maintains the logical value “0”.

On the other hand, the reference voltage output circuit 8 of the control circuit 50
(Shown as E in the figure) is a DC fixed voltage,
When the transimpedance preamplifier 100 has an output amplitude that saturates independently of the reset signal, the output of the comparator 9 of the control circuit 50 (denoted by F in the figure) becomes a logical value “1”.

Flip-flop circuit 10 of control circuit 50
Has a data terminal D connected to the power supply potential VDD, and a clock terminal C connected to the output of the comparator 9 (denoted as F in the figure). The reset signal of the flip-flop circuit 10 is
The reset is released only during the input of the external reset signal. Further, as shown in FIG. 4, the reset signal is a logical value “1” and the output of the comparator 9 (denoted as F in the figure)
Changes from “0” to “1”, the output of the flip-flop circuit 10 (denoted by G in the figure) becomes a logical value “1”, and accordingly, the output of the OR circuit 12 of the control circuit 50 (Denoted by H in the drawing) also becomes “1”.

Flip-flop circuit 13 of control circuit 50
Has a data terminal D connected to the power supply potential VDD, a clock terminal C connected to the output of the OR circuit 12 (denoted as H in the figure), and a reset terminal R connected to the output of the exclusive OR circuit 14 (FIG. Is denoted by I).

The exclusive OR circuit 14 of the control circuit 50 receives the reset signal and the output of the flip-flop circuit 10 (denoted by G in the figure).

When a large input signal that saturates the transimpedance preamplifier 100 is input at the time of inputting the reset signal as currently considered, the reset signal is set to "1" as shown in FIG. During this period, the output (G) of the flip-flop circuit 10 becomes “1”, and the output (G) “1” of this flip-flop circuit 10 is input to the exclusive OR circuit 14. Exclusive OR circuit 14
Performs an exclusive OR operation on the logical value “1” of the reset signal and the logical value “1” of the output (G) of the flip-flop circuit 10, and as a result, resets the logical value “1” of the flip-flop circuit 13. As a result of outputting to the terminal R, the reset state of the flip-flop circuit 13 is released.

As a result, the flip-flop circuit 13 enters a normal operation state, and the output (H) of the OR circuit 12 of the control circuit 50 changes from a logical value “0” to “1”. Output (J) is logical value "1"
, The MOS transistor 4 becomes conductive, and the control circuit 50 sets the transimpedance type preamplifier 1
Switch gain of 00. As a result, the feedback resistance becomes 4
Switching from 0KΩ to 3KΩ.

Further, when the reset signal returns to the logical value "0", as shown in FIG. 4, the reset terminal R of the flip-flop circuit 10 becomes the logical value "1" and the flip-flop circuit 10 is reset. Although the flip-flop circuit 10 outputs a logical value "0", the exclusive OR circuit 14 of the control circuit 50 does not change its output with the logical value "0" because both inputs have the logical value "0". As a result, the output of the flip-flop circuit 13 maintains the logical value “1” and does not change. Thus, in the transimpedance preamplifier 100 of the present embodiment, even when the reset signal and the input signal overlap, the output of the transimpedance preamplifier 100 is not saturated and linearity is maintained.

(Second Embodiment) FIG. 5 is a circuit diagram for explaining a transimpedance preamplifier 100 according to a second embodiment of the present invention. The transimpedance preamplifier 100 of the second embodiment is different from the first embodiment in that the connection of the comparator 9 in the first embodiment is changed to the output (B) of the peak hold circuit 5 and the output (E) of the reference voltage generation circuit 8. Has features. As a result, although the reaction time is delayed by the bandwidth of the peak hold circuit 5,
Since the load on the transimpedance type preamplifier 100 is reduced, it is effective in securing the band of the main signal.

The operation waveform diagram of the transimpedance preamplifier 100 of the second embodiment is the same as that of FIG.
Although the input to the comparator 9 has been changed from the output (A) of the current-voltage conversion amplifier circuit 1 to the output (B) of the peak hold circuit 5, the main operation itself is the same as that of the first embodiment, and the description is omitted. I do.

In the present embodiment, the present invention is not limited to the transimpedance type preamplifier,
The present invention can be applied to a gain control technique of a signal amplifier suitable for applying the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, but can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0050]

As described above, according to the present invention, even when the reset signal and the input signal overlap, the output is not saturated and the linearity can be maintained. As a result, the dynamic range can be reduced. It has the effect of being able to expand.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a transimpedance preamplifier according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating DC characteristics (DC characteristics) of the transimpedance preamplifier of the first embodiment.

FIG. 3 is a waveform operation diagram of the transimpedance preamplifier of the first embodiment when a reset signal and an input signal are not input simultaneously.

FIG. 4 is an operation waveform diagram of the transimpedance preamplifier of the first embodiment when a reset signal and an input signal are input simultaneously.

FIG. 5 is a circuit diagram for explaining a transimpedance type preamplifier according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram for explaining a conventional transimpedance type preamplifier.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Current-voltage conversion amplifier circuit (PRE) 2 ... Prescribed feedback resistor 3 ... Gain limiting feedback resistor 4 ... MOS transistor (switch means) 5 ... Peak hold circuit (PD) 6 ... Threshold generation circuit 7 ... Large input protection circuit 8 ... Reference voltage generation circuit (REF voltage) 9 ... Comparator (COMP) 10 ... Flip-flop circuit (F / F) 11 ... Negative logical operation circuit 12 ... OR circuit (OR) 13 ... Flip-flop circuit (F / F) 14 ... Exclusive OR circuit (EXOR) 50 ... Control circuit 100 ... Preamplifier (transimpedance preamplifier) VDD ... Power supply potential

Continuation of front page (56) References JP-A-9-8563 (JP, A) JP-A-5-291838 (JP, A) JP-A-6-350352 (JP, A) JP-A-2-199934 (JP , A) JP-A-4-367108 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G03G 3/20-3/34 H03F 3/08

Claims (2)

(57) [Claims] 1. A current-voltage conversion amplifier connected to an input terminal.
Circuit, MOS transistor, peak hold circuit, threshold
A reference voltage generating circuit for generating a reference voltage , a control circuit, and a control circuit.
Comparator, first flip-flop circuit, NOT logic
Arithmetic circuit, OR circuit, second flip-flop circuit,
An additional OR circuit, and an input / output of the current / voltage conversion amplifier circuit
A specified feedback resistor is connected between the outputs,
A switch operates between the input and output of the voltage conversion amplifier circuit.
The MOS transistor and the gain limiting feedback resistor
The threshold generation circuit outputs the output of the peak hold circuit.
A large signal input determination threshold is made as a reference voltage, and the large input protection circuit outputs the output of the current-voltage conversion amplifier circuit.
Force and the output of the threshold generation circuit are input,
When the detection is detected, the fact is output to the OR circuit, and the comparator compares the output of the reference voltage generation circuit with the output of the reference voltage generation circuit.
The output of the current-voltage conversion amplifier circuit.
The result to the clock terminal of the first flip-flop circuit
And the first flip-flop circuit has a data terminal
Potential to the clock terminal
Is connected to the output of the
Inverted signal of the externally supplied reset signal that is the output of the arithmetic circuit
And the output terminal is one of the input terminals of the OR circuit.
The OR circuit is connected to the output of the large input protection circuit and the
1 and the output of the flip-flop circuit.
Of the result of the second flip-flop circuit
Clock terminal, and the second flip-flop circuit outputs the data terminal
Pulled up to the power supply potential and connected to the clock terminal
The output of the OR circuit is connected and the reset terminal is
The output of the exclusive OR circuit is connected, and the
An output is connected to the gate terminal of the MOS transistor.
The exclusive-OR circuit is configured to output the externally supplied reset signal
An output from an output terminal of the first flip-flop circuit
And perform an exclusive OR operation with
Output to the reset terminal of the second flip-flop circuit
And, when said external supply reset signal is output, the peak
The hold circuit becomes a voltage follower circuit,
The second flip-flop circuit outputs a logical value “0” as an output terminal
As the output signal of the first flip-flop.
The reset terminal of the circuit is connected to the externally supplied reset signal.
The second flip-flop circuit receives a signal obtained by inverting the signal by the NOT logic operation circuit,
Exclusive OR operation of the output of the above and the externally supplied reset signal
When the calculation result is the logical value H, the normal operation state is set, and the logical value
Outputs a logical value “0” as the output signal of the output terminal when L is low.
A preamplifier, characterized in that: 2. A current-to-voltage conversion amplifier connected to an input terminal.
Circuit, MOS transistor, peak hold circuit, threshold
Having a creation circuit, a large input protection circuit, and a control circuit;
In the circuit, a reference voltage generation circuit that creates a reference voltage,
Comparator, first flip-flop circuit, NOT logic
Arithmetic circuit, OR circuit, second flip-flop circuit,
An additional OR circuit, and an input / output of the current / voltage conversion amplifier circuit
A specified feedback resistor is connected between the outputs,
A switch operates between the input and output of the voltage conversion amplifier circuit.
The MOS transistor and the gain limiting feedback resistor
And in the first flip-flop circuit,
The data terminal is pulled up to the power supply potential and the clock
The output of the comparator is connected to the
The externally supplied reset which is the output of the NOT logic operation circuit
Connected to the inverted signal of the
Connected to one of the input terminals of the
In the flip-flop circuit, the data terminal is connected to the power supply.
Is pulled up to the source potential, and the logic terminal is connected to the clock terminal.
The output of the sum circuit is connected, and the exclusive terminal is connected to the reset terminal.
The output of the logical OR circuit is connected, and the output from the output terminal is
Connected to the gate terminal of the MOS transistor
A large signal is input to the preamplifier using the output of the peak hold circuit as a reference voltage.
Generating a force determination threshold using the threshold generation circuit
And the output of the current-voltage conversion amplifier circuit and the threshold value generation circuit.
The large input protection circuit to which the output and the
When it is known, the fact is described using the large input protection circuit.
Outputting to the OR circuit; and outputting the reference voltage generation circuit using the comparator.
Power and the output of the current-voltage conversion amplifier circuit,
The result of the comparison is applied to the clock of the first flip-flop circuit.
And outputting the output of the large input protection circuit using the OR circuit.
The output is compared with the output of the first flip-flop circuit.
The signal resulting from the comparison is supplied to the second flip-flop circuit.
Outputting to the clock terminal, and using the exclusive OR circuit to reset the externally supplied signal.
From the signal and the output terminal of the first flip-flop circuit
Performs an exclusive OR operation with the output of
The reset terminal of the second flip-flop circuit
And when the externally supplied reset signal is output,
The hold circuit operates as a voltage follower circuit.
Using the second flip-flop circuit to generate a logical value "
0 "as an output signal of the output terminal,
The reset signal is inverted using the NOT logic operation circuit
The reset signal of the first flip-flop circuit.
And inputting the signal to the external terminal, and outputting the comparator and the externally supplied reset signal.
When the result of the exclusive OR operation of the logical
The flip-flop circuit is set to a normal operation state, and the second
Using a flip-flop circuit, a logical value L
A value "0" is output from the output terminal of the second flip-flop circuit.
A gain control method, comprising the step of outputting as an output signal .