JP3191746B2 - Optical receiving circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical receiving and amplifying circuit, and more particularly to a circuit for amplifying an electric signal obtained by converting a burst optical signal. Examples of burst-like optical signal transmission include passive double star (PDS) and optical Ethernet communication.

[0002]

2. Description of the Related Art Generally, in a circuit for amplifying an electric signal obtained by converting an optical signal using a light receiving element such as a photodiode, a transimpedance type amplifying circuit is used to convert a weak converted current into a voltage. .

[0003] Before describing the related art, a brief description will be given of, for example, a passive double star (PDS) system to which the present invention is applied, in order to facilitate understanding of the present invention. In the PDS method, no active element is installed in the middle of a subscriber line, and conversion from an optical fiber to a copper line is not performed.
An optical fiber extends to the subscriber's home, and the device composed of the active elements is installed at the subscriber's home. An optical star coupler that branches one optical fiber into several tens of optical fibers is merely installed outdoors. Since the optical star coupler is a passive element, power for branching is unnecessary.

[0004] In the above-mentioned PDS system, transmission of upstream information (from a subscriber to a station side apparatus) is performed by a time division multiple access (TDMA) system so that information from each subscriber does not overlap. The optical line terminal needs a circuit for converting a TDMA burst optical signal transmitted from each subscriber into an electric signal and amplifying the converted electric signal.

The present invention relates to a circuit for amplifying a burst-like electric signal obtained by converting such a burst-like optical signal, and it is needless to say that the present invention is not limited to the above-mentioned PDS system.

As described above, in order to convert a weak current signal obtained by converting an optical signal into a voltage signal, a transimpedance type amplifier circuit is generally used. This type of amplifier circuit is disclosed, for example, in Japanese Patent Application No. 7-153.
No. 150 (hereinafter referred to as the prior art).

FIG. 12 is a block diagram showing an optical receiving amplifier disclosed in the above-mentioned conventional example. As shown in FIG. 12, an optical receiving amplifier circuit 10 provided immediately after converting an optical signal into an electric signal is roughly divided into an amplifier (feedback amplifier) 12 and a control circuit 14 for controlling the gain of the amplifier 12. Consists of A photodiode 15 serving as a light receiving element for converting an optical signal into a current signal, a power supply terminal 16 connected to a cathode of the photodiode 15, and an anode between the anode of the photodiode 15 and a ground point are provided before the amplifier 12. There is a floating capacitance 18. Reference number 20
Indicates, for example, burst-like optical signals (B1, B2, B3, B4) transmitted at predetermined time intervals.

The amplifier 12 includes a feedback amplifier 24 for amplifying an input current signal 22 converted into an electric signal by the photodiode 15, a buffer circuit 26 receiving the output of the feedback amplifier 24, and a resistor for determining the gain of the feedback amplifier 24. Vessel 2
8 and 30, a phase compensation capacitor 32 for compensating the phase of the output signal of the feedback amplifier 24, and a switch for controlling the gain and phase compensation, that is, an N-channel metal oxide semiconductor
(MOS) transistors 34 and 36 are provided. Reference numeral 38 indicates an output terminal of the optical receiving amplifier circuit 12.

On the other hand, the gain control circuit 14 comprises a comparator 40 and a set / reset type flip-flop (hereinafter simply referred to as FF).
42). The comparator 40 compares the output 44 of the buffer circuit 26 (that is, the output of the optical receiving amplifier circuit 12) with a reference voltage 46, and outputs a control signal 48 indicating a result of the comparison. The FF 42 is set and reset by a control signal 48 and a reset signal 50 (output from a control circuit (not shown) after completion of each burst signal). As described later, the output (gain control signal) 4 of the FF 42
Reference numeral 3 is used to control conduction / non-conduction (on / off) of the N-channel MOS transistors 34 and 36.
Reference numerals 46a and 50a indicate input terminals to which the reference potential 46 and the reset signal 50 are input, respectively. In the figure,
D and S attached to the MOS transistor indicate a drain and a source, respectively.

Before describing the operation of the optical receiving amplifier circuit (hereinafter sometimes simply referred to as an amplifier circuit) 10 shown in FIG. 12, a burst-like optical signal input to the light receiving element 15 will be briefly described.

As shown in FIG. 13, each of the burst-like optical signals B1, B2, B3, B4, etc. has a preamble signal (consisting of a repetition of logical values 1 and 0) and a data following the preamble signal. Signal. The preamble signal is used by the amplifier circuit 10 and subsequent circuits (not shown) to accurately capture the data signal. FIG.
, S1, S2, S3,... Shown at the lower part of FIG. L1 and L2
Indicates signal levels corresponding to logical values 1 and 0, respectively. The current signal input to the amplifier circuit 10 is an electric signal similar to the preamble signals S1, S2, S3,... Shown in FIG. The electric signals corresponding to the preamble signals S1, S2, S3 are denoted by U1, U2, U3 and the like.

The comparator 40 outputs the output signal 4 of the amplifier circuit 10.
4 during the time corresponding to the first preamble signal U1 of the burst signal, the voltage of the output signal 44 and the reference voltage 46
Compare with If the amplified output signal 44 is equal to or lower than the reference voltage 46, the output 48 of the comparator 40 has, for example, a logical value “0”. On the other hand, if the amplified output signal 44 exceeds the reference voltage 46, the output 48 of the comparator 40 becomes a logical value "1" (set signal). The FF 42 is set by the set signal, and the switch control signal 43, which is the output of the FF 42, becomes a logical value "1" and holds this state.

At an appropriate time before or after each burst signal, FF 42 is reset by reset signal 50. That is, the comparator 40 repeats the above-described comparison operation for each burst signal. Note that the comparator 40 has a function of detecting the start of the burst signal and performing a comparison operation within a predetermined time.

The switch control signal 43 having the logical value "1" by the setting of the flip-flop 42 turns on the N-channel MOS transistors 34 and 36. That is, the resistor 30 is connected in parallel with the resistor 28,
A phase compensation capacitor 32 is inserted in the feedback path.

The input current signal 22 (to be precise, the signal U
When 1) is large and the output signal 44 exceeds the reference voltage 46, the feedback resistance value of the amplifier 24 becomes the combined resistance value of the resistor 28 and the resistor 30, and the operation of lowering the amplification gain is performed. The transimpedance gain in the case where the gain control is not performed is represented by the following equation (1).

Transimpedance gain = {A / (A + 1)} · R ₂₈ (1) On the other hand, the transimpedance gain at the time of gain control is expressed by the following equation (2).

Transimpedance gain = {A / (A + 1)}｝ (R ₂₈ · R ₃₀ ) / (R ₂₈ + R ₃₀ )｝ (2) where A is the gain of the feedback amplifier 24 and R ₂₈ and R ₃₀ are
These are the resistances of the resistors 28 and 30, respectively.

[0018]

However, FIG.
The conventional amplifier circuit shown in (1) has the following problem.

Generally, in a PDS optical transmission system or the like, the current when converting an optical signal into a current signal is 0.1 μA to 1 μA.
It varies over a wide range of 00 μA. Therefore, 0.1μ
When a small input current of about A is amplified to an appropriate value,
When amplifying a large input current close to 00 μA, it is necessary to monitor the output voltage 44 and control the gain of the amplifier circuit 10.

As described above, in the conventional circuit shown in FIG. 12, the input signal 22 is not so large, and as a result, if the output voltage 44 is lower than the reference voltage 46, the gain control 14 does not operate. The gain is the gain represented by the above equation (1). On the other hand, when the input signal 22 is large and the output voltage 44 exceeds the reference voltage 46, the gain control switch 34 operates, and the gain of the amplifier 24 is calculated by the above equation (2).
Is obtained.

Here, in order for the circuit connected to the amplifier circuit 10 to operate normally, the output amplitude of the amplifier circuit 10 must be set to 50.
mV to 500 mV, the gain (represented by A) of the feedback amplifier 24 is 30, and the resistance values of the feedback resistance values 28 and 30 are R2
If 8 = 40 KΩ and R30 = 4.44 KΩ, the range (input dynamic range) of the signal current that can be input to the amplifier circuit 10 is 1.29 μA to 129 μA, and there is a problem that the input dynamic range is limited.

As a measure for avoiding this problem, for example, it is conceivable to control the gain of the amplifier circuit 10 in three stages. That is, a new resistor and switch (for example, N
Series circuit of channel MOS transistor)
8 and a new "series circuit of a phase compensation capacitor and a switch (for example, an N-channel MOS transistor)" is connected in parallel with the capacitor 32, and the gain control circuit 14 controls the opening and closing of these switches. Add flip-flops. However, by providing these new circuits, there is a problem that the stray capacitance on the input side of the amplifier circuit 10 increases and the cutoff frequency of the amplifier circuit 10 decreases.

Furthermore, in order to avoid the above-mentioned decrease in the cutoff frequency of the amplifier circuit 10, a new series circuit of a resistor and a switch (N-channel MOS transistor) may be connected in parallel with the N-channel MOS transistor 34. (In this case as well, the gain control of the amplifier circuit 10 is performed in three stages). However, when the "newly added switch" is turned on after the switch 34 in the conductive state (on) is turned off (off), there is another problem that it takes too much time for gain switching.

Therefore, the technical problem of the present invention is to reduce the cutoff frequency and increase the gain switching time without causing
An object of the present invention is to provide an optical receiving amplifier circuit corresponding to an input signal having a large dynamic range.

[0025]

In order to solve the above-mentioned problems, an optical receiving amplifier circuit according to the present invention is an optical receiving amplifier circuit for amplifying a current signal from a light-receiving element, comprising: A second amplifier circuit; the first and second amplifier circuits;
And a control circuit for receiving first and second control signals based on the outputs of the first and second amplifier circuits. The first and second amplifier circuits respectively include the first and second amplifier circuits. The gain changes according to the control signal, and the output of the second amplifier circuit is used as a signal output.

Further, in the optical receiving amplifier circuit according to the present invention,
In the optical receiving amplifier circuit, a feedback amplifier for amplifying the current signal, first and second feedback resistors for determining a gain of the feedback amplifier, and the first or second feedback resistor are connected to the first or second feedback resistor. A switching element that is inserted into or removed from the circuit according to a control signal.

Furthermore, in the optical receiving amplifier circuit according to the present invention,
In the optical receiving amplifier circuit, the second amplifier circuit includes:
A voltage amplifier, first and second resistors for determining the gain of the voltage amplifier, and first and second switch elements for inserting or removing the first and second resistors from the circuit, respectively. Have.

Further, in the optical receiving amplifier circuit according to the present invention,
In the optical receiving amplifier circuit, the control circuit compares a first reference voltage with an output of the first amplifier circuit.
, A second comparator for comparing the output of the second amplifier circuit with a second reference voltage, and a first set / reset type to which the output of the first comparator is input. A flip-flop, a second set / reset flip-flop to which an output of the second comparator is input, an inverting circuit connected to an output of the first flip-flop circuit, and an output of the inverting circuit. An AND circuit to which an output of the second flip-flop is input, an output of the first flip-flop being the first control signal, and an output of the AND circuit being the second control signal. It is characterized by the following.

Further, in the optical receiving amplifier circuit according to the present invention,
In the optical reception amplifier circuit, the current signal from the light receiving element is a burst signal, and the control circuit receives a head voltage value of the burst signal output from each of the first and second amplifiers. , Outputting the first and second control signals, and resetting the first and second control signals after the end of the burst signal.

In the optical receiving amplifier circuit according to the present invention, the optical receiving amplifier circuit further includes a peak value holding circuit for detecting and holding a peak value of an output of the first amplifier circuit; The amplifier circuit is a differential amplifier, and the differential amplifier receives an output of the first amplifier circuit at one input terminal, is held by the peak value holding circuit, and receives a peak value at the other input terminal, The differential output of the differential amplifier is input,
A threshold control circuit that controls each signal level of the differential output to be substantially equal; and the control circuit controls the operation of the threshold control circuit when switching the gain of the first and second amplifier circuits. It is characterized by stopping for a predetermined time.

Further, in the optical receiving amplifier circuit according to the present invention,
In the optical reception amplifier circuit, the control circuit stops the operation of the peak value holding circuit for a predetermined time when switching the gain of the first amplifier circuit.

Further, in the optical receiving amplifier circuit according to the present invention,
In the optical reception amplifier circuit, the threshold control circuit includes a peak value holding unit that detects and holds each peak value of a differential output of the differential amplifier, and the control circuit includes the first and second threshold values. When the gain of the second amplifier circuit is switched, the operation of the peak value holding means of the threshold control circuit is stopped for a predetermined time.

[0033]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram schematically showing an optical receiving and amplifying circuit according to a first embodiment of the present invention.

As shown in FIG. 1, a burst-like current signal 58 is applied to the light receiving amplifier circuit 60 from, for example, the light receiving element shown in FIG. The amplifier circuit 60 includes a first amplifier 62, a second amplifier 64, and a gain control circuit 66. The gain of the amplifier 62 is
6, the gain becomes one of two different gains (G1 and G2 (G1> G2)), while the gain of the amplifier 64 becomes the gain control signal M2 outputted from the gain control circuit 66. By the gain (G3 and G
4 (G3> G4)).

The gain control circuit 66 includes comparators 68 and 70
And a control circuit 72. The comparator 68 compares the voltage output 74 of the amplifier 62 with the reference voltage REF1 and outputs a binary signal C68 representing the comparison result. Similarly, the comparator 70 outputs the voltage output 78 of the amplifier 64 and the reference voltage RE78.
F2 and outputs a binary signal C70 representing the comparison result. That is, the voltage output 74 of the amplifier 62 becomes the reference voltage RE.
If it is equal to or less than F1, C68 becomes, for example, a logical value 0, and if the output 74 exceeds the reference voltage REF1, C68 becomes a logical value 1. Similarly, the voltage output 78 of the amplifier 64 is equal to the reference voltage R
If it is equal to or less than EF2, C70 has, for example, a logical value 0, and if the output 78 exceeds the reference voltage REF2, C70 has a logical value of 1.
Becomes

The amplifier 64 amplifies the output of the amplifier 62 with reference to the reference voltage REF3. Further, the control circuit 66
Reset signal RS after the end of each burst signal
T1 is input.

As shown in FIG. 2, when the input signal 58 is very small, the outputs C68 and C70 of the comparators 68 and 70 are both logical 0. In this case, the gain control signals M1 and M2 are both logical 0, and the gains of the amplifiers 62 and 64 are G1 and G3, respectively. Input signal 58
Becomes large, and the output 74 of the amplifier 62 becomes the reference value REF1.
And the output 78 of the amplifier 64 is equal to the reference value REF2
, The output C6 of the comparators 68 and 70
8 and C70 have logical values 0 and 1, respectively. In this case, the gain control signals M1 and M2 have logical values 0 and 1, respectively, and the gains of the amplifiers 62 and 64 are G1 and G, respectively.
It becomes 4.

Further, the input signal 58 becomes very large,
When the output 74 of the amplifier 62 exceeds the reference value REF1, the outputs C68 and C70 of the comparators 68 and 70 both have the logical value "1". In this case, the gain control signals M1 and M2 become logical values 1 and 0, and the gains of the amplifiers 62 and 64 become G2 and G3, respectively. The reason is that if the gain of the preamplifier 62 is reduced, it is not necessary to reduce the gain of the amplifier 64.

Next, the operation of the optical receiving amplifier circuit of FIG. 1 will be described in more detail with reference to the signal waveform diagram of FIG.

FIG. 3 shows the case of CASE 1 shown in FIG.
That is, the input signal 58 is very small and the comparators 68 and 7
7 shows a waveform in the case where both outputs C68 and C70 of 0 are logic values 0. Therefore, the gains of the amplifiers 62 and 64 are both maximum (that is, the gains are G1 and G3, respectively). FIG. 3A shows a current waveform input to the amplifier 62,
Waveforms U1 and U2 correspond to optical signal waveforms S1 and S2 in FIG.
Is equivalent to FIG. 3B shows a voltage output 74 of the amplifier 62.
(That is, an amplifier 6 whose input current waveform is inverted)
2 shows a waveform which is converted into a voltage and inverted. In this case, the output 74 does not intersect with the reference voltage REF1 (in this specification, since the input signal is inverted, the output 74 actually falls below the reference voltage REF1, but the expression “exceeds” the REF1 is used. May be used). Further, FIG.
(C) is a waveform of the voltage output 78 of the amplifier 64 (the output 74 of the preamplifier 62 is inverted). Again, the output 78 is below the reference voltage REF2 because the input signal 58 is very small. Therefore, as shown in FIGS. 3D and 3E, the gain control signals M1 and M2 both have the logical value 0, and the gains of the amplifiers 62 and 64 are not controlled to be reduced.

FIG. 4 shows the case of CASE2 shown in FIG.
That is, the waveforms are shown when the input signal 58 is somewhat large and the outputs C68 and C70 of the comparators 68 and 70 have logical values 0 and 1, respectively. Therefore, the amplifier 62 is at the maximum (G1), but the gain of the amplifier 64 is at the minimum (G4). 4A to 4E correspond to FIGS. 3A to 3E, respectively. In the case of CASE2, as shown in FIG. 4C, the voltage output 78 of the amplifier 64 exceeds the reference voltage REF2. Therefore, FIG.
And (E), the gain control signal M1 has a logical value of 0.
, But M2 has changed from logic 0 to 1. Therefore, the gain of the amplifier 64 decreases, and the level of the output (indicated by U2b) of the amplifier 64 corresponding to the input signal U2 decreases.

FIG. 5 shows the case of CASE3 shown in FIG.
That is, the input signal 58 is very large and the comparators 68 and 7
The waveforms when the outputs C68 and C70 of 0 are both logical values 1 are shown. Therefore, the amplifier 62 becomes minimum (G2) and the gain of the amplifier 64 becomes maximum (G3). That is,
If the gain of the amplifier 62 is minimized, it is not necessary to reduce the gain of the amplifier 64. As in the case of FIG. 4, FIG.
3E to 3E correspond to FIGS. 3A to 3E, respectively.
In the case CASE3, as shown in FIG. 5B, the voltage output 78 of the amplifier 62 exceeds the reference voltage REF2. Therefore, as shown in FIGS. 5D and 5E, the gain control signals M1 and M2 have the logical values 1 and 0, respectively, so that the gain of the amplifier 62 decreases and the gain of the amplifier 62 corresponding to the input signal U2 is reduced. As the level of the output (represented by U2a) decreases, the level of the output (U2b) of the amplifier 64 also decreases.

Therefore, the total gain of the optical receiving amplifier 60 is
G1 × G3 for CASE1, G1 × G4 for CASE2, and G2 for CASE3
× G3. Therefore, by appropriately setting the values of G1 to G4, it is possible to operate as an optical amplifier circuit having a desired output swing and a large dynamic range with respect to an input signal that changes over a wide range.

Next, the circuit of FIG. 6 showing a specific example of the optical reception amplifier circuit of FIG. 1 will be described in detail. In FIG. 6, portions corresponding to the blocks, signals, and the like in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 6, the amplifier 62 includes an inverting amplifier circuit 100, a first feedback resistor 102 connected between an input terminal and an output terminal of the inverting amplifier circuit 100, and an inverting amplifier circuit 100. A second feedback resistor 104 having one end connected to the input end; an N-channel MOS switch element having a source connected to the other end of the resistor 104 and a drain connected to the output end of the inverting amplifier circuit 100 A transistor 106.

Further, the amplifier 64 has resistors 108 and 110 for determining the gain of the amplifier, a P-channel MOS transistor 112 and an N-channel MOS transistor 114, which are switching elements for gain switching, and a differential amplifier 116. An inverting input terminal (inverting phase input terminal) of the differential amplifier 116 is directly connected to the sources of the MOS transistors 112 and 114, and a reference voltage REF3 is applied to a non-inverting input terminal (positive phase input terminal). Note that the connection relationship between the above-described elements is clear from the drawing, and thus the description is omitted.

The control circuit 72 which forms a part of the gain control circuit 66 includes RS flip-flops 118 and 120
, An inverter 122, and an AND circuit 124. The output terminal of the comparator 68 described with reference to FIG. 1 is connected to the set terminal S of the FF 118, and the output terminal of the comparator 70 is connected to the FF 12
0 is connected to the set terminal S. Further, the output terminal Q of the FF 118 is connected to the gate of the MOS transistor 106, and the output terminal of the AND circuit 124 is connected to the MOS transistor 1
12 and 114 are connected to the gates.

The operation of the optical receiving amplifier shown in FIG. 6 will be described. In the basic operation, the current signal 58 input to the amplifier circuit 62 is amplified and voltage-converted by the amplifier circuit 62, further amplified by the amplifier circuit 64, and sent to the next circuit (not shown).

Here, the inverting amplifier circuit 10 of the amplifier circuit 62
The gain of 0 is 30, and the resistance value of the feedback resistor 102 is 40K.
When the resistance value of the feedback resistor 104 is 0.4 KΩ, the transimpedance gain is expressed by the above equation (1) when gain control is not performed, and by the above equation (2) when gain control is performed. expressed. That is, N-channel MOS
When the transistor 106 is off, it becomes 38.7 KΩ, and when the N-channel MOS transistor 106 is on, it becomes 0.383 KΩ.

On the other hand, if the gain of the differential amplifier 116 constituting the amplifying circuit 64 is 22.2 dB, the resistance of the resistor 108 is 9 KΩ, and the resistance of the resistor 110 is 1 KΩ, the gain of the amplifier 64 becomes P channel MOS transistor 112
Is on and the N-channel MOS transistor 114 is off, 22.2 dB, and the P-channel MOS transistor 112 is off and the N-channel MOS transistor 114 is on, 2.2 dB.

Further, it is assumed that the reference voltage REF1 is 387 mV and the reference voltage REF2 is 500 mV. When the reset signal RST1 is input, the outputs of the FFs 118 and 120 both have the logical value 0. In this case, since the gain control signals M1 and M2 both have the logical value 0, both the N-channel MOS transistors 106 and 114 are off, and the P-channel MOS transistor 112 is on. That is, the amplifiers 62 and 64 both have the maximum gain (38.7 KΩ and 22.2 dB, respectively). Therefore, the total gain from the input to the output is a maximum of 500 KΩ.

Next, a case where a signal is input will be described. When the input signal amplitude is 0.1 μA, the output of the amplifier circuit 62 is 3.87 mV, and the output of the amplifier circuit 64 is 50 μm.
mV. This amplitude is equal to the reference voltages REF1 and RE
Since it is smaller than F2, both outputs of the comparators 68 and 70 do not change at the logical value 0. That is, as described above, the total gain is 500 KΩ, and the amplitude of the output signal is 50 mV.

When the input signal 58 is 1 μA or less, the output of the amplifier circuit 62 is 38.7 mV and the output of the amplifier 64 is 500 mV or less. Therefore, the gain does not change and the maximum gain remains.

On the other hand, when the input signal exceeds 1 μA, the output of the amplifier circuit 64 becomes 500 mV, which is the reference voltage REF1.
Beyond. As a result, the output of the comparator 70 becomes the logical value 1, and the FF 120 is set. Since the output of the other FF 118 is a logical value 0, the output of the AND 124 is a logical value 1, and the N-channel MOS transistor 114 is turned on and the P-channel MOS transistor 112 is turned off. Therefore, the gain of the amplifier 64 drops to 2.2 dB, the total gain becomes 50 KΩ, and is held until the next reset signal is input.

Further, the input signal 58 becomes large and becomes 10 μA.
, The output amplitude of the amplifier circuit 62 exceeds 387 mV. As a result, the output of the comparator 68 has the logical value 1, and the output of the AND circuit 124 has the logical value 0. Therefore, N-channel MOS transistor 106 and P-channel MOS transistor 112 are turned on, and N-channel MOS transistor 114 is turned off. Therefore,
The gain of the amplifier circuit 62 is 0.387 KΩ, the gain of the amplifier circuit 64 is 22.2 dB, the total gain is reduced to 5 KΩ, and the output signal amplitude is 50 mV at 10 μA.
In this state, the output amplitude becomes 500 mV in the gain state when the input signal 58 rises to 100 μA.

As described above, by changing the gain of each of the two amplifier circuits connected in series, a desired output can be obtained from an input signal whose amplitude changes greatly.

Next, a second embodiment of the present invention will be described.

FIG. 7 is a block diagram schematically showing the second embodiment. As shown in FIG. 7, the optical receiving amplifier 200 according to the second embodiment includes an amplifying circuit 202 in front,
Peak value holding circuit 204 and second-stage amplifier circuit 206
, A threshold control circuit 208, and a control circuit 210. Note that a digital signal generator 212 is disposed after the optical receiving amplifier 200. The control circuit 210 receives reference voltages REF4 and REF5 and a reset signal RST2. Note that in the second embodiment, the first
The gain switching described in the embodiment is applied.

In the second embodiment, the optical receiving amplifier 20
A threshold control circuit 208 is provided at the last stage of 0. Therefore, the threshold value input to the subsequent digital signal generator 212 can be effectively adjusted, and there is an advantage that the output level accuracy required for the amplifier 206 is reduced.

As described above, in the first embodiment, the reference voltage REF 3 input to the amplifier 64 is fixed. However, it is difficult to accurately amplify a signal having a large input dynamic range (input that changes greatly) using a fixed reference voltage. Therefore, the second
In this embodiment, the peak value of the output of the preamplifier is detected and held instead of the reference voltage REF 3 , and this peak value is used as the reference voltage of the second amplifier 206.

Further, in the second embodiment, as described later, when the gain of the amplifier circuit 202 or 206 is switched,
The operation of the threshold control circuit 208 is stopped until the output of the amplifier circuit 202 or 206 is stabilized.

FIG. 8 is a circuit diagram showing the blocks of FIG. 7 in detail. 8, the amplifying circuit 202 includes an inverting amplifier 214, feedback resistors 216 and 218 for determining the gain of the amplifier 214, and an N-channel MOS transistor 220 as a switching element. This configuration is the same as the configuration of the amplifier 62 in FIG. 6, and therefore, further description will be omitted.

The peak value holding circuit 204 is
2 is a known circuit that detects and holds the peak value of the output of No. 2. The voltage value held in the peak value holding circuit 204 is applied to an inverting input terminal of a differential amplifier 222 forming a part of the amplifier circuit 206.

The differential amplifier 222 includes a differential amplifier 222
A feedback resistor 22 is connected between the inverting output terminal and the non-inverting input terminal.
4 and a series circuit of an N-channel MOS transistor 228 serving as a switch element, and another feedback resistor 226 connected in parallel to the series circuit. Similarly, between a non-inverting output terminal and an inverting input terminal of the differential amplifier 222, a series circuit of a feedback resistor 232 and an N-channel MOS transistor 234 serving as a switch element, and a feedback resistor connected in parallel to the series circuit. Unit 230 is connected. Amplifier circuit 2
Since 06 itself is publicly known, detailed description is omitted.

The threshold value control circuit 208 includes peak value holding circuits 236 and 238 having a known circuit configuration,
40, 242, 244 and 246. As shown, the peak value holding circuits 236 and 238 respectively detect the peak value in response to the non-inverted and inverted output of the differential amplifier 222, and hold the values. At a connection point 241 between the resistors 240 and 242, the peak value of the non-inverted output of the differential amplifier 222 and the inverted output of the differential amplifier 222 are combined.
At the connection point 245 between the resistors 244 and 246, the peak value of the inverted output of the differential amplifier 222 and the non-inverted output of the differential amplifier 222 are combined. Therefore, the connection points 241 and 24
5 is controlled so that the non-inversion and inversion voltage values are equal.

The output of the threshold control circuit 208 is input to the non-inverting and inverting input terminals of the differential amplifier 260 of the digital signal generator 212. The output of the differential amplifier 260 is limited to a predetermined amplitude value by an amplitude limiter 262, and a binary digital signal is generated.

Control circuit 210 includes comparators 248 and 25
0, RS flip-flops 252 and 254, an OR circuit (OR circuit) 256, and a delay circuit 258.

The comparator 248 outputs the output 26 of the amplifier 202.
4 and the reference voltage REF4. If the output 264 is equal to or less than the reference voltage REF4 (the output 264 is equal to the reference voltage REF4).
If the output 264 exceeds the reference voltage REF4 (if the output 264 exceeds the reference voltage R4), the logical value 0 is output.
Output a logical value of 1 (if it crosses EF4). This logical value 1 becomes a reset signal CL1 of the peak value holding circuits 204, 236 and 238, and also becomes a set signal to the FF 252. When set, the FF 252 outputs a gain control signal M3 (logical value 1) for decreasing the gain of the amplifier 202 until reset by the reset RST2.

On the other hand, the comparator 250 includes a differential amplifier 222
Is compared with the reference voltage REF5, and if the output 266 is equal to or less than the reference voltage REF5 (the output 266).
Outputs a logical value 0 (if does not intersect with reference voltage REF5), and outputs 266 if output 266 exceeds reference voltage REF5 (output 2).
It outputs a logical 1 (if 66 crosses the reference voltage REF5). This logical value 1 is used for the peak value holding circuits 236 and 2
At the same time, the reset signal CL2 becomes a set signal for the FF 254. When set, the FF 254 outputs a gain control signal M4 (logical value 1) for decreasing the gain of the differential amplifier 222 until reset by the reset RST2.

Referring to FIGS. 9 to 11, FIGS.
The operation of the circuit will be described in more detail.

FIG. 9 shows that the input signal 198 is very small,
The waveform when the outputs of the comparators 248 and 250 are both logical 0 is shown. Therefore, the gains of the amplifiers 202 and 206 are both maximized (that is, the gains are G1 and G3, respectively). FIG. 9A shows a current waveform input to the amplifier 202, and waveforms U1 and U2 correspond to the optical signal waveform S of FIG.
1 and S2. FIG. 9B shows the waveform of the voltage output 203 of the amplifier 202 (ie, the input current waveform is converted to a voltage by the inverting amplifier 214 and then inverted). In this case, the output 203 of the amplifier 202 does not cross the reference voltage REF4. The peak value holding circuit 204 holds and outputs the peak value of the output 264 of the amplifier 202.

Further, as shown in FIG. 9C, the voltage output waveform of the amplifier 206 is a non-inverted (positive phase) and inverted (negative phase) differential waveform. Again, because the input signal 198 is very small, the non-inverted output
Does not cross the reference voltage REF5. Therefore, as shown in FIGS. 9D and 9E, the gain control signal M3
And M4 are both logical 0, and similarly, the reset signals CL1 and CL2 are also logical 0. Therefore,
Both amplifiers 202 and 206 are not controlled to reduce their gain. In this case, as shown in FIG. 9 (F), the levels of the non-inverted and inverted outputs of the threshold control circuit 208 are equal, and as shown in FIG. 9 (G), the digital signal is changed from the first signal U1. Occurs normally.

Generally, when the input signal 198 has a minimum value of 0.1 μm.
Assuming that the transimpedance gain of the amplifier 202 is 50 KΩ and the gain of the amplifier 206 is 20 dB, the amplitude of the output voltage of the amplifier 206 at this time is 50 m
V. Here, if the threshold value is shifted by 5 mV, the minimum light receiving sensitivity is degraded by 10%. However, the difference between the threshold values of the non-inverted and inverted output of the amplifier 206 is corrected by the threshold control circuit 208 provided at the subsequent stage. Further, since the minimum input amplitude to the threshold control circuit 208 is 50 mV, the sensitivity can be improved about 10 times as compared with the case where the threshold control circuit 208 is not provided.

FIG. 10 shows that the input signal 198 is somewhat large, the comparator 248 outputs a logical value of 0,
Shows a waveform when a logical value 1 is output. Therefore, the gain of the amplifier 202 is the maximum (G1), but the gain of the amplifier 206 is
Is minimum (becomes G4). (A) to (G) of FIG. 10 correspond to (A) to (G) of FIG. 9, respectively. In this case, as shown in FIG.
6 crosses the reference voltage REF5. Therefore, as shown in FIG. 10D, the gain control signal M3 has a logical value of 0, but the gain control signal M4 has changed from a logical value of 0 to 1.

Further, as shown in FIG. 10E, the reset signal CL1 remains at the logical value 0, but the other reset signals CL2 change from the logical value 0 to 1. The reset signal CL2 is delayed by a predetermined time only in the falling portion in the delay circuit 258, and the peak value holding circuit 23
6 and 238. The above-mentioned predetermined time is a time until the output of the amplifier 206 becomes stable, and the next signal U
By the time 2 is input, the gain is controlled and stabilized. For this reason, the peak value holding circuits 236 and 238 stop capturing the peak value during the predetermined time. Therefore, the threshold control circuit 208 operates normally from the next signal U2. This is shown in FIG. Further, FIG.
As shown in (G) of 0, the digital signal is normally output from the input signal U2. Note that the box marked with an X in FIG. 10G indicates that the output waveform of the digital signal generator 212 cannot be specified.

FIG. 11 shows a waveform when the input signal 198 is very large, the comparator 248 outputs a logical value 1, and as a result, the comparator 250 also outputs a logical value 1. In this case, if the gain of the amplifier 202 is minimized (G2), the gain of the amplifier 206 may remain at the maximum (G3).
(A) to (G) of FIG. 11 correspond to (A) to (G) of FIG. 9, respectively. In the above case, as shown in FIG. 11B, the voltage output 264 of the amplifier 202 crosses the reference voltage REF4. Therefore, FIG.
As shown in FIG. 7, the gain control signal M4 remains at the logical value 0, but the gain control signal M3 changes from the logical value 0 to 1.

Further, as shown in FIG. 11E, the reset signal CL1 changes from the logical value 0 to 1. This is because when the output of the amplifier 202 decreases due to the decrease in the gain, the output of the amplifier 206 also decreases.
04 needs to be reset. Further, FIG.
Similarly to the case of 0, a reset signal CL2 is generated, and only the falling portion is delayed by a predetermined time in the delay circuit 258 and is applied to the peak value holding circuits 236 and 238. Therefore, the threshold control circuit 208 outputs the next signal U2
Works fine from. This state is shown in FIG. Further, as shown in FIG. 11 (G), the input signal U2
Output a digital signal normally.

Although the embodiment of the present invention has been described in detail, the present invention is not limited to an amplifier for optical reception. The present invention can be widely applied to a circuit for amplifying a signal having a wide dynamic range.

[0080]

As described above, in the optical receiving amplifier circuit according to the first embodiment of the present invention, the gain of two cascaded amplifiers is adjusted according to the level of the output signal of each amplifier. Since switching is performed individually, a desired output signal level can be obtained even for a signal having a wide input dynamic range. Further, according to the optical reception amplifier circuit of the second embodiment of the present invention, the influence of the amplification output level which changes instantaneously due to the gain switching of the amplifier can be eliminated in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram of an optical receiving amplifier according to a first embodiment of the present invention.

FIG. 2 is a diagram showing logical values of signals for explaining the operation of FIG. 1;

FIG. 3 is a signal waveform diagram for explaining the operation of the optical receiving amplifier shown in FIG.

FIG. 4 is a signal waveform diagram for explaining the operation of the optical receiving amplifier shown in FIG.

FIG. 5 is a signal waveform diagram for explaining the operation of the optical receiving amplifier shown in FIG.

FIG. 6 is a detailed circuit diagram of the optical receiving amplifier shown in FIG.

FIG. 7 is a block diagram of an optical receiving amplifier according to a second embodiment of the present invention.

8 is a detailed circuit diagram of the optical receiving amplifier shown in FIG.

FIG. 9 is a signal waveform diagram for explaining the operation of the optical receiving amplifier shown in FIGS. 7 and 8;

FIG. 10 is a signal waveform diagram for explaining the operation of the optical receiving amplifier shown in FIGS. 7 and 8;

FIG. 11 is a signal waveform diagram for explaining the operation of the optical receiving amplifier shown in FIGS. 7 and 8;

FIG. 12 is a block diagram of an optical reception amplifier circuit according to a conventional example.

FIG. 13 is a schematic diagram of a burst-like optical signal used in the present invention and a conventional example.

FIG. 14 is a diagram showing the burst-shaped optical signal of FIG. 13 in more detail;

[Explanation of symbols]

 62, 64 Amplifier 66 Control circuit 202, 206 Amplifier 204 Peak value holding circuit 208 Threshold control circuit 210 Control circuit

Claims (5)

(57) [Claims] 1. An optical receiving amplifier circuit for amplifying a current signal from a light receiving element , comprising: a first amplifier circuit;
A second amplifier circuit, which is a differential amplifier connected in series to the circuit
And provided between the first and second amplifier circuits,
A peak for detecting and holding the peak value of the output of the first amplifier circuit.
And a differential value output from the differential amplifier.
So that the signal levels of the differential outputs are almost equal.
And a threshold control circuit for controlling, wherein the control circuit comprises:
When switching the gains of the first and second amplifier circuits,
An optical reception amplifier circuit for stopping the operation of the threshold control circuit for a predetermined time . 2. The first amplifier circuit includes a feedback amplifier for amplifying the current signal, first and second feedback resistors for determining a gain of the feedback amplifier, and the first or second feedback resistor. 2. The optical receiving amplifier circuit according to claim 1, further comprising: a switch element for inserting or removing a circuit from or into the circuit according to the first control signal. 3. The differential amplifier of claim 1 , wherein
The output is received at one input terminal and stored in the peak value holding circuit.
2. The optical receiving amplifier circuit according to claim 1, wherein the held peak value is received at the other input terminal . 4. The control circuit according to claim 1 , wherein
When switching the gain, the operation of the peak value holding circuit
2. The optical receiving amplifier circuit according to claim 1, wherein the optical receiving amplifier is stopped for a predetermined time . 5. The threshold control circuit according to claim 1 , wherein
Peak value to detect and hold each peak value of differential output
Holding means, wherein the control circuit includes the first and second
When switching the gain of the amplifier circuit, the threshold control circuit
Stop the operation of the peak value holding means for a predetermined time.
The optical receiving amplifier circuit according to claim 1, wherein: