JP3322978B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a thin film transistor used as a switching element in a liquid crystal display device or the like.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor having a structure shown in FIG. 7 is known. This thin film transistor has a gate electrode 42 on an insulating substrate 41 as shown in FIG.
Is formed on the substrate 41 so as to cover the gate electrode 42, and the gate insulating film 43
A semiconductor layer 44 is formed above the gate electrode 42.

The semiconductor layer 44 is ion-implanted from above the channel protection film 45 patterned thereon, so that the semiconductor layer 44 under the channel protection film 45 is formed.
The contact layers 46a and 46b doped with impurities are formed on both sides of the gate insulating film 43, and the source electrode 47 and the drain electrode 48 are formed over the contact layers 46a and 46b.

[0004]

In the case of a conventional thin film transistor, the contact layer 46 implanted with impurities is used.
If the thicknesses of the a and b are small, the source electrode 47 and the contact layer 46a and the drain electrode 48 and the contact layer 46
b and a resistance component existing in the thickness direction between the channel portion of the semiconductor layer 44. This resistance component has an adverse effect on the switching characteristics of pixels when the active matrix liquid crystal display has a large area and high definition. Therefore, it is desirable that this resistance component be as small as possible.

Further, in the case of a conventional thin film transistor,
The impurity-implanted contact layers 46a and 46b are formed with a large overlap in the vertical direction shown in FIG. 7 with the gate electrode 42, and the source electrode 47 and the drain electrode 48 on the contact layers 46a and 46b are also formed with the contact layers 46a and 46b. It is formed with a large overlap with the gate electrode 42 via the channel protection film 45 and the channel protection film 45.

When the source electrode 47 and the drain electrode 48 overlap with the gate electrode 42 as described above, a parasitic capacitance occurs at the overlapping portion. If this parasitic capacitance is large,
When used as a switching element of a pixel of an active matrix liquid crystal display, the effect of feedthrough of a scanning signal applied to the gate electrode 42 appears on a voltage written to the pixel. Therefore, it is desirable that this parasitic capacitance be as small as possible.

However, in the conventional method, it is difficult to reduce the overlapping portions of the contact layers 46a and 46b, the source electrode 47, the drain electrode 48, and the gate electrode 42, which cause a parasitic capacitance, due to the mask positioning accuracy. Met. That is, if the overlapping portion is not provided at 2 μm or more in terms of mask positioning accuracy, a gap is formed between the source electrode 47 and the drain electrode 48 and the gate electrode 42,
There is a possibility that a transistor that does not operate may be formed.

[0008] Further, in order to put large-area, large-capacity, high-density active-matrix liquid crystal displays to practical use and to reduce the defective rate during production, it is necessary to simplify the manufacturing method.

The present invention has been made to solve the problems of the prior art, and provides a method of manufacturing a thin film transistor capable of minimizing a resistance component existing in a thickness direction of a channel region of a semiconductor layer as much as possible. The purpose is to do.

Another object of the present invention is to provide a method of manufacturing a thin film transistor which can minimize the parasitic capacitance between the source and drain electrodes and the gate electrode.

Another object of the present invention is to provide a method for realizing the above-described thin film transistor by self-alignment.

Still another object of the present invention is to simplify a manufacturing process of a thin film transistor.

[0013]

According to a method of manufacturing a thin film transistor of the present invention, a gate electrode, a gate insulating film, a semiconductor layer serving as a channel region, an insulating layer serving as a channel protective film, and a resist film are sequentially laminated on an insulating substrate. By exposing the resist film from the back side of the insulating substrate, a resist mask self-aligned with the gate electrode is formed, and the channel protective film and the semiconductor layer are patterned in accordance with the resist mask. Then, a semiconductor impurity is injected into the side surface of the semiconductor layer, a metal layer to be a source electrode and a drain electrode is formed, and the resist mask is peeled off to form a source electrode and a drain electrode.

Further, a gate electrode, a gate insulating film, a semiconductor layer serving as a channel region, and a resist film are sequentially formed on an insulating substrate, and the resist film is exposed from the back surface side of the insulating substrate. A resist mask self-aligned with the gate electrode is formed, the semiconductor layer is patterned according to the resist mask, semiconductor impurities are implanted into side portions of the semiconductor layer, and then a metal layer serving as a source electrode and a drain electrode is formed. Is formed, and the source electrode and the drain electrode are formed by removing the resist mask.

[0015]

According to the present invention, a contact layer is provided on a side surface of a semiconductor layer and a source electrode and a drain electrode are continuously formed on the contact layer. The resistance component can also be made extremely small. Further, since a contact layer is provided on a side surface of the semiconductor layer and a source electrode and a drain electrode are formed continuously with the contact layer, there is no overlapping portion between the source electrode, the drain electrode, and the gate electrode. Therefore, it is possible to suppress the occurrence of parasitic capacitance caused by the overlap of the source electrode and the drain electrode with the gate electrode, and when used as a switching element of a pixel of an active matrix liquid crystal display, a scanning signal applied to the gate electrode with respect to a voltage written to the pixel. Can reduce the effect of feedthrough.

Further, according to the present invention, there is provided a method of manufacturing a thin film transistor in which a resistance component in a thickness direction of a channel region of a semiconductor layer is extremely small and generation of a parasitic capacitance caused by overlapping of a source electrode, a drain electrode and a gate electrode is suppressed. Can be provided.

In the present invention, by providing a contact layer on the side surface of the semiconductor layer, the semiconductor layer and the channel protective film can be formed in the same step. Thereby, one photomask can be omitted.

Furthermore, by using the resist mask used for patterning the semiconductor layer as a mask for impurity ion implantation, one thin film deposition step, one etching step, and one photomask can be omitted.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a thin film transistor according to the present invention will be described below. FIG. 1 shows a part of a thin film transistor manufactured by the manufacturing method of the present invention.
FIG. 2 shows a cross-sectional structure taken along line AA of FIG. The thin film transistor includes a gate electrode 12a formed on a substrate 11, a gate insulating film 13 covering the gate electrode 12a, a semiconductor layer 14 formed on the gate insulating film 13, and a channel formed on the semiconductor layer 14. Protective film 15, contact layers 16a and 16b formed on both side surfaces of semiconductor layer 14, and contact layers 16a and 1b.
6b and a source electrode 17 and a drain electrode 18 which cover a part of the gate insulating film 15 and are formed separately on both sides.

Next, a method for manufacturing a thin film transistor will be described with reference to FIG. In this method of manufacturing a thin film transistor, first, as shown in FIG. 3A, a gate electrode 12a is formed on a transparent insulating substrate 11 such as glass. The gate electrode 12a is made of a single-layer or multi-layer metal such as Ta, Ti, Al, Cr, Cu, etc.
1, a thickness of 100 nm to 300 nm, preferably 150 nm
It is fabricated by depositing about nm and then patterning. At this time, a gate bus line 12b (see FIG. 1) having a gate electrode 12a branched on the way is formed at the same time.

Next, the substrate 1 on which the gate electrode 12a is formed
A gate insulating film 13 is formed on 1. The gate insulating film 13 is formed by depositing a single-layer or multilayer insulating film of SiNx, TaOx, or the like formed by, for example, a P-CVD method or a sputtering method to a thickness of 300 nm to 500 nm, preferably about 400 nm.

Next, the semiconductor layer 1 is formed on the gate insulating film 13.
4 and a channel protection film 15 are deposited. This semiconductor layer 1
4 is a-Si having a thickness of 20 by P-CVD, for example.
The channel protective film 15 is deposited, for example, by P-CVD.
It is formed by depositing SiNx by a method with a thickness of 200 nm to 400 nm, preferably about 300 nm.

Next, by performing photolithography, FIG.
As shown in (B), the semiconductor layer 14 and the channel protective film 1
5 is patterned. At this time, a resist mask 19 is formed by exposing the resist film to light from the back surface of the substrate 11, and the semiconductor layer 14 and the channel protective film 15 are self-aligned with the gate electrode 12a to be patterned.

Next, as shown in FIG. 3C, implantation of impurity ions such as P ⁺ is performed. At this time, the resist mask 19 used for forming the pattern of the semiconductor layer 14 and the channel protective film 15 is left without being stripped and used as an implantation mask. The implantation of the impurity ions is performed by, for example, a non-mass separation type ion doping apparatus, and by utilizing the fact that the impurity ions are injected around the resist mask 19 and the channel protective film 15 and implanted into the side surfaces of the semiconductor layer 14, The contact layers 16a and 16b are formed on the side surfaces of the layer 14. These contact layers 16a and 16b
Is formed from the side surface of the semiconductor layer to the inside of 20 to 150 nm. That is, when the thickness is 20 nm or less, it becomes difficult to make ohmic contact, and the off-state current of the transistor increases. In the case of 150 nm or more,
Ion implantation becomes difficult.

Next, as shown in FIG. 3D, metal layers 17 and 18 serving as a source electrode 17 and a drain electrode 18 are formed.
Deposit 20. The metal layers 17, 18, and 20 are formed by depositing a single layer or multiple layers of Al, Ti, MoSi, or the like by, for example, a sputtering method, and have a thickness of 200 nm or more.
It is deposited to a thickness of 400 nm, preferably about 300 nm.

Next, the metal layer 20 is lifted off using the resist mask 19 to form the source electrode 17 and the drain electrode 18 shown in FIG.

As described above, the contact layers 16a and 16b are formed on the side surfaces of the semiconductor layer 14, and the contact between the source electrode 17 and the drain electrode 18 and the semiconductor layer 14 is performed on the side surfaces of the semiconductor layer 14. The series resistance between the contact layers 16a and 16b can be reduced.

Further, the source electrode 1 is formed on the side surface of the semiconductor layer 14.
7 and the drain electrode 18, and by forming the source electrode 17 and the drain electrode 18 by lift-off, the gate electrode 12 a
And the generation of parasitic capacitance at the overlapping portion of the source region and the drain region.

In addition, as described above, the resist mask 19
Is implanted from above, no impurity is implanted into the upper portion of the channel protective film 15. Therefore, current leakage does not occur between the contact layers 16a and 16b and the source electrode 17 and the drain electrode 18 through the impurities.

Further, since the patterning of the semiconductor layer 14 and the channel protective film 15 is performed simultaneously,
It is possible to reduce the number of steps and the manufacturing time, and to enjoy a simplified and efficient manufacturing process.

FIGS. 4 and 5 show another embodiment of the present invention. In this embodiment, a method of manufacturing an active matrix substrate having no channel protective film is shown. That is, similarly to FIG. 3 of the above embodiment, a gate electrode 22 is formed on a transparent insulating substrate 21 such as glass, and a gate insulating film 23 and a semiconductor layer 24 are formed on the gate electrode 22 by, for example, a P-CVD method. Is deposited.

Next, photolithography is performed to obtain FIG.
The semiconductor layer 24 is patterned as shown in FIG.
At this time, the semiconductor layer 24 is self-aligned with the gate electrode 22 and patterned in the same manner as in the above embodiment. Then, as shown in FIG. 5 (C), the resist mask 28 patterned by the photolithography is used as an implantation mask without being stripped, and impurity ions are implanted from above into the side surface of the semiconductor layer 24 to form a contact layer. 25a and 2
5b is formed. At this time, as shown in FIG. 6, before performing ion implantation, a resist mask 38 is formed on the semiconductor layer 3.
The ion implantation may be performed after reducing the size slightly compared to the case of FIG. That is, after the semiconductor layer 34 is etched by patterning the resist mask 38, the semiconductor layer 34 is again patterned into a reduced shape, oxygen plasma is irradiated to pattern the reduced shape, or the resist mask 38 is baked at a high temperature to reduce the reduced shape. After patterning, ion implantation is performed.

Next, as shown in FIG. 5D, metal layers 26 and 2 serving as a source electrode 26 and a drain electrode 27 are formed.
7, 29 are deposited. Then, the metal layer 29 is lifted off using the implantation mask 28 to form the source electrode 26 and the drain electrode 27 shown in FIG.

According to this embodiment, the same effect as that of the above embodiment, that is, the source electrode 26 and the drain electrode 2 are formed.
By making contact between the semiconductor layer 24 and the semiconductor layer 24 on the side surface of the semiconductor layer 24, the series resistance between the channel portion and the contact layers 25a and 25b can be reduced, and furthermore, the gate electrode 22 overlaps the source region and the drain region. It is possible to minimize the occurrence of the generated parasitic capacitance, to reduce the number of steps and the manufacturing time, and to provide a simplified and efficient manufacturing process. In addition, as shown in FIG. 6, before the ion implantation is performed, the resist mask 38 is slightly reduced in size as compared with the semiconductor layer 34, so that the impurity ions can be more efficiently implanted into the side surfaces of the semiconductor layer 34.

[0035]

As described above, in the production method of the present invention,
It is possible to provide a method of manufacturing a thin film transistor in which a resistance component in a thickness direction of a channel region of a semiconductor layer is extremely small, and a generation of a parasitic capacitance caused by overlapping of a source electrode, a drain electrode, and a gate electrode is suppressed. Can be simplified.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a structure of a thin film transistor formed by a manufacturing method of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a process chart showing a production method of the present invention.

FIG. 4 is a cross-sectional view illustrating a structure of a thin film transistor formed by another manufacturing method of the present invention.

FIG. 5 is a process chart showing another manufacturing method of the present invention.

FIG. 6 is a view showing another example of the process of another manufacturing method of the present invention.

FIG. 7 is a cross-sectional view illustrating a structure of a conventional thin film transistor.

[Explanation of symbols]

10: Pixel electrode, 11, 21, 31, 41 ... Substrate, 12a, 22, 32, 42 ... Gate electrode, 12
b: gate bus line, 13, 23, 33, 43
..Gate insulating films, 14, 24, 34, 44... Semiconductor layers, 15, 45... Channel protective films, 16a, 16
b, 25a, 25b, 35a, 35b, 46a, 46b
... contact layer, 17, 26, 47 ... source electrode, 17a ... source bus line, 18, 27, 4
8 ... drain electrode, 19, 28, 38 ... resist mask, 20, 29 ... metal film

Claims (3)

(57) [Claims] 1. A gate electrode, a gate insulating film, a semiconductor layer serving as a channel region, an insulating layer serving as a channel protective film, and a resist film are sequentially laminated and formed on an insulating substrate, and the gate electrode, the gate insulating film, and a resist film are sequentially stacked. By exposing the resist film, a resist mask self-aligned with the gate electrode is formed, and the channel protective film and the semiconductor layer are patterned in accordance with the resist mask, and semiconductor impurities are implanted into side surfaces of the semiconductor layer. Then, a metal layer to be a source electrode and a drain electrode is formed, and the resist mask is peeled off to form a source electrode and a drain electrode. 2. A gate electrode, a gate insulating film, a semiconductor layer serving as a channel region, and a resist film are sequentially laminated and formed on an insulating substrate, and the resist film is exposed from the back surface side of the insulating substrate. A resist mask self-aligned with the gate electrode is formed, the semiconductor layer is patterned according to the resist mask, semiconductor impurities are implanted into side portions of the semiconductor layer, and then a metal layer serving as a source electrode and a drain electrode is formed. And forming a source electrode and a drain electrode by removing the resist mask. 3. The method according to claim 2, wherein, after patterning the semiconductor layer, the resist mask is reduced and a semiconductor impurity is implanted into the semiconductor layer.