JP3322620B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a liquid crystal display device, and more particularly to a display device for protecting a display device and a drive circuit thereof.

[0002]

2. Description of the Related Art Display devices, for example, JP-A-8-13689.
In the liquid crystal display device disclosed in Japanese Unexamined Patent Application Publication No. 3 (1993), a device for protecting the liquid crystal display device and its driving circuit is devised. That is, after a display control signal sent from an external device such as a personal computer is activated to control on / off of the liquid crystal display, the power supply voltage is at a specified value, and a frame signal is supplied. On condition that
By adding a circuit for activating the drive circuit of the display, it is possible to prevent the application of a direct current to the liquid crystal display and the destruction of the drive circuit caused by the abnormal control sequence.

However, the conventional circuit configuration has the following problems. That is, after the display control signal sent from the external device is activated, the drive circuit of the display is activated on the condition that the power supply voltage is at the specified value and the frame signal is supplied. Even if, for example, the supply of a scanning clock signal for changing the scanning position of a scanning line is stopped due to an abnormality in a signal sent from an external device, only a specific scanning line is selected, and the scanning line is selected. The state in which the voltage is applied only to the liquid crystal in the portion along the line continues. As a result, a state in which a DC voltage is applied to a portion of the liquid crystal along the scanning line causes deterioration of the liquid crystal.
Even when the display is other than the liquid crystal display, if the state where the voltage is applied to only a specific scanning line continues, the characteristics of the display element in that portion may be deteriorated.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above points, and it is an object of the present invention to reliably protect a display and its driving circuit even when an abnormality occurs in a control sequence. One of Another object is to provide the protection circuit with a simple configuration.

[0005]

According to the present invention, there is provided a display in which a plurality of scanning lines and a plurality of data lines are arranged in a matrix and pixels are formed at intersections thereof, and a periodicity indicating the start of a frame is provided. A scanning line driving circuit for starting scanning of the plurality of scanning lines by a frame signal and sequentially selecting the scanning lines by a scanning clock signal indicating a scanning period; and a data line driving circuit for driving the plurality of data lines based on display data. A display device comprising: a circuit; and a control circuit that outputs an activation signal for activating the scan line driving circuit and the data line driving circuit to an operation thereof. Voltage detecting means for detecting whether or not the voltage is equal to or higher than a specified value; AND means for outputting a logical product of an output of the detecting means and a display control signal sent from the outside; A monostable multivibrator having a clock signal connected to a trigger input terminal and an output of the AND means connected to a clear terminal, wherein an output of the monostable multivibrator is used as the activation signal. I do.

[0006]

The output holding time of the monostable multivibrator can be set longer than a maximum retrace period set between frames. Further, the control circuit includes a flip-flop that supplies a frame signal to a clock terminal and supplies an output of the monostable multivibrator to a clear terminal.
While the output is held at the L level, the output is held at the L level. When the clear terminal is held at the H level, the output is switched from the L level to the H level by the rising edge of the first frame signal applied to the clock terminal, and the H level is set. The feature is to keep the level.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings, taking a liquid crystal display device as an example. As shown in FIG. 1, the liquid crystal display device 1 includes a liquid crystal display 2, a scanning line driving circuit 3, a data line driving circuit 4, and a power supply circuit 5.
, A control circuit 6, and a wiring 7 for connection to an external device.

The liquid crystal display 2 has a dot matrix structure in which a plurality of scanning lines 21 and a plurality of data lines 22 are arranged in a matrix and pixels are formed at intersections thereof. The liquid crystal display 2 has a simple matrix type in which a plurality of scanning lines are formed on one substrate, a plurality of data lines are formed on the other substrate, and a liquid crystal is sandwiched between the substrates, or An active matrix type in which a plurality of scanning lines and a plurality of data lines are formed, switching elements are provided at intersections thereof, a common electrode is formed on the other substrate, and a liquid crystal is sandwiched between the substrates. Can be.

The scanning line drive circuit 3 starts scanning the plurality of scanning lines 21 by a periodic frame signal FLM indicating the start of a frame, and sequentially selects the scanning lines 21 by a scanning clock signal CL1 indicating a scanning period. As described above, it is constituted by a plurality of driver ICs. The scanning line driving circuit 3 receives a bias voltage necessary for the operation from the power supply circuit 5 and starts operation when a control signal DISP output from the control circuit 6 is activated, and the scanning line driving circuit 3 is deactivated. Operation is stopped by

The data line driving circuit 4 is provided with a display data DAT.
A according to the data clock signal CL2, and a plurality of drivers I so as to drive the plurality of data lines based on the display data DATA and the scan clock CL1.
C. The data line drive circuit 4 receives a bias voltage required for the operation from the power supply circuit 5 and starts operation when the control signal DISP output from the control circuit 6 is activated.
The operation is stopped by being deactivated.

The power supply circuit 5 receives a DC voltage VDD supplied from an external device as a driving power supply for the display device,
It is configured to convert into various bias voltages for driving liquid crystal and to output the same, and for example, includes a DC-DC converter.

The control circuit 6 protects the scanning line driving circuit 3 and the data line driving circuit 4 in an unsteady state such as when power is turned on or when various signals (particularly the scanning clock signal CL1 or the like) are interrupted. In order to prevent the DC voltage from being continuously applied to the liquid crystal display 2, as shown in FIG. 2, it also functions as a voltage detecting means 61, an AND gate 62, and a means for detecting the presence / absence of the scanning clock signal CL1. A monostable multivibrator 63 and a D-type flip-flop 64 functioning as data holding means.

The voltage detecting means 61 detects whether or not the voltage VDD of the power supplied from the external device as the power supply for driving the display device is higher than a specified value (for example, a voltage value of about 70% of the voltage VDD). When the voltage VDD is equal to or lower than a specified value, a low-level signal is output.
Output level signal. Here, it is effective to prevent the chattering of the detection output, although the prescribed value has a slight hysteresis.

The AND gate 62 is connected to the voltage detecting means 6.
1 and the display control signal DI sent from the external device
The logical product of SPin is obtained and the output is supplied to the monostable multivibrator 63.

The monostable multivibrator 63 has a scanning clock signal CL1 connected to an input B triggered by a rising edge, and an output of the AND gate 62 connected to a clear terminal CLR. By holding the clear terminal CLR at the L level, the monostable multivibrator 63 holds its output Q at the L level. The monostable multivibrator 63 is triggered by the rising edge of the scan clock signal CL1 applied to the input B. Once triggered, the monostable multivibrator 63 keeps the output t for a certain period of time t high unless the clear terminal CLR is set to the L level.
Hold on level. The predetermined time t is equal to the external resistance RX.
And the time constant of the capacitor CX. Between a frame and the next frame, a scan clock C
In some cases, a retrace period of several to several tens times the period of L1 is set, and during this retrace period, the supply of the scan clock CL1 may be stopped. The output holding time t is desirably set slightly longer than the maximum retrace time set between frames. In this example, the output holding time t is about half the frame period (several m).
s).

The D-type flip-flop 64 has a frame terminal FLM and a clear terminal CL connected to the clock terminal CLK.
R, the output Q of the monostable multivibrator 63 is connected, and the data input D and the preset terminal P
R is connected to the voltage VDD and held at the H level. While the clear terminal CLR is held at the L level, the output Q is always held at the L level, and the clear terminal CLR is held at the L level.
Is held at the H level, the output Q is switched from the L level to the H level by the rise of the first frame signal FLM applied to the clock terminal CLK, and the H level is held.

Next, the operation of the above configuration will be described with reference to timing charts shown in FIGS.

First, a normal operation will be described with reference to FIG. When the power supply voltage VDD supplied from the external device rises and reaches the specified value, at time t1, the output of the voltage detecting means 61 switches from L level to H level. Thereafter, at a time point t2 when a predetermined period has elapsed, the scan clock signal CL1, the data clock signal CL2, and the data signal D
Signals such as ATA and a frame signal FLM are provided. At time t3 after a predetermined period elapses after the start of signal supply, the externally supplied display control signal DISPin switches from L level to H level to indicate the start of display. When the display control signal DISPin switches from L level to H level, the output of the AND gate 62 switches from L level to H level, and the output is given to the clear terminal CLR of the monostable multivibrator 63.

When the clear terminal CLR switches to the H level, the monostable multivibrator 63 is triggered by the rising edge of the scan clock signal CL1 applied to the input B, and switches its output from the L level to the H level. After the trigger, the output Q is set to H for a certain period of time.
Hold on level. Since the fixed time t is set slightly longer than the maximum retrace time set between the frames, in the steady state, the next scanning clock signal CL1 is applied to the input B until the fixed time t elapses. Therefore, the monostable multivibrator 63 is triggered again, and by repeating this, holds the output Q at the H level.

When the output Q of the monostable multivibrator 63 switches from L level to H level, the D flip-flop 64 has its clear terminal CLR switched from L level to H level, but its output is held at L level. . Thereafter, at time t4 when the first frame signal FLM is applied to the clock terminal CLK, the D flip-flop 6
4 is switched from L level to H level. The output Q of the D flip-flop 64 is used as a control signal DIS for activating the scanning line driving circuit 3 and the data line driving circuit 4.
By using P, when the output Q of the D flip-flop 64 switches from L level to H level,
The operation of the scanning line driving circuit 3 and the data line driving circuit 4 can be started.

At the end of the display, the display control signal DISPin
Is switched from H level to L level at time t5,
Monostable multivibrator 63, D flip-flop 6
4 are simultaneously switched from the H level to the L level, the control signal DISP changes to the L level, and the scanning line driving circuit 3 and the data line driving circuit 4 stop their operations, thereby completing the normal end processing. Done.

Next, an operation when an unsteady state occurs after the display is started will be described with reference to FIG. First, a case where the supply of the scanning clock signal CL1 is stopped halfway will be described. When the supply of the scanning clock signal CL1 is stopped during the scanning, the switching of the scanning line is stopped, and the specific scanning line remains selected, and the voltage application is concentrated on the portion along the specific scanning line. However, an overload is applied to the display element (in this case, the liquid crystal in a specific portion).

However, when the supply of the scanning clock signal CL1 is stopped during the scanning, for example, at time t17, the input to the input B is stopped by the monostable multivibrator 63. Q is H
Switching from level to L level. The D flip-flop 64 also has its clear terminal CLR switched from the H level to the L level due to a change in the output Q of the monostable multivibrator 63, and the output Q switches from the H level to the L level at time t18. As a result, the control signal DISP given to the scanning line driving circuit 3 and the data line driving circuit 4 for controlling the operation becomes L level, and the scanning line driving circuit 3 and the data line driving circuit 4 are deactivated. As a result, it is possible to prevent the display 2 from being turned off and applying an overload to a specific portion.

Thereafter, at time t19, the scanning clock signal CL
When the supply of 1 is resumed, the monostable multivibrator 6
3 is triggered by the scanning clock signal CL1, and its output Q switches from L level to H level. However, the D flip-flop 64 outputs the frame signal FL
Until M arrives, its output Q is kept at L level. When the first frame signal FLM arrives at time t20, the output Q of the D flip-flop 64 changes from L level to H level.
Switch to level. Therefore, the scan clock signal CL1
After a lapse of a predetermined time from the restart of the supply of data, the control signal DISP is supplied to the scanning line driving circuit 3 and the data line driving circuit 4. In this way, by using the frame signal FLM having the longest cycle for switching the output of the D flip-flop 64, the control signal DISP is less affected by the output fluctuation of the monostable multivibrator 63.

When the voltage of the power supply VDD supplied from the outside drops below the specified value on the way (time t10), or when the display control signal DISPin switches to the L level on the way (time t14), By switching the output of the AND gate 62 from H level to L level,
Monostable multivibrator 63, D flip-flop 6
4 can be immediately switched from H level to L level. As a result, the control signal DISP given to the scanning line driving circuit 3 and the data line driving circuit 4 can be switched to the L level, and the display 2 can be kept in the off state.

Then, when the voltage of the power supply VDD recovers to a specified value or more at time t11, the output of the AND gate 62 switches from L level to H level, and the output Q of the monostable multivibrator 63 switches from L level to H level. However, the output Q of the D flip-flop 64 holds the L level. The output Q of the D flip-flop 64 switches from the L level to the H level at the time t12 when the next frame signal FLM arrives. Similarly, when the display control signal DISPin returns to the H level at time t15, the output of the AND gate 62 switches from the L level to the H level, and the output Q of the monostable multivibrator 63 switches from the L level to the H level. Output Q of flip-flop 64 holds L level. The output Q of the D flip-flop 64 is
At time t16 when the next frame signal FLM arrives, the level is switched from L level to H level.

Therefore, the power supply VDD and the display control signal DISP
After the recovery of the signal “in” and the lapse of a predetermined time, the control signal DISP is supplied to the scanning line driving circuit 3 and the data line driving circuit 4. In this way, by using the frame signal FLM having the longest cycle for switching the output of the D flip-flop 64, the control signal DISP is less affected by the output fluctuation of the monostable multivibrator 63. In particular,
Since the power supply VDD and the display control signal DISPin easily cause a chattering phenomenon, which easily causes the output fluctuation of the monostable multivibrator 63, the D flip-flop 64 is effective to prevent the fluctuation of the control signal DISP due to the output fluctuation. It is.

In the above embodiment, the control signal DIS for activating the scanning line driving circuit 3 and the data line driving circuit 4 is used.
The reason for using the output Q of the D flip-flop 64 instead of the output Q of the monostable multivibrator 63 as P is as follows.

When the input to the clear terminal CLR of the monostable multivibrator 63 becomes L level, the output Q also becomes L level, so that the output of the AND gate 62 connected to the clear terminal CLR is given from the outside. If the output Q fluctuates at a high frequency due to the chattering of the power supply voltage VDD or the display control signal DISPin, the output Q may fluctuate at a high frequency in conjunction therewith. The output of the monostable multivibrator 63 which fluctuates at a high frequency as described above is output to the control signal DISP.
When applied to the scanning line driving circuit 3 and the data line driving circuit 4, the input / output current of the power supply system portion of the IC constituting the scanning line driving circuit 3 and the data line driving circuit 4 increases, and burnout of the circuit pattern and the transistor The problem of destruction of functions may occur.

Therefore, as in the above embodiment, the output Q of the monostable multivibrator 63 is connected to the D flip-flop 6.
4 is used as the clock of the D flip-flop 64, by using the frame signal FLM having the longest cycle among the clock signals used in the display, so that the variation cycle of the control signal DISP is equal to the frame signal FLM. , A longer cycle can be set, and the above-described fluctuation at high frequencies can be suppressed. As a result, it is possible to eliminate the adverse effect on the driving IC as described above.

However, when no chattering of the externally applied power supply voltage VDD or the display control signal DISPin occurs, or when the driving IC controls the control signal D
In the case of a structure that can cope with high-frequency fluctuations of the ISP, the output Q of the monostable multivibrator 63 may be changed to a control signal for activating the scanning line driving circuit 3 and the data line driving circuit 4 as necessary. It can also be used as a DISP.

[0033]

As described above, according to the present invention, the display device and its driving circuit can be reliably protected even if an abnormality occurs in the control sequence, and the display operation can be performed more reliably. It can be. In particular, it is possible to prevent an overload occurring in a specific portion due to the stoppage of the selection of the scanning line, thereby protecting the display and its driving circuit. Further, a circuit for the protection can have a simpler configuration. As a result, it is possible to maintain good display quality of the display.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a liquid crystal display device showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a main part of the control circuit of the embodiment.

FIG. 3 is a time chart for explaining the operation of the embodiment.

FIG. 4 is a time chart for explaining the operation of the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Liquid crystal display 3 Scan line drive circuit 4 Data line drive circuit 5 Power supply circuit 6 Control circuit 61 Voltage detection means 62 AND gate 63 Monostable multivibrator 64 D-flip-flop

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/36 G02F 1/133 505

Claims (4)

(57) [Claims] 1. A display device in which a plurality of scanning lines and a plurality of data lines are arranged in a matrix and pixels are formed at intersections thereof, and the plurality of scanning lines are formed by a periodic frame signal indicating the start of a frame. A scanning line driving circuit for starting scanning of the scanning line and sequentially selecting scanning lines by a scanning clock signal indicating a scanning period, a data line driving circuit for driving the plurality of data lines based on display data, and the scanning line driving circuit in the display device and a control circuit for outputting an active signal for enabling the operation to the data line driving circuit and said control circuit includes a driving power source conductive of said display device
Voltage detection means for detecting whether the pressure is above a specified value
And the output of this detection means and the display system sent from outside
AND means for outputting a logical product of control signals;
Lock signal to the trigger input terminal and
Monostable multivibrator with output connected to clear terminal
And the output of the monostable multivibrator is
A display device, wherein the display device is used as an activation signal . 2. An output holding device for a monostable multivibrator.
Time longer than the maximum retrace interval set between frames.
The display device according to claim 1, wherein the display device is set to be long.
Place. 3. The control circuit according to claim 1, wherein the clock terminal has a frame.
And supply the clear signal to the monostable multivibrator.
A flip-flop that supplies the output of the
The flip-flop has its clear terminal held at L level.
The output is held at the L level while the clear terminal is
When held at H level, the first
Whether the output is L level by the rising edge of the frame signal
Switch to H level and hold H level
The display device according to claim 1. 4. The display according to claim 1, wherein said display is a liquid crystal display.
The display device according to claim 1, wherein: