JP2000098339A - Liquid crystal display panel scanning line driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To start excellently the display operation of a liquid crystal display panel and to prevent an element destruction when a power source is turned on even when the storage state of a D flip-flop when the power source of the liquid crystal display panel was turned off in the last time is random. SOLUTION: When a first high potential side source VDD1 and a second high potential side source VDD2 are raised by power source supplying, a reset signal is outputted from an output terminal 34 to all D flip-flops FF0-FFn. Then, when a second low potential side source VSS2 is lowered together with the second high potential side source VDD2, a switching element of an N channel MOS-FET is turned on, and the output terminal 34 is made minus potential, and the reset is released, and a shift register 10 is activated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel scanning line driver, and more particularly to a technique of power-on reset for a shift register.

[0002]

2. Description of the Related Art A liquid crystal display panel scanning line driver is generally used.
It comprises a shift register having a plurality of power supply inputs, a plurality of flip-flops for a plurality of scan electrode lines, and a buffer. By the output shift operation of the shift register, a plurality of scan electrode lines are sequentially activated, and the display screen of the liquid crystal display panel is scanned in the vertical direction.

[0003]

Each of the plurality of flip-flops in the shift register has a memory function. Therefore, the state when the power supply of the liquid crystal display panel was turned off last time remains stored in the flip-flop. Which D flip-flop is output "H" and which flip-flop is output "L"
This randomly changes depending on the power-off timing. Therefore, when the power supply of the liquid crystal display panel is turned on next time, the internal logic of the shift register becomes random, and the circuit state of the shift register becomes indefinite, which adversely affects the display of the liquid crystal display panel. is there. In some cases, elements such as an LSI constituting the shift register and the buffer circuit may be destroyed.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to solve the problem of screen display at power-on.

[0005]

SUMMARY OF THE INVENTION A liquid crystal display panel scanning line driver according to the present invention clears all of a plurality of flip-flops in a shift register which outputs to a scanning electrode line group of a liquid crystal display panel when power is turned on. Things. Turn off the power of the LCD panel last time
Even if the state at the time of setting F is randomly stored in a plurality of flip-flops, when the power of the liquid crystal display panel is next turned on, all the flip-flops are reset once without fail. The display operation of the panel is started well as expected.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A liquid crystal display panel scanning line driver according to claim 1 of the present invention is configured so that all of a plurality of flip-flops constituting a shift register are all cleared when power is turned on. . Conventionally, the liquid crystal display panel scanning line driver did not have a power-on reset function. However, the present invention has a power-on reset function, so that when the power to the liquid crystal display panel is turned on, the display operation is not disturbed as expected. Can be started well. Further, the possibility of destruction of elements such as an LSI constituting the shift register and the buffer circuit can be greatly reduced.

According to a second aspect of the present invention, a liquid crystal display panel scanning line driver according to the first aspect outputs a reset signal to all flip-flops based on power-on, and outputs a reset signal immediately thereafter. The configuration includes a power-on reset circuit for canceling. When the power is turned on, the shift register is activated after it is all cleared, so that an initial malfunction in display on the liquid crystal display panel can be prevented and the reliability of circuit components can be improved.

According to a third aspect of the present invention, in the liquid crystal display panel scanning line driver according to the second aspect, the power-on reset circuit includes a resistor connected to the first high-potential-side power supply, and a resistor connected to the first high-potential-side power supply. It comprises a switching element inserted between the power supply and a potential side power supply, and an output terminal connected to a connection point between the resistor and the switching element. This is described in more detail in claim 4 below.
That is, in the liquid crystal display panel scanning line driver according to claim 4 of the present invention, the power-on reset circuit according to claim 3 is configured such that the power-on reset circuit includes a resistor connected to a positive power supply terminal to which the first high-potential-side power is applied. A drain of an N-channel switching element is connected, a gate of the switching element is connected to a ground terminal to which a first low-potential-side power supply is applied, and a second low-potential-side power supply is applied to a source of the switching element. Negative power supply terminal is connected, and after the high potential side power supply is
The second high-potential power supply and the second low-potential power supply are both turned off while keeping the potential difference between them substantially constant, so that the switching element is made conductive. When the power is turned on, the power-on reset circuit is activated first. First, the first high-potential-side power supply is turned on. At this time, since the switching element is kept OFF, an “H” level reset signal is output from the output terminal to all the flip-flops to completely shift the shift register. clear. Next, the potential of the first low-potential power supply of the gate is made relatively higher than that of the second low-potential power supply by turning off the second low-potential power supply of the source, and the switching element is turned on. By doing so, the output of the reset signal is released. At this time, the potential of the output terminal becomes the second low potential side power supply level, and the active state of the flip-flop can be reliably guaranteed. Since the second high-potential-side power supply is turned off together with the second low-potential-side power supply, an excessive load is not imposed on the switching element that continues to be in the ON state thereafter.

Hereinafter, specific embodiments of a liquid crystal display panel scanning line driver with a power-on reset circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a liquid crystal display panel scanning line driver. This liquid crystal display panel scanning line driver 1
00 is a power-on reset circuit 30 that clears all D flip-flops of the shift register 10 when the power is turned on, in addition to the shift register 10 and the buffer circuit 20.
It has. The power-on control circuit 40 supplies the first high-potential power supply VDD1, the first low-potential power supply VSS1, and the second low-potential power supply VSS to the power-on reset circuit 30 according to a predetermined power sequence based on the input of the power-on detection signal S _ON . Is sequentially output from the high-potential-side power supply VDD2 and the second low-potential-side power supply VSS2. As an example of the voltage level, VDD1 is 2.7 to 5.5 V, VSS
1 is 0V (ground GND), VSS2 is -5 to -3
V and VDD2 are equal to VDD1 (2.7 to 2.7) with respect to VSS2.
5.5V). Also, VDD1, VSS
1 is used for a logic input circuit, and the input signal is further level-shifted to VDD2 and VSS2,
2. VSS2 is a power supply for operating an internal logic circuit.

FIG. 2 is a circuit diagram of the power-on reset circuit 30. The power-on reset circuit 30 is configured as follows. One end of a resistor R ₀ is connected to the positive power supply terminal 31, and the other end of the resistor R ₀ is connected to the drain of a switching element Q ₀ composed of an enhancement type N-channel MOS-FET. The source of the switching element Q ₀ is connected to the negative power supply terminal 32, and the gate is connected to the ground terminal 33. The drain of the switching element Q ₀ , that is, the connection point with the resistor R ₀ is connected to the output terminal 34. The positive power supply terminal 31 of the power-on reset circuit 30 can be connected to the line of the second high-potential power supply VDD2 of the power-on control circuit 40, and the minus power supply terminal 32 is connected to the power-on control circuit 40.
And the ground terminal 33 is connectable to the line of the first low-potential power supply VSS1 of the power-on control circuit 40. The output terminal 34 of the power-on reset circuit 30 is connected to all the D flip-flops F in the shift register 10.
It is connected to the F ₀ to ff _n of the reset terminal R.

[0012] In the shift register 10 is driven by the second high-potential power supply VDD2 and the second low-potential power supply VSS2, data input terminal D of the first-stage D flip-flop FF ₀ is the first high-potential-side The power supply and the input signal having the amplitude of the first low-potential power supply are connected to the drive signal input terminal 11 which is level-shifted to the amplitudes of the second high-potential power supply VDD2 and the second low-potential power supply VSS2. About the steps,
The output terminal Q of the Q output of the previous stage of the D flip-flop FF _i
There is connected to the input terminal of the buffer B _i of the next D flip-flop FF i _{+ 1} data input terminal D and the corresponding buffer circuit 20. A clock signal input terminal 12 is commonly connected to the active low type clock input terminals CK of all the D flip-flops FF _{0 to} FF _n . Each of the buffers B _{0 to} B _n of the buffer circuit 20 corresponds to a scanning electrode line Y ₀ to a liquid crystal display panel (not shown).
It is connected to Y _n.

Next, the operation of the liquid crystal display panel scanning line driver 100 configured as described above will be described with reference to the timing chart of FIG. When the power to the liquid crystal display panel is turned off, the power-on control circuit 40
, The first high-potential power supply VDD1, the first low-potential power supply VSS1, the second high-potential power supply VDD2, and the second low-potential power supply VSS2 0V. Therefore, in the power-on reset circuit 30, the potentials of the positive power supply terminal 31, the ground terminal 33, and the negative power supply terminal 32 are all 0V. The gate of the switching element Q ₀ - source voltage is also at 0V, the switching element Q ₀ is in the OFF state. As a result, the output terminal 34 of the power-on reset circuit 30 maintains the zero level.

When the power to the liquid crystal display panel is turned on, a power-on detection signal S _ON is input to the power-on control circuit 40, and the power-on control circuit 40 sends a first high potential to the power-on reset circuit 30. A power supply VDD1, a first low-potential power supply VSS1, a second high-potential power supply VDD2, and a second low-potential power supply VSS2 are supplied. A first high-potential-side power supply VDD1 is supplied. This is the state at time t _0. At time t _0, a second low-potential-side power supply VSS2 is supplied to the negative power supply terminal 32 connected to the source of the switching element Q ₀ is 0V, since the ground terminal 33 connected to the gate is also at 0V, the switching element Q ₀ Keep the OFF state. The ground terminal 33 always keeps 0V.

[0015] According to the power-on control circuit 40 is followed by a predetermined power supply sequence, the second high-potential power supply VDD2 at time t ₁ raises the "H" level. As a result, the positive power supply terminal 31 becomes “H” level, and at this time, the switching element Q ₀ is OFF, so that the potential of the positive power supply terminal 31 is reduced by the resistance R _{0 at} the output terminal 34. An H level voltage is output. The “H” level signal from the output terminal 34 is output to the shift register 10 as a reset signal. That is, the “H” level reset signal from the output terminal 34 of the power-on reset circuit 30 is input to the reset terminals (clear terminals) of all the D flip-flops FF _{0 to} FF _n of the shift register 10 and all the D flip-flops FF _{0 to} FF _n are reset. That is, the shift register 10 is all cleared. That is, the outputs of the output terminals Q of all the D flip-flops FF _{0 to} FF _n become “L” level, and the buffer circuit 20
All scan electrode lines at the output terminal that is, the liquid crystal display panel of all the buffers B ₀ .about.B _n in Y ₀
ＹY _n are initially reset to “L” level. As described above, it is important to forcibly reset all the scan electrode lines to the "L" level once when the power is turned on.

[0016] Subsequently, the power-on control circuit 40 is gradually lowered from the time t ₂ and the second high-potential power supply VDD2 and the second low-potential power supply VSS2 according to a predetermined power supply sequence. As a result, in the power-on reset circuit 30, while the potential difference between the positive power supply terminal 31 and the negative power supply terminal 32 is kept constant, the potential of the gate of the switching element Q ₀ connected to the ground terminal 33 becomes negative. relatively raised with respect to the potential of the source that is connected to the power supply terminal 32, gate - when source voltage (VSS1-VSS2) exceeds a threshold level, i.e. at time t _3, the switching element Q ₀ is oN I do. As a result, the potential of the output terminal 34, which has been close to the second high-potential power supply VDD2 connected to the plus power supply terminal 31, has become substantially equal to the potential of the second low-potential power supply VSS2.

Time t_Three From time t_Four To continue
And the second high potential connected to the positive power supply terminal 31
Side power supply VDD2 and minus power supply terminal 32
And the second low-potential-side power supply VSS2 further drops gradually.
The positive power supply terminal 31 is connected to the second high potential side power supply V
DD2 becomes a predetermined positive reference potential VDD2th.
The negative power supply terminal 32 is connected to a second low-potential-side power supply VSS2.
At a predetermined negative reference potential VSS2th. plus
Is slightly higher than 0 V from 0 V.
It is set as follows. The potential of the output terminal 34 is also at the second low level.
It continues to drop together with the potential side power supply VSS2 at time t_Four In
And stabilized at the negative reference potential VSS2th. Sand
The output terminal 34 of the power-on reset circuit 30
At the eggplant level, at time t_Three Up to shift register 10
All D flip-flops FF ₀ ~ FF_n Giving to
Release the reset signal, and set the D flip-flop FF₀ ~
FF_n Switch from its all clear state to the active state.
I will replace it.

In the present embodiment, since the power-on reset circuit 30 as described above is incorporated in the liquid crystal display panel scanning line driver 100, the following effects are exhibited. All D flip-flop FF ₀ to ff _n in the shift register 10 is has the function of memory, and while the state where the OFF the liquid crystal display panel to the last stored in the D flip-flop FF ₀ to ff _n Even if the storage state is extremely random according to the power-off timing, the power-on reset circuit 30 operates the power-on reset circuit 30 as described above when the power of the liquid crystal display panel is next turned on. Immediately after turning on, all D flip-flops FF _0-
After the FF _n is securely reset and the shift register 10 is all cleared, each of the D flip-flops FF _{0 to} FF
_{Since n} transitions to the active state, when the power of the liquid crystal display panel is turned on, the internal logic of the shift register 10 is forcibly initialized to the same all-clear state at power-on. Therefore, the display operation of the liquid crystal display panel is started well as expected. Therefore, the possibility of destruction of the LSI constituting the shift register 10 and the buffer circuit 20 can be greatly reduced.

Since the operation of the shift register 10 is the same as that of the prior art, a brief description will be given here. When a drive signal is input from the drive signal input terminal 11, every time a clock signal is input from the clock signal input terminal 12, each of the D flip-flops FF ₀ to FF ₀ to
The output of the FF _n is gradually switched to successively "H" level. That is, the output terminal Q to "H" level of the D flip-flop FF ₀ at first one of the clock signal, the output terminal Q to "H" level of the D flip-flop FF ₁ in second clock signal, such as be a condition , thereby, the scan electrode lines Y ₀ to Y _n via the respective buffer B ₀ .about.B _n
Are sequentially activated. In this case, always only the first scan electrode lines Y ₀ as the first driven lines intended as hereinafter that arranges the scan electrode lines Y ₁ to Y _n in a row in the Y direction on the liquid crystal display panel In this order, the line can be driven purely.

[0020] Incidentally, FIG. 4 is a circuit configuration of the power-on reset circuit 30 in the case of using a MOS-FET of a P-channel as a switching element Q _1, the operation of this case is as in the timing chart of FIG.

[0021]

According to the liquid crystal display panel scanning line driver according to the present invention, regardless of the storage state of the plurality of flip-flops when the power supply was last turned off, the power supply of the liquid crystal display panel is turned on next. In this case, by completely clearing the shift register, the display operation of the liquid crystal display panel can be started satisfactorily as expected, and destruction of elements can be prevented as much as possible.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a liquid crystal display panel scanning line driver according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a power-on reset circuit according to the embodiment;

FIG. 3 is a timing chart illustrating operation of a power-on reset circuit according to the embodiment;

FIG. 4 is a circuit diagram of a power-on reset circuit according to another embodiment;

FIG. 5 is a timing chart illustrating operation of a power-on reset circuit according to another embodiment.

[Explanation of symbols]

Reference Signs List 10 shift register 11 drive signal input terminal 12 clock signal input terminal 20 buffer circuit 30 power-on reset circuit 31 positive power supply terminal 32 negative power supply terminal 33 ground terminal 34 ... output terminal 40 ...... power-on control circuit 100 ...... liquid crystal display panel scan line driver Q ₀ ...... switching elements R ₀ ...... resistance FF ₀ ~FF _n ...... D flip-flop B ₀ .about.B _n ...... buffer Y ₀ ... Y _n ... Scanning electrode line VDD1... First high-potential-side power supply VDD2... Second high-potential-side power supply VSS1... First low-potential-side power supply VSS2.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NC10 NC16 NC21 NC22 ND34 ND60 5C006 AF67 BB11 BC03 BF03 BF06 BF34 FA16 FA33

Claims (4)

[Claims] 1. A liquid crystal display panel scanning line driver configured to clear all of a plurality of flip-flops constituting a shift register when power is turned on. 2. The liquid crystal display panel according to claim 1, further comprising a power-on reset circuit for outputting reset signals to all flip-flops upon power-on, and immediately releasing the reset signal output. Wire driver. 3. A power-on reset circuit comprising: a resistor connected to a high-potential-side power supply; a switching element inserted between the resistor and the low-potential-side power supply; and a connection point between the resistor and the switching element. The liquid crystal display panel scanning line driver according to claim 2, further comprising an output terminal connected thereto. 4. A power-on reset circuit, wherein a drain of an N-channel switching element is connected via a resistor to a positive power supply terminal to which a high-potential-side power supply is applied, and a gate of the switching element is connected to a first low-potential side. A ground terminal to which power is applied is connected, a negative power supply terminal to which a second low-potential-side power is applied is connected to the source of the switching element, and after the high-potential-side power is turned on with power-on, 4. The liquid crystal display according to claim 3, wherein the switching element is turned on by lowering both the high-potential-side power supply and the second low-potential-side power supply while keeping the potential difference between them substantially constant. Panel scan line driver.